- 22 Apr, 2020 40 commits
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Anthony Koo authored
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jaehyun Chung authored
[Why] HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation were only added to dcn20. [How] Add hubp cursor position calculation changes to dcn10. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] We expect to be able to perform immediate flipping without having to recalculate and update all the watermarks. There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such that we get a urgency value of 0 for frac_urg_bw_flip because we're explicitly passing in a value of "false" for requiring immediate flip support into the DLG calculation. [How] Always pass in true into the calculation. With this we get a correct non-zero value for frac_urg_bw_flip. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This prevents dpcd access on virtual links. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Anthony Koo authored
[Why] without destroy it is causing a memory leak [How] destroy panel on link destruct Signed-off-by:
Wyatt Wood <Wyatt.Wood@amd.com> Acked-by:
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Paul Hsieh authored
[Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Anthony Koo authored
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by:
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Anthony Koo authored
[Why] Backlight adjustment is tied to a specific display. So make the calls target a link rather than making it a global state. [How] make all backlight calls link based Signed-off-by:
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Sung Lee authored
[WHY] In certain conditions with low pixel clock, some values in DML may go past the max due to margining for latency hiding. This causes assertions to get hit. [HOW] If the pixel clock is low and some values are high, cap it to the max. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] - Driver does not recognize new definitions of psr states. - Internal tool is required for checking if psr is active. [How] - Parse psr state correctly so that driver will recognize psr state. - Add visual confirmation that psr is active using existing mechanisms. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Aric Cyr authored
Don't skip MPCC tree updates if requested. Signed-off-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Aric Cyr authored
Some cases were incorrectly reporting the wrong visual confirm, even though they were working as expected. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Color blending for NV12 formats is incorrect because we're using the predefined SRGB degamma. [How] Calculate the correct input transfer function for degamma from the color module depending on what the actual surface format is. Signed-off-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Haiyi Zhou authored
[Why] Certain displays may experience blanking if infopacket max range does not equal nominal refresh rate. [How] Add additional infopacket versions to program range to full or forced range in freesync states. This does not change the vrr logic. Signed-off-by:
Haiyi Zhou <haiyi.zhou@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] On ASIC without ABM support (most dGPU) we run into a null pointer dereference when attempting to set the backlight level. [How] This function requires ABM, so fix up the condition to only allow DMCU to be optional. Signed-off-by:
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Dmytro Laktyushkin authored
We need to set up stream even with virtual displays when running diags. Signed-off-by:
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Sung Lee authored
[Why]: Some inputs to dml_ceil have it dividied by int which causes a truncation. This loss of precision means the ceil function becomes redundant and does not round up. [How]: Cast parameter to float before division. Signed-off-by:
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Sung Lee authored
[WHY]: Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead to a large number causing an assert to get hit. In VBA, this value is 0 when DCC is disabled. [HOW]: Set value to 0 to avoid hitting the assert. Signed-off-by:
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Wenjing Liu authored
[why] Optc needs to know if timing is enabled with ODM or DSC before computing crc. Otherwise value computed will be inaccurate. Before this change, the CRC computed without ODM is not equal to the CRC computed with ODM for the same timing. This is unexpected as we are driving the same timing despite of the underlaying hardware setup to achieve it. This is caused by missing hardware programming sequence to support it. [how] Add the new programming sequence based on hardware guide. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Jinze Xu authored
[Why] Some mst dock can't translate DP to HDMI properly. [How] Bypass YCbCr timings on specific MST device. Signed-off-by:
Jinze Xu <jinze.xu@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] A NULL ramp is a valid configuration for passing into mod_color_calculate_degamma_params but we'll hit a NULL pointer if we do so. We need this in order to get the right transfer function to do degamma on NV12 formats where we aren't supplied with a custom user degamma. [How] Add the NULL check. Signed-off-by:
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Wyatt Wood authored
[Why] As it stands, psr has feature flags in dm, stream, and link. Most are not defined well enough, and different dm layers have different uses for these same flags. [How] We define a new structure called psr_settings in dc_link that will hold the following psr feature flags: psr_feature_enable - psr is supported psr_allow_active - psr is currently active psr_version - internal psr version supported psr_frame_capture_indication_req psr_sdp_transmit_line_num_deadline The last two flags were moved out of the power module for the purposes of consolidating psr flags. Their use is already well-defined. Psr caps reported by sink will also be stored in dc_link, in dpcd_caps.psr_caps. Signed-off-by:
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Stylon Wang authored
[Why] Plane-level gamut remap is not enabled in DM, which is necessary to support CTM as a plane-level property. [How] Enable gamut remap in DM. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Set backlight calls to firmware are are being prevented by dmcu == null check. Dmcu is expected to be null in this case. [How] Only prevent call if dmcu and abm are null. Also rename variable 'use_smooth_brightness' to 'fw_set_brightness' as it's more appropriate. Signed-off-by:
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Wyatt Wood authored
[Why] Since x86 and dmcub are both little endian, byte swapping isn't necessary. Dmcu requires byte swapping as it is big endian. [How] Add flag to function definitions to determine if byte swapping is necessary. Signed-off-by:
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Joshua Aberback authored
[Why] The HUBBUB watermark registers are in an area that cannot be power gated, but the HUBP copies of the watermark values are in areas that can be power gated. When we power on a pipe, it will not automatically take the HUBBUB values, we need to force propagation by writing to a watermark register. [How] - new HUBBUB function to re-write current value in a WM register - touch WM register after enabling the plane in program_pipe Signed-off-by:
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Wyatt Wood authored
[Why] Dmcu init fw call has some logic to initialize abm values. Since this doesn't exist on dmcub, must find a proper place for it in the abm sequence. [How] Move enable fractional pwm call. Signed-off-by:
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Wyatt Wood authored
[Why] Porting abm from dmcu to dmcub missed one register write. [How] Add this register write in the SetBacklightLevel sequence. Signed-off-by:
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Dale Zhao authored
[Why]: Renoir's pipe VM flags are not correctly updated if pipe strategy has changed during some scenarios. It will result in watermarks mistakenly calculation, thus underflow and garbage appear. [How]: Correctly update pipe VM flags to pipes which have been populated. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Signed-off-by:
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Zhan Liu authored
[Why] Aconnector is not necessary to be NULL in order to read dpcd successfully. Actually if we rely on checking aconnector here, we won't be able to turn off all displays before doing display detection. That will cause some MST hubs not able to light up. [How] Remove aconnector check when turning off all displays at hardware initialization stage. Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Signed-off-by:
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YueHaibing authored
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c:1017:50: warning: ‘video_optimized_pixel_rates’ defined but not used [-Wunused-const-variable=] static const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { ^~~~~~~~~~~~~~~~~~~~~~~~~~~ commit d8cd587d ("drm/amd/display: removing MODULO change for dcn2") left behind this unused vairable, remove it. Signed-off-by:YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Jason Yan authored
Fix the following gcc warning: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega10_powertune.c:710:46: warning: ‘PSMGCEDCThresholdConfig_vega10’ defined but not used [-Wunused-const-variable=] static const struct vega10_didt_config_reg PSMGCEDCThresholdConfig_vega10[] = ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega10_powertune.c:654:46: warning: ‘PSMSEEDCThresholdConfig_Vega10’ defined but not used [-Wunused-const-variable=] static const struct vega10_didt_config_reg PSMSEEDCThresholdConfig_Vega10[] = ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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Jonathan Kim authored
Vega20 arbitrates pstate at hive level and not device level. Last peer to remote buffer unmap could drop P-State while another process is still remote buffer mapped. With this fix, P-States still needs to be disabled for now as SMU bug was discovered on synchronous P2P transfers. This should be fixed in the next FW update. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
Mirror what we do for i2c display buses. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
We were registering the aux device in the MST late_register rather than the regular one. v2: handle eDP as well Fixes: 405a1f90 ("drm/amdgpu/display: split dp connector registration (v4)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100Signed-off-by:
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Sandeep Raghuraman authored
Initialize thermal controller fields in the PowerPlay table for Hawaii GPUs, so that fan speeds are reported. Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by:
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James Zhu authored
This reverts commit 3fded222 This is work around for vcn1 only. Currently vcn1 has separate begin_use and idle work handle. Signed-off-by:
James Zhu <James.Zhu@amd.com> Tested-by:
changzhu <Changfeng.Zhu@amd.com> Reviewed-by:
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Guchun Chen authored
When running ras uncorrectable error injection and triggering GPU reset on sGPU, below issue is observed. It's caused by the list uninitialized when accessing. [ 80.047227] BUG: unable to handle page fault for address: ffffffffc0f4f750 [ 80.047300] #PF: supervisor write access in kernel mode [ 80.047351] #PF: error_code(0x0003) - permissions violation [ 80.047404] PGD 12c20e067 P4D 12c20e067 PUD 12c210067 PMD 41c4ee067 PTE 404316061 [ 80.047477] Oops: 0003 [#1] SMP PTI [ 80.047516] CPU: 7 PID: 377 Comm: kworker/7:2 Tainted: G OE 5.4.0-rc7-guchchen #1 [ 80.047594] Hardware name: System manufacturer System Product Name/TUF Z370-PLUS GAMING II, BIOS 0411 09/21/2018 [ 80.047888] Workqueue: events amdgpu_ras_do_recovery [amdgpu] Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
John Clements <John.Clements@amd.com> Signed-off-by:
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Kent Russell authored
Update the list with supported Arcturus chips, but disable for now until final list is confirmed. Ideally we can poll atombios for FRU support, instead of maintaining this list of chips, but this will enable serial number reading for supported ASICs for the time-being. Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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