1. 12 Apr, 2017 7 commits
    • Ray Jui's avatar
      clk: iproc: Remove redundant check · d5a0945f
      Ray Jui authored
      Remove the redundant check of 'rate' in the if statement of the
      'pll_set_rate' function
      Reported-by: default avatarDavid Binderman <dcb314@hotmail.com>
      Signed-off-by: default avatarRay Jui <ray.jui@broadcom.com>
      Fixes: 5fe225c1 ("clk: iproc: add initial common clock support")
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      d5a0945f
    • Michael Turquette's avatar
      Merge tag 'v4.12-rockchip-clk1' of... · 55798360
      Michael Turquette authored
      Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
      
      Pull rockchip clk driver updates from Heiko Stuebner:
      
        General rockchip clock changes for 4.12. Contains some new clock-ids
        as well as fixups of the clock-ids on rk3368 timers, which were unused
        and completely wrong (more and differently named timers).
        Also there is one new clock on rk3328 using the muxgrf type, a fix for
        pll enablement which should wait for the pll to lock before continuing,
        some more critical clocks and the rename of the rk1108 to rv1108, as the
        soc seems to have been using a preliminary name before its actual release.
        The plan is to have the driver changes (pinctrl, clk) go through the
        respective maintainer trees and once everything landed in mainline do
        the rename of the devicetree files. With the dts-include change in the
        clock rename, we also keep everything compiling and thus bisectability.
      
      * tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
        clk: rockchip: add pll_wait_lock for pll_enable
        clk: rockchip: rename RK1108 to RV1108
        dt-bindings: rk1108-cru: rename RK1108 to RV1108
        clk: rockchip: mark some rk3368 core-clks as critical
        clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
        clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
        clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
        clk: rockchip: fix up rk3368 timer-ids
        clk: rockchip: add rk3328 clk_mac2io_ext ID
        clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
      55798360
    • Michael Turquette's avatar
      Merge tag 'clk-renesas-for-v4.12-tag2' of... · 0d4ae360
      Michael Turquette authored
      Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
      
      Pull Renesas clk driver updates from Geert Uytterhoeven:
      
        - Add support for the Clock Pulse Generator / Module Standby and
          Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
          differs from ES1.x in some areas.
        - Add IMR clocks for R-Car H3 and M3-W,
        - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
        - Small fixes and cleanups.
      
      * tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
        clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
        clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
        clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
        clk: renesas: cpg-mssr: Add support for fixing up clock tables
        clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
        clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
        clk: renesas: r8a7796: Reformat core clock table
        clk: renesas: r8a7795: Reformat core clock table
        clk: renesas: r8a7796: Correct name of watchdog clock
        clk: renesas: r8a7795: Correct name of watchdog clock
        clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
        clk: renesas: r8a7796: Add IMR clocks
        clk: renesas: r8a7795: Add IMR clocks
      0d4ae360
    • Stephen Boyd's avatar
      Merge branch 'clk-fixes' into clk-next · f37753e2
      Stephen Boyd authored
      * clk-fixes:
        clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
      f37753e2
    • Gabriel Fernandez's avatar
      clk: stm32f4: fix: exclude values 0 and 1 for PLLQ · ef189104
      Gabriel Fernandez authored
      0000: PLLQ = 0, wrong configuration
      0001: PLLQ = 1, wrong configuration
      ...
      0010: PLLQ = 2
      0011: PLLQ = 3
      0100: PLLQ = 4
      ...
      1111: PLLQ = 1
      
      Use divider table to exclude 0 and 1 values.
      
      Fixes: 83135ad3 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards")
      Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      ef189104
    • Stephen Boyd's avatar
      Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-next · 4641d6a5
      Stephen Boyd authored
      * 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm:
        clk: ti: convert to use proper register definition for all accesses
        clk: ti: dpll44xx: fix clksel register initialization
        clk: ti: gate: export gate_clk_ops locally
        clk: ti: divider: add driver internal API for parsing divider data
        clk: ti: divider: convert TI divider clock to use its own data representation
        clk: ti: mux: convert TI mux clock to use its internal data representation
        clk: ti: drop unnecessary MEMMAP_ADDRESSING flag
        clk: ti: omap4: cleanup unnecessary clock aliases
        clk: ti: enforce const types on string arrays
        clk: ti: move omap2_init_clk_clkdm under TI clock driver
        clk: ti: add clkdm_lookup to the exported functions
        clk: ti: use automatic clock alias generation framework
        clk: ti: add API for creating aliases automatically for simple clock types
        clk: ti: add support for automatic clock alias generation
        clk: ti: remove un-used definitions from public clk_hw_omap struct
      4641d6a5
    • Leo Yan's avatar
      clk: hi6220: add debug APB clock · b0459491
      Leo Yan authored
      The debug APB clock is absent in hi6220 driver, so this patch is to add
      support for it.
      Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      b0459491
  2. 30 Mar, 2017 4 commits
    • Geert Uytterhoeven's avatar
      clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 · bb195306
      Geert Uytterhoeven authored
      Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28.
      
      Add support for that, but retain the old behavior for R-Car H3 ES1.x and
      M3-W ES1.0 using a quirk.
      
      Inspired by a patch by Takeshi Kihara in the BSP.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
      bb195306
    • Geert Uytterhoeven's avatar
      clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 · 5573d194
      Geert Uytterhoeven authored
      The Clock Pulse Generator / Module Standby and Software Reset module in
      R-Car H3 ES2.0 differs from ES1.x in the following areas:
        - More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
        - Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
          SYS-DMAC, VIN, VSPB, VSPI,
        - Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
          USB3-IF1, VSPD3, VSPI2,
        - Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
      
      The goal is twofold:
        1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
           for now,
        2. Make it clear which code supports ES1.x, so it can easily be
           identified and removed later, when production SoCs are deemed
           ubiquitous.
      
      This is achieved by:
        - Updating the clock tables for the latest revision (ES2.0), but not
          removing clocks that only exist on earlier revisions (ES1.x),
        - Detecting the SoC revision at runtime using the new soc_device_match()
          API, and fixing up the clocks tables to match the actual SoC
          revision, by:
            - NULLifying core and module clocks of modules that do not exist,
            - Reparenting module clocks that have a different parent on ES1.x.
      
      Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      5573d194
    • Geert Uytterhoeven's avatar
      clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions · 89f1b1c6
      Geert Uytterhoeven authored
      Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as
      listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3
      Hardware User's Manual rev. 0.53E.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      89f1b1c6
    • Geert Uytterhoeven's avatar
      clk: renesas: cpg-mssr: Add support for fixing up clock tables · 48d0341e
      Geert Uytterhoeven authored
      The same SoC may have different clocks and/or module clock parents,
      depending on SoC revision.  One option is to use different sets of clock
      tables for each SoC revision.  However, if the differences are small, it
      is much more space-efficient to have a single set of clock tables, and
      fix those up at runtime instead.
      
      Hence provide three helpers:
        - Two helpers to NULLify core and module clocks that do not exist on
          some revisions (NULLified clocks are skipped during the registration
          phase),
        - One helper to reparent module clocks that have different clock
          parents.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      48d0341e
  3. 23 Mar, 2017 1 commit
  4. 22 Mar, 2017 3 commits
  5. 21 Mar, 2017 7 commits
  6. 20 Mar, 2017 2 commits
  7. 10 Mar, 2017 7 commits
  8. 08 Mar, 2017 9 commits