1. 30 May, 2014 13 commits
  2. 29 May, 2014 2 commits
  3. 28 May, 2014 25 commits
    • Paul Burton's avatar
      MIPS: Malta: CPS SMP by default · 32201453
      Paul Burton authored
      The CONFIG_MIPS_CPS SMP implementation should be able to handle all
      cases the CONFIG_MIPS_CMP implementation does, but without requiring
      bootloader assistance. It is also required in order to make use of
      features such as hotplug & cpuidle core power gating. Enable it by
      default for Malta configs that previously enabled the now deprecated
      CONFIG_MIPS_CMP, and disable the latter. The local version suffix "cmp"
      is removed rather than replaced with "cps" since there are other ways to
      tell that the CPS SMP implementation is in use (the "VPE topology" line
      in the boot log being one).
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      32201453
    • Paul Burton's avatar
      cpuidle: cpuidle-cps: add MIPS CPS cpuidle driver · d0508944
      Paul Burton authored
      This patch adds a cpuidle driver for systems based around the MIPS
      Coherent Processing System (CPS) architecture. It supports four idle
      states:
      
        - The standard MIPS wait instruction.
      
        - The non-coherent wait, clock gated & power gated states exposed by
          the recently added pm-cps layer.
      
      The pm-cps layer is used to enter all the deep idle states. Since cores
      in the clock or power gated states cannot service interrupts, the
      gic_send_ipi_single function is modified to send a power up command for
      the appropriate core to the CPC in cases where the target CPU has marked
      itself potentially incoherent.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      d0508944
    • Paul Burton's avatar
      cpuidle: declare cpuidle_dev in cpuidle.h · f08dbf8a
      Paul Burton authored
      Declaring this allows drivers which need to initialise each struct
      cpuidle_device at initialisation time to make use of the structures
      already defined in cpuidle.c, rather than having to wastefully define
      their own.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      f08dbf8a
    • Paul Burton's avatar
      MIPS: include cpuidle Kconfig menu · c095ebaf
      Paul Burton authored
      This patch simply includes the cpuidle Kconfig entries in preparation
      for cpuidle drivers used on MIPS systems.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      c095ebaf
    • Paul Burton's avatar
      MIPS: cpuidle wait instruction state · da9f970f
      Paul Burton authored
      Defines a macro intended to allow trivial use of the regular MIPS wait
      instruction from cpuidle drivers, which may simply invoke the macro
      within their array of states.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      da9f970f
    • Paul Burton's avatar
      MIPS: smp-cps: duplicate core0 CCA on secondary cores · 0155a065
      Paul Burton authored
      Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
      the boot CPU. This allows overrides of the CCA using the cca= kernel
      parameter to take effect on all CPUs for consistency.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      0155a065
    • Paul Burton's avatar
      MIPS: smp-cps: set a coherent default CCA · 33b68665
      Paul Burton authored
      This patch sets a default CCA suited for use with multi-core SMP on all
      current MIPS CPS based systems. It may still be overriden by the cca=
      argument on the kernel command line.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      33b68665
    • Paul Burton's avatar
      MIPS: smp-cps: prevent multi-core SMP with unsuitable CCA · 5c399f6e
      Paul Burton authored
      If the user or bootloader sets the CCA to a value which is not suited
      for multi-core SMP (ie. anything non-coherent) then limit the system to
      using only a single core and warn the user.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      5c399f6e
    • Paul Burton's avatar
      MIPS: smp-cps: hotplug support · 1d8f1f5a
      Paul Burton authored
      This patch adds support for offlining CPUs via hotplug when using the
      CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2
      things will happen:
      
        - If the CPU is part of a core which implements the MT ASE and there
          is at least one other VPE online within that core then the VPE will
          be halted by settings its TCHalt bit.
      
        - Otherwise if supported the core will be powered down via the CPC.
      
        - Otherwise the CPU will hang by executing an infinite loop.
      
      Bringing CPUs back online is then a process of either clearing the
      appropriate VPEs TCHalt bit or powering up the appropriate core via the
      CPC. Throughout the process the struct core_boot_config vpe_mask field
      must be maintained such that mips_cps_boot_vpes will start & stop the
      correct VPEs.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      1d8f1f5a
    • Paul Burton's avatar
      MIPS: pm-cps: add PM state entry code for CPS systems · 3179d37e
      Paul Burton authored
      This patch adds code to generate entry & exit code for various low power
      states available on systems based around the MIPS Coherent Processing
      System architecture (ie. those with a Coherence Manager, Global
      Interrupt Controller & for >=CM2 a Cluster Power Controller). States
      supported are:
      
        - Non-coherent wait. This state first leaves the coherent domain and
          then executes a regular MIPS wait instruction. Power savings are
          found from the elimination of coherency interventions between the
          core and any other coherent requestors in the system.
      
        - Clock gated. This state leaves the coherent domain and then gates
          the clock input to the core. This removes all dynamic power from the
          core but leaves the core at the mercy of another to restart its
          clock. Register state is preserved, but the core can not service
          interrupts whilst its clock is gated.
      
        - Power gated. This deepest state removes all power input to the core.
          All register state is lost and the core will restart execution from
          its BEV when another core powers it back up. Because register state
          is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
          implementation in order for the core to exit the state successfully.
      
      The code will detect which states are available on the current system
      during boot & generate the entry/exit code for those states. This will
      be used by cpuidle & hotplug implementations.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      3179d37e
    • Paul Burton's avatar
      MIPS: smp-cps: use CPC core-other locking · dd9233d0
      Paul Burton authored
      The core which the CPC core-other region relates to is based upon the
      core-local core-other addressing register. As its name suggests this
      register is shared between all VPEs within a core, and if there is a
      possibility that multiple VPEs within a core will attempt to access
      another core simultaneously then locking is required. This wasn't
      previously a problem with the only user being cpu0 during boot, but will
      be an issue once hotplug is implemented & may race with other users such
      as cpuidle.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      dd9233d0
    • Paul Burton's avatar
      MIPS: smp-cps: flush cache after patching mips_cps_core_entry · 0f4d3d11
      Paul Burton authored
      The start of mips_cps_core_entry is patched in order to provide the code
      with the address of the CM register region at a point where it will be
      running non-coherent with the rest of the system. However the cache
      wasn't being flushed after that patching which could in principle lead
      to secondary cores using an invalid CM base address.
      
      The patching is moved to cps_prepare_cpus since local_flush_icache_range
      has not been initialised at the point cps_smp_setup is called.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      0f4d3d11
    • Paul Burton's avatar
      MIPS: smp-cps: function to determine whether CPS SMP is in use · 68c1232f
      Paul Burton authored
      The core power down state for cpuidle will require that the CPS SMP
      implementation is in use. This patch provides a mips_cps_smp_in_use
      function which determines whether or not the CPS SMP implementation is
      currently in use.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      68c1232f
    • Paul Burton's avatar
      MIPS: smp-cps: rework core/VPE initialisation · 245a7868
      Paul Burton authored
      When hotplug and/or a powered down idle state are supported cases will
      arise where a non-zero VPE must be brought online without VPE 0, and it
      where multiple VPEs must be onlined simultaneously. This patch prepares
      for that by:
      
        - Splitting struct boot_config into core & VPE boot config structures,
          allocated one per core or VPE respectively. This allows for multiple
          VPEs to be onlined simultaneously without clobbering each others
          configuration.
      
        - Indicating which VPEs should be online within a core at any given
          time using a bitmap. This allows multiple VPEs to be brought online
          simultaneously and also indicates to VPE 0 whether it should halt
          after starting any non-zero VPEs that should be online within the
          core. For example if all VPEs within a core are offlined via hotplug
          and the user onlines the second VPE within that core:
      
            1) The core will be powered up.
      
            2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
               initialise the core.
      
            3) VPE 0 will start VPE 1 because its bit is set in the cores
               bitmap.
      
            4) VPE 0 will halt itself because its bit is clear in the cores
               bitmap.
      
        - Moving the core & VPE initialisation to assembly code which does not
          make any use of the stack. This is because if a non-zero VPE is to
          be brought online in a powered down core then when VPE 0 of that
          core runs it may not have a valid stack, and even if it did then
          it's messy to run through parts of generic kernel code on VPE 0
          before starting the correct VPE.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      245a7868
    • Paul Burton's avatar
      MIPS: uasm: add MT ASE yield instruction · d674dd14
      Paul Burton authored
      This patch allows use of the MT ASE yield instruction from uasm. It will
      be used by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      d674dd14
    • Paul Burton's avatar
      MIPS: uasm: add wait instruction · 53ed1389
      Paul Burton authored
      This patch allows use of the wait instruction from uasm. It will be used
      by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      53ed1389
    • Paul Burton's avatar
      MIPS: uasm: add sync instruction · 729ff561
      Paul Burton authored
      This patch allows use of the sync instruction from uasm. It will be used
      by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      729ff561
    • Paul Burton's avatar
      MIPS: uasm: add jalr instruction · 49e9529b
      Paul Burton authored
      This patch allows use of the jalr instruction from uasm. It will be used
      by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      49e9529b
    • Paul Burton's avatar
      MIPS: uasm: add a label variant of beq · 8dee5901
      Paul Burton authored
      This patch allows for use of the beq instruction with labels from uasm,
      much as bne & others already do. It will be used by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      8dee5901
    • Paul Burton's avatar
      MIPS: inst.h: define microMIPS wait op · f263839a
      Paul Burton authored
      The opcode for the wait instruction within POOL32AXf was missing. This
      patch adds it for use by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      f263839a
    • Paul Burton's avatar
      MIPS: inst.h: define microMIPS sync op · 7ed82ad1
      Paul Burton authored
      The opcode for the sync instruction within POOL32AXf was missing. This
      patch adds it for use by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      7ed82ad1
    • Paul Burton's avatar
      MIPS: inst.h: define MT yield op · 6f5bb424
      Paul Burton authored
      The opcode for the MT ASE yield instruction within the spec3 group was
      missing. This patch adds it for use by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      6f5bb424
    • Paul Burton's avatar
      MIPS: inst.h: define COP0 wait op · b0a3eae2
      Paul Burton authored
      The func field for the wait instruction was missing from inst.h - this
      patch adds it.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      b0a3eae2
    • Paul Burton's avatar
      MIPS: MT: define write_c0_tchalt macro · 27476f3b
      Paul Burton authored
      Define a macro to write to the current TCs TCHalt register. This will be
      used by a subsequent patch.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      27476f3b
    • Paul Burton's avatar
      MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entry · e2a9e5ad
      Paul Burton authored
      This is identical to kmap_coherent apart from the cache coherency
      attribute used for the TLB entry, so kmap_coherent is abstracted to
      kmap_prot which is then called for both kmap_coherent &
      kmap_noncoherent. This will be used by a subsequent patch.
      Suggested-by: default avatarLeonid Yegoshin <leonid.yegoshin@imgtec.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      e2a9e5ad