1. 12 May, 2016 4 commits
  2. 09 May, 2016 3 commits
    • Heiko Stuebner's avatar
      clk: rockchip: drop old_rate calculation on pll rate changes · 7e5385dc
      Heiko Stuebner authored
      Previously when everything happened in the set_rate callbacks itself we
      needed the old_rate value for the possible rate rollback, so that made
      it easy to also use it in the debug output.
      
      Now with the param-handling being done in separate functions, reading and
      recalculating the current pll rate only to use it in a debug message that
      won't get displayed in regular cases anyway is quite a waste.
      
      Therefore drop that value from the debug output. In the worst case that
      previous rate will have been displayed on the rate change before.
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      7e5385dc
    • Heiko Stuebner's avatar
      clk: rockchip: simplify GRF handling in pll clocks · c9c3c6ee
      Heiko Stuebner authored
      With the previous commit, the clock drivers now know at init time if the
      GRF regmap is available. That means if it isn't available then, it also
      won't become available later and we can therefore switch PLLs, that need
      the GRF for the lock-status, to read-only mode - similar behaviour as the
      aborting of rate changes we did before.
      
      This saves some conditionals on every rate change and we can also drop
      the rockchip_clk_get_grf function completely.
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      c9c3c6ee
    • Heiko Stuebner's avatar
      clk: rockchip: lookup General Register Files in rockchip_clk_init · 6f339dc2
      Heiko Stuebner authored
      In the distant past syscons were initialized pretty late and weren't
      available at the time the clock init ran. As the GRF is mainly needed
      for PLL lock-status checking, we had this lazy init that tried to grab
      the syscon on PLL rate changes and denied these changes if it was not
      available.
      
      These days syscons are available very early and recent addition to
      rockchip clocks, like the PLL clk_init actually also rely on them
      being available at that time, so there is no need to keep that lazy
      init around, as it will also result in some more simplifications in
      other parts of the clock-code.
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      6f339dc2
  3. 08 May, 2016 1 commit
  4. 06 May, 2016 12 commits
  5. 03 May, 2016 4 commits
  6. 02 May, 2016 2 commits
    • Stephen Boyd's avatar
      Merge tag 'tegra-for-4.7-clk' of... · 5bc75324
      Stephen Boyd authored
      Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
      
      Pull tegra clk driver changes from Thierry Reding:
      
      This set of changes contains a bunch of cleanups and minor fixes along
      with some new clocks, mainly on Tegra210, in preparation for supporting
      DisplayPort and HDMI 2.0.
      
      * tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
        clk: tegra: dfll: Reformat CVB frequency table
        clk: tegra: dfll: Properly clean up on failure and removal
        clk: tegra: dfll: Make code more comprehensible
        clk: tegra: dfll: Reference CVB table instead of copying data
        clk: tegra: dfll: Update kerneldoc
        clk: tegra: Fix PLL_U post divider and initial rate on Tegra30
        clk: tegra: Initialize PLL_C to sane rate on Tegra30
        clk: tegra: Fix pllre Tegra210 and add pll_re_out1
        clk: tegra: Add sor_safe clock
        clk: tegra: dpaux and dpaux1 are fixed factor clocks
        clk: tegra: Add dpaux1 clock
        clk: tegra: Use correct parent for dpaux clock
        clk: tegra: Add fixed factor peripheral clock type
        clk: tegra: Special-case mipi-cal parent on Tegra114
        clk: tegra: Remove trailing blank line
        clk: tegra: Constify peripheral clock registers
        clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
      5bc75324
    • Stephen Boyd's avatar
      Merge tag 'v4.7-rockchip-clk3' of... · 5569aedf
      Stephen Boyd authored
      Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
      
      Pull rockchip clk updates from Heiko Stuebner:
      
      A spelling fix and a bunch of rk3399 clock fixes.
      
      * tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
        clk: rockchip: fix the rk3399 cifout clock
        clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
        clk: rockchip: add some frequencies on the rk3399 PLL table
        clk: rockchip: assign more necessary rk3399 clock ids
        clk: rockchip: export some necessary rk3399 clock ids
        clk: rockchip: rename rga clock-id on rk3399
        clk: rockchip: add general gpu soft-reset on rk3399
        clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
        clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
      5569aedf
  7. 28 Apr, 2016 14 commits