- 19 Nov, 2019 11 commits
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Chris Wilson authored
As we may park the gt during request retirement, we may cancel the retirement worker only to then program the delayed worker once more. If we schedule the next delayed retirement worker first, if we then park the gt, the work will remain cancelled. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191119162559.3313003-2-chris@chris-wilson.co.uk
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Chris Wilson authored
When adding a new active timeline, place it at the end of the list. This allows for intel_gt_retire_requests() to pick up the newcomer more quickly and hopefully complete the retirement sooner. A miniscule optimisation. References: 7936a22d ("drm/i915/gt: Wait for new requests in intel_gt_retire_requests()") Signed-off-by:
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Matthew Auld authored
For our current users we don't expect pool objects to be writable from the gpu. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Fixes: 4f7af194 ("drm/i915: Support ro ppgtt mapped cmdparser shadow buffers") Reviewed-by:
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Matt Roper authored
The bspec initially provided a single DKL PHY vswing table for both HDMI and DP, but was recently updated to include an independent table for HDMI. Bspec: 49292 Fixes: 978c3e53 ("drm/i915/tgl: Add dkl phy programming sequences") Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191118180219.9309-1-matthew.d.roper@intel.comReviewed-by:
José Roberto de Souza <jose.souza@intel.com>
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Vandita Kulkarni authored
As per the Bspec, port mapping is fixed for mipi dsi. v2: Reuse the existing function (Jani) Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191119072004.4093-1-vandita.kulkarni@intel.com
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Chris Wilson authored
Take the obj->vma.lock to prevent modifications to the list as we iterate, to avoid the dreaded NULL pointer. <1>[ 347.820823] BUG: kernel NULL pointer dereference, address: 0000000000000150 <1>[ 347.820856] #PF: supervisor read access in kernel mode <1>[ 347.820874] #PF: error_code(0x0000) - not-present page <6>[ 347.820892] PGD 0 P4D 0 <4>[ 347.820908] Oops: 0000 [#1] PREEMPT SMP NOPTI <4>[ 347.820926] CPU: 3 PID: 1303 Comm: gem_persistent_ Tainted: G U 5.4.0-rc7-CI-CI_DRM_7352+ #1 <4>[ 347.820956] Hardware name: /NUC6CAYB, BIOS AYAPLCEL.86A.0049.2018.0508.1356 05/08/2018 <4>[ 347.821132] RIP: 0010:i915_gem_object_flush_write_domain+0xd9/0x1d0 [i915] <4>[ 347.821157] Code: 0f 84 e9 00 00 00 48 8b 80 e0 fd ff ff f6 c4 40 75 11 e9 ed 00 00 00 48 8b 80 e0 fd ff ff f6 c4 40 74 26 48 8b 83 b0 00 00 00 <48> 8b b8 50 01 00 00 e8 fb 20 fb ff 48 8b 83 30 03 00 00 49 39 c4 <4>[ 347.821210] RSP: 0018:ffffc90000a1f8f8 EFLAGS: 00010202 <4>[ 347.821229] RAX: 0000000000000000 RBX: ffffc900008479a0 RCX: 0000000000000018 <4>[ 347.821252] RDX: 0000000000000000 RSI: 000000000000000d RDI: ffff888275a090b0 <4>[ 347.821274] RBP: ffff8882673c8040 R08: ffff88825991b8d0 R09: 0000000000000000 <4>[ 347.821297] R10: 0000000000000000 R11: 0000000000000000 R12: ffff8882673c8280 <4>[ 347.821319] R13: ffff8882673c8368 R14: 0000000000000000 R15: ffff888266a54000 <4>[ 347.821343] FS: 00007f75865f4240(0000) GS:ffff888277b80000(0000) knlGS:0000000000000000 <4>[ 347.821368] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 347.821389] CR2: 0000000000000150 CR3: 000000025aee0000 CR4: 00000000003406e0 <4>[ 347.821411] Call Trace: <4>[ 347.821555] i915_gem_object_prepare_read+0xea/0x2a0 [i915] <4>[ 347.821706] intel_engine_cmd_parser+0x5ce/0xe90 [i915] <4>[ 347.821834] ? __i915_sw_fence_complete+0x1a0/0x250 [i915] <4>[ 347.821990] i915_gem_do_execbuffer+0xb4c/0x2550 [i915] Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191119100929.2628356-8-chris@chris-wilson.co.uk
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Chris Wilson authored
We only need the one loop to find the dirty vma flush them and their chipset. Signed-off-by:
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Chris Wilson authored
When userspace writes into the GTT itself, it is supposed to call set-domain to let the kernel keep track and so manage the CPU/GPU caches. As we track writes on the individual i915_vma, we should also be sure to mark them as dirty. Signed-off-by:
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Chris Wilson authored
In order to avoid some nasty mutex inversions, commit 09c5ab38 ("drm/i915: Keep rings pinned while the context is active") allowed the intel_ring unpinning to be run concurrently with the next context pinning it. Thus each step in intel_ring_unpin() needed to be atomic and ordered in a nice onion with intel_ring_pin() so that the lifetimes overlapped and were always safe. Sadly, a few steps in intel_ring_unpin() were overlooked, such as closing the read/write pointers of the ring and discarding the intel_ring.vaddr, as these steps were not serialised with intel_ring_pin() and so could leave the ring in disarray. Fixes: 09c5ab38 ("drm/i915: Keep rings pinned while the context is active") Signed-off-by:
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Chris Wilson authored
Only serialise with the chipset using an mmio if the chipset is currently active. We expect that any writes into the chipset range will simply be forgotten until it wakes up. Signed-off-by:
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Matt Roper authored
The bspec was recently updated with new cdclk -> voltage level tables to accommodate the new 324/326.4 cdclk values. Bspec: 21809 Fixes: 63c9dae7 ("drm/i915/ehl: Add voltage level requirement table") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by:
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- 18 Nov, 2019 7 commits
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Lucas De Marchi authored
When we call intel_dsb_get(), the dsb initialization may fail for various reasons. We already log the error message in that path, making it unnecessary to trigger a warning that refcount == 0 when calling intel_dsb_put(). So here we simplify the logic and do lazy shutdown: leaving the extra refcount alive so when we call intel_dsb_put() we end up calling i915_vma_unpin_and_release(). Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Lucas De Marchi authored
The current dsb API is not really prepared to handle multithread access. I was debugging an issue that ended up fixed by commit a096883d ("drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA") and was puzzled how these atomic operations were guaranteeing atomicity. if (atomic_add_return(1, &dsb->refcount) != 1) return dsb; Thread A could still be initializing dsb struct (and even fail in the middle) while thread B would take a reference and use it (even derefencing a NULL cmd_buf). I don't think the atomic operations here will help much if this were to support multithreaded scenario in future, so just remove them to avoid confusion. v2: Use refcount++ != 0 instead of ++refcount != 1 (from Ville) Signed-off-by:
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José Roberto de Souza authored
When the connector has VCPI allocated and is being moved to another pipe it causes drm_dp_atomic_release_vcpi_slots() and drm_dp_atomic_find_vcpi_slots() to be called in the same atomic check causing the error bellow. This happens because at this point Intel's hw.enable(and all other flags in the same struct) is not set but checking to on the uapi one it have the expected value. [ 580.804430] ------------[ cut here ]------------ [ 580.804436] WARNING: CPU: 0 PID: 1221 at drivers/gpu/drm/drm_dp_mst_topology.c:4094 drm_dp_atomic_find_vcpi_slots+0x157/0x180 [ 580.804439] Modules linked in: cdc_ether r8152 i915 prime_numbers snd_hda_codec_hdmi snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep asix snd_hda_core x86_pkg_temp_thermal usbnet mei_hdcp coretemp mii mei_me crct10dif_pclmul snd_pcm crc32_pclmul mei ghash_clmulni_intel i2c_i801 [last unloaded: prime_numbers] [ 580.804462] CPU: 0 PID: 1221 Comm: kworker/0:0 Tainted: G W 5.4.0-rc7-zeh+ #1226 [ 580.804465] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.D00.2321.A09.1909250226 09/25/2019 [ 580.804470] Workqueue: events output_poll_execute [ 580.804476] RIP: 0010:drm_dp_atomic_find_vcpi_slots+0x157/0x180 [ 580.804481] Code: 6a ff ff ff 49 89 6d 08 4c 89 6b 10 4c 89 63 18 49 89 6e 08 e9 55 ff ff ff 41 89 c7 5b 5d 44 89 f8 41 5c 41 5d 41 5e 41 5f c3 <0f> 0b 48 c7 c7 08 73 11 82 48 89 ee 41 bf ea ff ff ff e8 b2 e3 02 [ 580.804484] RSP: 0018:ffffc900009b7ab8 EFLAGS: 00010246 [ 580.804488] RAX: ffff88848c04ef50 RBX: ffff88848c04ef40 RCX: 0000000000000214 [ 580.804492] RDX: ffff88848c04f5e0 RSI: ffff888486eb2c68 RDI: ffff88848e518800 [ 580.804495] RBP: ffff88849d339000 R08: 00000000bc4e1092 R09: 0000000000000000 [ 580.804498] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848c04e728 [ 580.804501] R13: 0000000000000214 R14: ffff88848c04e720 R15: ffff888486eb2c68 [ 580.804504] FS: 0000000000000000(0000) GS:ffff8884a0000000(0000) knlGS:0000000000000000 [ 580.804507] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 580.804510] CR2: 00007ff6bf1ba680 CR3: 0000000005210003 CR4: 0000000000760ef0 [ 580.804512] PKRU: 55555554 [ 580.804515] Call Trace: [ 580.804574] intel_dp_mst_compute_config+0x193/0x2b0 [i915] [ 580.804636] intel_atomic_check+0x10cc/0x20b0 [i915] [ 580.804644] ? drm_atomic_print_old_state+0xf1/0x130 [ 580.804655] drm_atomic_check_only+0x56a/0x810 [ 580.804663] drm_atomic_commit+0xe/0x50 [ 580.804668] drm_client_modeset_commit_atomic+0x18b/0x220 [ 580.804680] drm_client_modeset_commit_force+0x4d/0x180 [ 580.804685] drm_fb_helper_restore_fbdev_mode_unlocked+0x46/0xa0 [ 580.804689] drm_fb_helper_set_par+0x27/0x50 [ 580.804692] drm_fb_helper_hotplug_event.part.0+0xa7/0xc0 [ 580.804696] drm_kms_helper_hotplug_event+0x21/0x30 [ 580.804699] output_poll_execute+0x1a4/0x1c0 [ 580.804706] process_one_work+0x25b/0x5b0 [ 580.804713] worker_thread+0x4b/0x3b0 [ 580.804720] kthread+0x100/0x140 [ 580.804723] ? process_one_work+0x5b0/0x5b0 [ 580.804725] ? kthread_park+0x80/0x80 [ 580.804730] ret_from_fork+0x24/0x50 [ 580.804740] irq event stamp: 40988 [ 580.804743] hardirqs last enabled at (40987): [<ffffffff81128567>] console_unlock+0x437/0x590 [ 580.804746] hardirqs last disabled at (40988): [<ffffffff81001cfa>] trace_hardirqs_off_thunk+0x1a/0x20 [ 580.804749] softirqs last enabled at (40972): [<ffffffff81c00389>] __do_softirq+0x389/0x47f [ 580.804752] softirqs last disabled at (40959): [<ffffffff810b6f19>] irq_exit+0xa9/0xc0 [ 580.804754] ---[ end trace 80052e0c60463c67 ]--- [ 580.804758] [drm:drm_dp_atomic_find_vcpi_slots] *ERROR* cannot allocate and release VCPI on [MST PORT:000000007880692e] in the same state [ 580.811370] [drm:intel_dp_hpd_pulse [i915]] got esi2 02 00 00 [ 580.817239] [drm:intel_dp_hpd_pulse [i915]] got esi 02 00 00 [ 580.817313] ------------[ cut here ]------------ [ 580.817318] WARNING: CPU: 0 PID: 1221 at drivers/gpu/drm/drm_dp_mst_topology.c:4094 drm_dp_atomic_find_vcpi_slots+0x157/0x180 [ 580.817321] Modules linked in: cdc_ether r8152 i915 prime_numbers snd_hda_codec_hdmi snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep asix snd_hda_core x86_pkg_temp_thermal [ 580.817412] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on [ENCODER:306:DDI E] - short [ 580.817413] usbnet mei_hdcp coretemp mii mei_me crct10dif_pclmul snd_pcm crc32_pclmul [ 580.817490] [drm:intel_dp_hpd_pulse [i915]] is_mst [ 580.817491] mei ghash_clmulni_intel i2c_i801 [last unloaded: prime_numbers] [ 580.817498] CPU: 0 PID: 1221 Comm: kworker/0:0 Tainted: G W 5.4.0-rc7-zeh+ #1226 [ 580.817503] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.D00.2321.A09.1909250226 09/25/2019 [ 580.817506] Workqueue: events output_poll_execute [ 580.817511] RIP: 0010:drm_dp_atomic_find_vcpi_slots+0x157/0x180 [ 580.817514] Code: 6a ff ff ff 49 89 6d 08 4c 89 6b 10 4c 89 63 18 49 89 6e 08 e9 55 ff ff ff 41 89 c7 5b 5d 44 89 f8 41 5c 41 5d 41 5e 41 5f c3 <0f> 0b 48 c7 c7 08 73 11 82 48 89 ee 41 bf ea ff ff ff e8 b2 e3 02 [ 580.817516] RSP: 0018:ffffc900009b7ab8 EFLAGS: 00010246 [ 580.817519] RAX: ffff88848c04ef50 RBX: ffff88848c04ef40 RCX: 000000000000018f [ 580.817521] RDX: ffff88848c04f5e0 RSI: ffff888486eb2c68 RDI: ffff88848e518800 [ 580.817523] RBP: ffff88849d339000 R08: 00000000bc4e1092 R09: 0000000000000000 [ 580.817525] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848c04e728 [ 580.817528] R13: 000000000000018f R14: ffff88848c04e720 R15: ffff888486eb2c68 [ 580.817532] FS: 0000000000000000(0000) GS:ffff8884a0000000(0000) knlGS:0000000000000000 [ 580.817534] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 580.817535] CR2: 00007ff6bf1ba680 CR3: 0000000005210003 CR4: 0000000000760ef0 [ 580.817537] PKRU: 55555554 [ 580.817538] Call Trace: [ 580.817620] intel_dp_mst_compute_config+0x193/0x2b0 [i915] [ 580.817690] intel_atomic_check+0x10cc/0x20b0 [i915] [ 580.817697] ? drm_atomic_print_old_state+0xf1/0x130 [ 580.817711] drm_atomic_check_only+0x56a/0x810 [ 580.817721] drm_atomic_commit+0xe/0x50 [ 580.817726] drm_client_modeset_commit_atomic+0x18b/0x220 [ 580.817744] drm_client_modeset_commit_force+0x4d/0x180 [ 580.817751] drm_fb_helper_restore_fbdev_mode_unlocked+0x46/0xa0 [ 580.817756] drm_fb_helper_set_par+0x27/0x50 [ 580.817762] drm_fb_helper_hotplug_event.part.0+0xa7/0xc0 [ 580.817767] drm_kms_helper_hotplug_event+0x21/0x30 [ 580.817771] output_poll_execute+0x1a4/0x1c0 [ 580.817780] process_one_work+0x25b/0x5b0 [ 580.817791] worker_thread+0x4b/0x3b0 [ 580.817800] kthread+0x100/0x140 [ 580.817804] ? process_one_work+0x5b0/0x5b0 [ 580.817807] ? kthread_park+0x80/0x80 [ 580.817813] ret_from_fork+0x24/0x50 [ 580.817832] irq event stamp: 41028 [ 580.817838] hardirqs last enabled at (41027): [<ffffffff81128567>] console_unlock+0x437/0x590 [ 580.817841] hardirqs last disabled at (41028): [<ffffffff81001cfa>] trace_hardirqs_off_thunk+0x1a/0x20 [ 580.817846] softirqs last enabled at (41022): [<ffffffff81c00389>] __do_softirq+0x389/0x47f [ 580.817851] softirqs last disabled at (41013): [<ffffffff810b6f19>] irq_exit+0xa9/0xc0 [ 580.817854] ---[ end trace 80052e0c60463c68 ]--- [ 580.817858] [drm:drm_dp_atomic_find_vcpi_slots] *ERROR* cannot allocate and release VCPI on [MST PORT:000000007880692e] in the same state [ 580.830767] [drm:intel_dp_mst_compute_config [i915]] failed finding vcpi slots:-22 [ 580.830821] [drm:intel_atomic_check [i915]] Encoder config failure: -22 Cc: Lyude Paul <lyude@redhat.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Lyude Paul <lyude@redhat.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191115200430.53146-1-jose.souza@intel.com
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Matt Roper authored
VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the old LFP panel mode data in block 42. Let's start parsing this block to fill in the panel fixed mode on devices with a >=229 VBT. v2: * Update according to the recent updates: - DTD size is now 16 bits instead of 24 - polarity is now just a single bit for hsync and vsync and is properly documented * Minor checkpatch fix v3: * Now that panel options are parsed separately from the previous patch, move generic DTD parsing into a function parallel to parse_lfp_panel_dtd. We'll still fall back to looking at the legacy LVDS timing block if the generic DTD fails. (Jani) * Don't forget to actually set lfp_lvds_vbt_mode! (Jani) * Drop "bdb_" prefix from dtd entry structure. (Jani) * Follow C99 standard for structure's flexible array member. (Jani) v4: * Add "positive" to polarity field names for clarity. (Jani) * Move VBT version check and fallback to legacy DTD parsing logic to a helper to keep top-level VBT parsing uncluttered. (Jani) * Restructure reserved bit packing at end of generic_dtd_entry from "u32 rsvd:24" to "u8 rsvd[3]" to prevent copy/paste mistakes in the future. (Jani) Bspec: 54751 Bspec: 20148 Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: -
Matt Roper authored
Newer VBT versions will add an alternate way to read panel DTD information, so let's split parsing of the general panel information from the timing data in preparation. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Jesse Barnes <jsbarnes@google.com> Reviewed-by:
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Chris Wilson authored
Having called intel_gt_init_early() to setup the mock intel_gt, we need to call the corresponding intel_gt_driver_late_release() to clean up. References: dea397e8 ("drm/i915/gt: Flush retire.work timer object on unload") References: 24635c51 ("drm/i915: Move intel_gt initialization to a separate file") Signed-off-by:
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Jani Nikula authored
It's supposed to be just a const pointer. Fixes: 074c77e3 ("drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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- 16 Nov, 2019 1 commit
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Don Hiatt authored
On some platforms (e.g. KBL) that do not support GuC submission, but the user enabled the GuC communication (e.g for HuC authentication) calling the GuC EXIT_S_STATE action results in lose of ability to enter RC6. We can remove the GuC suspend/resume entirely as we do not need to save the GuC submission status. Add intel_guc_submission_is_enabled() function to determine if GuC submission is active. v2: Do not suspend/resume the GuC on platforms that do not support Guc Submission. v3: Fix typo, move suspend logic to remove goto. v4: Use intel_guc_submission_is_enabled() to check GuC submission status. v5: No need to look at engine to determine if submission is enabled. Squash fix + intel_guc_submission_is_enabled() patch into one. v6: Move resume check into intel_guc_resume() for symmetry. Fix commit Fixes tag. Reported-by:KiteStramuort <kitestramuort@autistici.org> Reported-by:
S. Zharkoff <s.zharkoff@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111594 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111623 Fixes: ffd5ce22 ("drm/i915/guc: Updates for GuC 32.0.3 firmware") Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceralo Spurio <daniele.ceraolospurio@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Tested-by:
Tomas Janousek <tomi@nomi.cz> Signed-off-by:
Don Hiatt <don.hiatt@intel.com> Reviewed-by:
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- 15 Nov, 2019 14 commits
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Chris Wilson authored
This died many years ago as we now use i915_vma first and foremost. Signed-off-by:
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Chris Wilson authored
When telling the user that device power management is disabled, it is helpful to say which device that was. Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191115122343.821331-1-chris@chris-wilson.co.uk
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Ville Syrjälä authored
Currently we're blindly poking at the frame start delay bits in PIPECONF when trying to sanitize the hardware state. Those bits decided to move elsewhere on HSW, so on many platforms we're not doing anything at all here. Also we're forgetting about the PCH transcoder entirely. Add all the bit definitions for the various homes these bits have had throughout the years, and reset them all to zero. However I'm not entirely sure this is a safe thing to do. If not I guess we'd want full readout+statecheck for this stuff. For now let's stick to the current logic and hope for the best. Signed-off-by:
Uma Shankar <uma.shankar@intel.com>
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Chris Wilson authored
As the heartbeat has the effect of flushing context barriers, this interferes with the context barrier tests that are trying to observe them directly. Disable the heartbeat so that the barriers are as predictable as the test demands. Signed-off-by:
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Chris Wilson authored
Verify that we can execute a long chain of dependent requests from userspace, each one slightly more important than the last. Signed-off-by:
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Lionel Landwerlin authored
While we're waiting for the OA configuration to apply, let's give a chance to other contexts that might need to run other workloads. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Suggested-by:
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Chris Wilson authored
We need to wait until the timer object is marked as deactivated before unloading, so follow up our gentle cancel_delayed_work() with the synchronous variant to ensure it is flushed off a remote cpu before we mark the memory as freed. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111994Signed-off-by:
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Chris Wilson authored
RC6 is tracked underneath the intel_gt, so use our local pointers. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191115114800.725061-1-chris@chris-wilson.co.uk
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Chris Wilson authored
It applies to all gen9 and gen10 now, so we can use a single test against the gen bitmask. Signed-off-by:
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Chris Wilson authored
Inside the constructor, while cloning, we need to replace the dst->engines. Having forgotten that dst->engines is marked as RCU protected, we need to add the appropriate annotations to make sparse happy. Signed-off-by:
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Chris Wilson authored
Our callers fall into two categories, those passing timeout=0 who just want to flush request retirements and those passing a timeout that need to wait for submission completion (e.g. intel_gt_wait_for_idle()). Currently, we only wait for a snapshot of timelines at the start of the wait (but there was an expectation that new requests would cause timelines to appear at the end). However, our callers, such as intel_gt_wait_for_idle() before suspend, do require us to wait for the power management requests emitted by retirement as well. If we don't, then it takes an extra second or two for the background worker to flush the queue and mark the GT as idle. Fixes: 7e805762 ("drm/i915: Drop struct_mutex from around i915_retire_requests()") Signed-off-by:
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Jani Nikula authored
Backmerge to get dfce9025 ("Backmerge i915 security patches from commit 'ea0b163b' into drm-next") and thus 100d46bd ("Merge Intel Gen8/Gen9 graphics fixes from Jon Bloomfield."). Signed-off-by:
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
Two minor cleanups / fixes for -next. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m=20=28VMware=29?= Link: https://patchwork.freedesktop.org/patch/msgid/20191114131703.8607-1-thomas_os@shipmail.org
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2019-11-14' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - PMU "Frequency" is reported as accumulated cycles - Avoid OOPS in dumb_create IOCTL when no CRTCs - Mitigation for userptr put_pages deadlock with trylock_page - Fix to avoid freeing heartbeat request too early - Fix LRC coherency issue - Fix Bugzilla #112212: Avoid screen corruption on MST - Error path fix to unlock context on failed context VM SETPARAM - Always consider holding preemption a privileged op in perf/OA - Preload LUTs if the hw isn't currently using them to avoid color flash on VLV/CHV - Protect context while grabbing its name for the request - Don't resize aliasing ppGTT size - Smaller fixes picked by tooling Signed-off-by:
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- 14 Nov, 2019 7 commits
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Daniele Ceraolo Spurio authored
With the new interrupt re-partitioning in Gen11, GuC controls by itself the interrupts it receives, so steering bits and registers have been defeatured. Being this the case, when the GuC is in control of submissions we won't know what to do with the ctx switch interrupt in the driver, so disable it. v2 (Daniele): replace the gen9 paths instead of keeping gen9 and gen11 functions since we won't support guc submission on any pre-gen11 platform. Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by:
John Harrison <John.C.Harrison@Intel.com> Signed-off-by:
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Imre Deak authored
The workaround to disable coarse power gating is still needed on SKL GT3/GT4 machines and since the RC6 context corruption was discovered by the hardware team also on all GEN9 machines. Restore applying the workaround. Fixes: c1132367 ("drm/i915: Extract GT render sleep (rc6) management") Testcase: igt/intel_gt_pm_late_selftests/live_rc6_ctx Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Signed-off-by:
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Ville Syrjälä authored
HDMI_PICTURE_ASPECT_NONE is zero and the connector state is kzalloc()'d so no need to initialize conn_state->picture_aspect_ratio with it. Cc: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Ville Syrjälä authored
HDMI_PICTURE_ASPECT_NONE means "Automatic" so when the user has that selected we should keep whatever aspect ratio the mode already has. Also no point in checking for connector->is_hdmi in the SDVO code since we only attach the property to HDMI connectors. Cc: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Chris Wilson authored
As we want to be able to run inside atomic context for retiring the i915_active, and we are no longer allowed to abuse mutex_trylock, split the tree management portion of i915_active.mutex into an irq-safe spinlock. References: a0855d24 ("locking/mutex: Complain upon mutex API misuse in IRQ contexts") References: https://bugs.freedesktop.org/show_bug.cgi?id=111626 Fixes: 274cbf20 ("drm/i915: Push the i915_active.retire into a worker") Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191114172535.1116-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Probe the mocs registers for new contexts and across GPU resets. Similar to intel_workarounds, we have tables of what register values we expect to see, so verify that user contexts are affected by them. In the future, we should add tests similar to intel_sseu to cover dynamic reconfigurations. Signed-off-by:
Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191112223600.30993-4-chris@chris-wilson.co.uk
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Chris Wilson authored
We repeatedly (and more so in future) use the same looping construct over the mocs definition table to setup the register state. Refactor the loop construct into a reusable macro. add/remove: 2/1 grow/shrink: 1/2 up/down: 113/-330 (-217) Function old new delta intel_mocs_init_engine.cold - 71 +71 offset - 28 +28 __func__ 17273 17287 +14 intel_mocs_init 143 113 -30 mocs_register.isra 91 - -91 intel_mocs_init_engine 503 294 -209 Signed-off-by:
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