- 04 Oct, 2018 40 commits
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Jordan Crouse authored
The only HFI communication with the GMU on sdm845 happens during initialization and all commands are synchronous. A fancy interrupt tasklet and associated infrastructure is entirely not eeded and puts us at the mercy of the scheduler. Instead poll for the message signal and handle the response immediately and go on our way. Signed-off-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Jordan Crouse authored
The point of the 'force_dma' parameter for of_dma_configure is to force the device to be set up even if DMA capability is not described by the firmware which is exactly the use case we have for GMU - we need SMMU to get set up but we have no other dma capabilities since memory is managed by the GPU driver. Currently we pass false so of_dma_configure() fails and subsequently GMU and GPU probe does as well. Fixes: 4b565ca5 ("drm/msm: Add A6XX device support") Signed-off-by:
Sibi Sankar <sibis@codeaurora.org> Signed-off-by:
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Sharat Masetty authored
In the case where preemption is not enabled, this patch simply skips preemption related initialization in hardware init sequence. Signed-off-by:
Sharat Masetty <smasetty@codeaurora.org> Reviewed-by:
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Colin Ian King authored
The return from the call to _mixer_stages can be a negative error code however this is being assigned to an unsigned variable 'stages' hence the check is always false. Fix this by making 'stages' an int. Detected by Coccinelle ("Unsigned expression compared with zero: stages < 0") Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Jordan Crouse authored
The current design greedily takes a big chunk of the PDC register space instead of just the GPU specific sections which conflicts with other drivers and generally makes a mess of things. Furthermore we only need to map the GPU PDC sections just once during init so map the memory inside the function that uses it and adjust the pointers and register offsets accordingly. Signed-off-by:
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Jordan Crouse authored
>From the review for the DT bindings for the GPU/GMU it was suggested that the phandle for the GMU be 'qcom,gmu' instead of just 'gmu'. Signed-off-by:
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Anders Roxell authored
When CONFIG_DEV_COREDUMP isn't defined msm_gpu_crashstate_capture doesn't pass the correct parameters. drivers/gpu/drm/msm/msm_gpu.c: In function ‘recover_worker’: drivers/gpu/drm/msm/msm_gpu.c:479:34: error: passing argument 2 of ‘msm_gpu_crashstate_capture’ from incompatible pointer type [-Werror=incompatible-pointer-types] msm_gpu_crashstate_capture(gpu, submit, comm, cmd); ^~~~~~ drivers/gpu/drm/msm/msm_gpu.c:388:13: note: expected ‘char *’ but argument is of type ‘struct msm_gem_submit *’ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm, ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/msm_gpu.c:479:2: error: too many arguments to function ‘msm_gpu_crashstate_capture’ msm_gpu_crashstate_capture(gpu, submit, comm, cmd); ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/msm_gpu.c:388:13: note: declared here static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm, In current code the function msm_gpu_crashstate_capture parameters. Fixes: cdb95931 ("drm/msm/gpu: Add the buffer objects from the submit to the crash dump") Signed-off-by:Anders Roxell <anders.roxell@linaro.org> Reviewed-By:
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Sharat Masetty authored
The index of the perf table was being set in the wrong bit position in the register. With this fix, the GPU clock can be seen running at desired frequency. Signed-off-by:
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Rob Clark authored
The [v]snprintf() functions return the size that *would have* been written into the buffer, rather than the size *actually* written. Which results in us trying to memcpy() past the end of the stack. What we really want is [v]scnprintf(). Signed-off-by: -
Sean Paul authored
cur_master in dpu_encoder is assigned at modeset and cleared on .disable(). Unfortunately dpms (or enable/disable) does not guarantee a modeset, so cur_master is NULL when we try to re-enable it. This patch moves the NULL assignment to setup_display where it will be re-assigned later in the function. Tested-by:
Bruce Wang <bzwang@chromium.org> Reviewed-by:
Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
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Bruce Wang authored
Remove unneeded checks from _dpu_plane_get_aspace. v3: change _dpu_plane_get_aspace to return a struct *msm_gem_address_space instead passing in a pointer of the same type to edit. Remove uneeded arguments. Reviewed-by:
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Bruce Wang authored
Removed all impossible checks from the function, which eliminates the need for a return value. This function is also never used outside of dpu_plane.c, so the function is made static. v3: Using helper function _dpu_plane_get_kms() instead of doing it locally. Signed-off-by:
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Bruce Wang authored
Removes redundant tests for _dpu_crtc_vblank_enable_no_lock. Function return type is now void and all function calls have been changed accordingly. Signed-off-by:
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Bruce Wang authored
All checks for _dpu_crtc_power_enable are not true, so the function can never return an error code. This removes the need for the function as pm_runtime functions can be used instead. v3: Separated _dpu_crtc_power_enable into _dpu_crtc_power_enable and _dpu_crtc_power_disable for clarity. v4: Removed both _dpu_crtc_power_enable and _dpu_crtc_power_disable and called pm_runtime_get_sync and pm_runtime_put_sync from all call points Reviewed-by:
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Bruce Wang authored
Removes impossible checks in dpu_crtc.c. Variable assignments are moved up to be initializations where possible. Some variables are no longer used, these are removed. v3: reverted back to original patch Reviewed-by:
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Bruce Wang authored
Removes unnecessary checks from dpu_plane_atomic_disable, old_state argument for both dpu_plane_atomic_disable and dpu_plane_sspp_atomic_update is removed as it is no longer used. Reviewed-by:
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Bruce Wang authored
Removes some checks from dpu_plane.c that will never result in an error. Subsequent variable assignments become part of the initialization wherever possible. Unused variables are removed. v3: removed additional impossible checks and called helper function _dpu_plane_get_kms() where possible. Reviewed-by:
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Sean Paul authored
TP_printk is not synchronous, so storing pointers and then later dereferencing them is a Bad Idea. This patch stores everything locally to avoid display stomped memory. Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> [seanpaul fixed up commit msg typo on apply] Signed-off-by:
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Sean Paul authored
It's useful to know which bits of the flush come from extra_flush_bits Reviewed-by:
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Sean Paul authored
We're printing the frame_busy_mask in a trace, but after it's been cleared. This, as it turns out, is pretty pointless. Reviewed-by:
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Sean Paul authored
There's no benefit in falling out of the if, just return directly. Changes in v2: - None Reviewed-by:
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Sean Paul authored
All of the checks in dpu_plane_sspp_atomic_update() are impossible, so remove them and make the function void. This removes the need to error check in dpu_plane_atomic_update(). Additionally, remove impossible checks in dpu_plane_atomic_update(). Changes in v2: - None Reviewed-by:
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Sean Paul authored
plane->state->visible encompasses all of these checks and more, so we can just check visible. Changes in v2: - None Reviewed-by:
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Sean Paul authored
It's doing the same thing dpu_plane_enabled() is. Changes in v2: - None Reviewed-by:
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Sean Paul authored
dpu_plane_atomic_check() is a very thin wrapper around dpu_plane_sspp_atomic_check(). All it does is a NULL-check of state->fb, which is already done by drm_atomic_helper_check_plane_state(). Further, the helper sets state->visible = false when this is true. So remove dpu_plane_atomic_check() and just use dpu_plane_sspp_atomic_check() directly. Changes in v2: - Fix spelling mistake in Subject (Jeykumar) Reviewed-by:
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Sean Paul authored
src/dst rects are checked in both atomic_check and atomic_update, with the more comprehensive check occurring in atomic_update, which is backwards. So consolodate the checks in atomic_check. Changes in v2: - Use the correct crtc state (Jeykumar) Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by:
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Sean Paul authored
This patch removes some checks which are impossible to hit. As a result, we can move some of the local var assignments into the declarations. Changes in v2: - None Reviewed-by:
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Jordan Crouse authored
enum dpu_ad isn't used and can be safely removed. Reviewed-by:
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Jeykumar Sankaran authored
RM maintained a redundant definition for display topology to identify the no. of hw blocks needed for a display and their hardware dependencies. This information can be implicitly deduced from the msm_display_topology structure available in RM reserve request. In addition to getting rid of the redundant topology, this change also removes the topology name enums and their usages. changes in v4: - remove the topology name enum entirely (Sean) changes in v5: - remove RM topology definition and their references (Sean) - Implement helper for dual mixer CRTC (Sean) changes in v6: - avoid heap memory for topology (Sean) Signed-off-by:
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Jeykumar Sankaran authored
DPU, being over protective, validates every parameter of a module. This change traces the call stack for some of encoder functions affected by previous set of clean up patches and cleans up unwanted validations. changes in v5: - Introduced in the series changes in v6: - none Signed-off-by:
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Jeykumar Sankaran authored
Connector states were passed around RM to update the custom topology connector property with chosen topology data. Now that we got rid of both custom properties and topology names, this change cleans up the mechanism to pass connector states across RM helpers and encoder functions. changes in v5: - Introduced in the series changes in v6: - remove parameter checking in rm reserve (Jordan) Signed-off-by:
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Jeykumar Sankaran authored
Encoder H_TILE values are not used for allocating the hw blocks. no. of hw_intf blocks provides the info. changes in v4: - remove irrelevant changes (Sean) - retain log macros (Sean) changes in v5: - none Signed-off-by:
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Jeykumar Sankaran authored
DPU had the support to LOCK the hw resources in atomic check and CLEAR the locked resources explicitly through custom property values. Now that DPU is stripped off of all the custom properties, the RM handlers for this feature will be no-op's. This change gets rid of all its references. changes in v5: - Introduced in the series. Signed-off-by:
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Jeykumar Sankaran authored
Support for CDM block is not present in DPU. Remove CDM handlers from resource manager. changes in v4: - Introduced in the series changes in v5: - Remove catalog references to CDM (Sean) Signed-off-by:
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Jeykumar Sankaran authored
Destination scaling(DS) is a Snapdragon hardware feature to scale up the display ROI after layer blending. DPU driver doesn't support programming of DS blocks yet. This change cleans up the residual code present in catalog and RM for DS block handling. Support for the same can be added back when the feature is formally implemented. changes in v5: - introduced in the series Signed-off-by:
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Jeykumar Sankaran authored
Rename hw_ctl to lm_ctl to mean the ctl associated with the hw layer mixer block. sed -i 's/\([*@.>]\)hw_ctl\([^s]\)/\1lm_ctl\2/g' dpu_crtc.c dpu_crtc.h changes in v4: - Specifiy shell command used for renaming (Sean) changes in v5: - none Signed-off-by:
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Jeykumar Sankaran authored
Prep changes for state based resource management. Moves all the hw block tracking for the crtc to the state object. changes in v4: - Serialize crtc state access in debugfs handlers (Sean) - Split the crtc width query as a separate change (Sean) changes in v5: - mode set lock all before crtc state access (Sean) - remove unwanted memset for hw mixer cache (Sean) Signed-off-by:
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Jeykumar Sankaran authored
Mark CRTC get_mixer_width helper API static as it is not used outside the file. changes in v4: - Patch introduced in the series changes in v5: - Simplify the inline function (Sean) Signed-off-by:
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Jeykumar Sankaran authored
Resource manager assigns hw_intf blocks for the encoder only on modeset. If queried for hw_intf objects during init, it will be NULL. Since hw_intf objects are needed only after encoder enable, defer the query to encoder enable which will be triggered after modeset. changes in v4: - Add details on commit text on why the change is needed (Sean) changes in v5: - Reword commit text on the usage of hw_intf objects (Sean) Signed-off-by:
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Jeykumar Sankaran authored
In virtual encoder modeset, DPU makes RM request to assign hw blocks for the display. It is also expected in modeset to iterate and associate the physical encoders with their relevant hw blocks. Ping pong blocks are already handled here but hw ctl blocks are not. This change moves the hw_ctl iteration and mapping from physical encoder to virtual encoder. changes in v4: - Fix hw_ctl initialization (Sean) changes in v5: - Update commit text with details on why the change is needed (Sean) Signed-off-by:
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