- 17 Oct, 2019 20 commits
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Bhawanpreet Lakha authored
Detile buffer size affects dcc caps, it was already added for dcn2. Now add it for dcn21 Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
1 vmid limitation only exists for HOSTVM which is a custom use case anyway. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Eric Yang authored
[Why] Renoir is gfx9, same as dcn10, not dcn20. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Renoir can use vm contexes as long as HOSTVM is off so this should be initialized. Signed-off-by:
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Lewis Huang authored
[Why] Watermarks not propagated to DCHUBP after it is powered on [How] Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Bhawanpreet Lakha authored
Incorrect page table address and programming sys aperture for stutter gather, so fix it. Signed-off-by:
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Dmytro Laktyushkin authored
Enabling hostvm when ROIMMU is not active seems to break GPUVM. This fixes the issue by not enabling hostvm if ROIMMU is not activated. Signed-off-by:
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Lewis Huang authored
[why] driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box [How] Move the patch function before calculate wm. Signed-off-by:
joseph graveno <joseph.gravenor@amd.com> Acked-by:
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Bhawanpreet Lakha authored
it allows us to do urgent latency programming Signed-off-by:
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Bhawanpreet Lakha authored
[Why] DCN20 and DCN21 have different phy programming sequences. [How] Create a separate dcn21_link_encoder for Renoir Signed-off-by:
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Bhawanpreet Lakha authored
This change adds renoir hw_seq, needed to do renoir specific hw programing Signed-off-by:
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Bhawanpreet Lakha authored
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Bhawanpreet Lakha authored
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Roman Li authored
[Why] Earlier changes to support configurable aux timeout caused dc init failure on vega due to missing reg defs. Needs to be disabled until implemented for vega. [How] Set extended aux timeout cap for vega to false. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Signed-off-by:
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abdoulaye berthe authored
[Description] 1-add configurable timeout support to aux engine. 2-add timeout support field to dc_caps 3-add reg_key to override extended timeout support Signed-off-by:
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abdoulaye berthe authored
1-add timeout length and multiplier fields to aux_control1 register 2-update access mechanism from macro constructed name to uint32_t defined addresses. 3-define registers and field per asic family Signed-off-by:
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chen gong authored
smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. As to when GPU get into "GFXoff" will be up to drawing load. So we can not sure which state GPU should be in after enable gfxoff feature. Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Kenneth Feng authored
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Prike Liang authored
Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response. The patch can fix VCN IB test failed and DAL get dispaly count failed issue. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Prike Liang authored
Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE. Signed-off-by:
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- 15 Oct, 2019 20 commits
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Ahzo authored
This fixes kernel NULL pointer dereferences on shutdown: RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu] RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu] Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Ahzo <Ahzo@tutanota.com> Signed-off-by:
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Alex Deucher authored
Use BACO to reset the GPU if supported on SMU7 based dGPUs. v2: don't use baco on CI parts Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Wire up the powerplay callbacks for for BACO for smu7 devices. Reviewed-by:
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Alex Deucher authored
Several of the BACO functions are common across smu7-based asics. Split the common code out. Reviewed-by:
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Alex Deucher authored
This adds BACO support for CI asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Fiji asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for VegaM asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Polaris asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Iceland asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Tonga. Reviewed-by:
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Alex Deucher authored
This adds core support for BACO on pre-vega asics. Reviewed-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Add support for vega20 when the swSMU path is used. Reviewed-by:
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Alex Deucher authored
It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by:
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Alex Deucher authored
Use the base class rather than the specific class and drop the second loop. Reviewed-by:
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Alex Deucher authored
Move it into the caller. There are cases were we don't want it. We need it for hibernation, but we don't need it for runtime pm, so drop it for runtime pm. Reviewed-by:
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