1. 24 Oct, 2019 1 commit
  2. 12 Oct, 2019 3 commits
    • Paul Burton's avatar
      MIPS: Make builtin_cmdline const & variable length · 9dd422f6
      Paul Burton authored
      We have no need for the builtin_cmdline array to be fixed at the length
      of COMMAND_LINE_SIZE - we'll only copy out the string it contains up to
      its NULL terminator anyway, and cap the size at COMMAND_LINE_SIZE when
      copying into or concatenating with boot_command_line.
      
      The string value is also constant, so we can declare it as such to place
      it in the .init.rodata section.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      9dd422f6
    • Paul Burton's avatar
      MIPS: Fix CONFIG_OF_EARLY_FLATTREE=n builds · 97272776
      Paul Burton authored
      Configurations with CONFIG_OF_EARLY_FLATTREE=n fail to build since
      commit 7784cac6 ("MIPS: cmdline: Clean up boot_command_line
      initialization") because of_scan_flat_dt() & of_scan_flat_dt() are not
      defined in these configurations. Fix this by #ifdef'ing the affected
      code...
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Fixes: 7784cac6 ("MIPS: cmdline: Clean up boot_command_line initialization")
      Reported-by: default avatarkbuild test robot <lkp@intel.com>
      Cc: linux-mips@vger.kernel.org
      97272776
    • Paul Burton's avatar
      MIPS: Always define builtin_cmdline · b7340422
      Paul Burton authored
      Commit 7784cac6 ("MIPS: cmdline: Clean up boot_command_line
      initialization") made use of builtin_cmdline conditional upon plain C if
      statements rather than preprocessor #ifdef's. This caused build failures
      for configurations with CONFIG_CMDLINE_BOOL=n where builtin_cmdline
      wasn't defined, for example:
      
         arch/mips/kernel/setup.c: In function 'bootcmdline_init':
      >> arch/mips/kernel/setup.c:582:30: error: 'builtin_cmdline' undeclared
          (first use in this function); did you mean 'builtin_driver'?
            strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
                                       ^~~~~~~~~~~~~~~
                                       builtin_driver
         arch/mips/kernel/setup.c:582:30: note: each undeclared identifier is
          reported only once for each function it appears in
      
      Fix this by defining builtin_cmdline as an empty string in the affected
      configurations. All of the paths that use it should be optimized out
      anyway so the data itself gets optimized away too.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Fixes: 7784cac6 ("MIPS: cmdline: Clean up boot_command_line initialization")
      Reported-by: default avatarkbuild test robot <lkp@intel.com>
      Reported-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Cc: linux-mips@vger.kernel.org
      b7340422
  3. 10 Oct, 2019 2 commits
    • Nathan Chancellor's avatar
      mips: Fix unroll macro when building with Clang · df3da048
      Nathan Chancellor authored
      Building with Clang errors after commit 6baaeada ("MIPS: Provide
      unroll() macro, use it for cache ops") since the GCC_VERSION macro
      is defined in include/linux/compiler-gcc.h, which is only included
      in compiler.h when using GCC:
      
      In file included from arch/mips/kernel/mips-mt.c:20:
      ./arch/mips/include/asm/r4kcache.h:254:1: error: use of undeclared
      identifier 'GCC_VERSION'; did you mean 'S_VERSION'?
      __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32,
      )
      ^
      ./arch/mips/include/asm/r4kcache.h:219:4: note: expanded from macro
      '__BUILD_BLAST_CACHE'
                              cache_unroll(32, kernel_cache, indexop,
                              ^
      ./arch/mips/include/asm/r4kcache.h:203:2: note: expanded from macro
      'cache_unroll'
              unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize)));
              ^
      ./arch/mips/include/asm/unroll.h:28:15: note: expanded from macro
      'unroll'
              BUILD_BUG_ON(GCC_VERSION >= 40700 &&                    \
                           ^
      
      Use CONFIG_GCC_VERSION, which will always be set by Kconfig.
      Additionally, Clang 8 had improvements around __builtin_constant_p so
      use that as a lower limit for this check with Clang (although MIPS
      wasn't buildable until Clang 9); building a kernel with Clang 9.0.0
      has no issues after this change.
      
      Fixes: 6baaeada ("MIPS: Provide unroll() macro, use it for cache ops")
      Link: https://github.com/ClangBuiltLinux/linux/issues/736Signed-off-by: default avatarNathan Chancellor <natechancellor@gmail.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: clang-built-linux@googlegroups.com
      Cc: Nick Desaulniers <ndesaulniers@google.com>
      df3da048
    • Paul Burton's avatar
      MIPS: cmdline: Clean up boot_command_line initialization · 7784cac6
      Paul Burton authored
      Our current code to initialize boot_command_line is a mess. Some of this
      is due to the addition of too many options over the years, and some of
      this is due to workarounds for early_init_dt_scan_chosen() performing
      actions specific to options from other architectures that probably
      shouldn't be in generic code.
      
      Clean this up by introducing a new bootcmdline_init() function that
      simplifies the initialization somewhat. The major changes are:
      
      - Because bootcmdline_init() is a function it can return early in the
        CONFIG_CMDLINE_OVERRIDE case.
      
      - We clear boot_command_line rather than inheriting whatever
        early_init_dt_scan_chosen() may have left us. This means we no longer
        need to set boot_command_line to a space character in an attempt to
        prevent early_init_dt_scan_chosen() from copying CONFIG_CMDLINE into
        boot_command_line without us knowing about it.
      
      - Indirection via USE_PROM_CMDLINE, USE_DTB_CMDLINE, EXTEND_WITH_PROM &
        BUILTIN_EXTEND_WITH_PROM macros is removed; they seemingly served only
        to obfuscate the code.
      
      - The logic is cleaner, clearer & commented.
      
      Two minor drawbacks of this approach are:
      
      1) We call of_scan_flat_dt(), which means we scan through the DT again.
         The overhead is fairly minimal & shouldn't be noticeable.
      
      2) cmdline_scan_chosen() duplicates a small amount of the logic from
         early_init_dt_scan_chosen(). Alternatives might be to allow the
         generic FDT code to keep & expose a copy of the arguments taken from
         the /chosen node's bootargs property, or to introduce a function like
         early_init_dt_scan_chosen() that retrieves them without modification
         to handle CONFIG_CMDLINE. Neither of these sounds particularly
         cleaner though, and this way we at least keep the extra work in
         arch/mips.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      7784cac6
  4. 09 Oct, 2019 9 commits
  5. 08 Oct, 2019 1 commit
    • Tiezhu Yang's avatar
      MIPS: generic: Use __initconst for const init data · a14bf1dc
      Tiezhu Yang authored
      Fix the following checkpatch errors:
      
      $ ./scripts/checkpatch.pl --no-tree -f arch/mips/generic/init.c
      ERROR: Use of const init definition must use __initconst
      #23: FILE: arch/mips/generic/init.c:23:
      +static __initdata const void *fdt;
      
      ERROR: Use of const init definition must use __initconst
      #24: FILE: arch/mips/generic/init.c:24:
      +static __initdata const struct mips_machine *mach;
      
      ERROR: Use of const init definition must use __initconst
      #25: FILE: arch/mips/generic/init.c:25:
      +static __initdata const void *mach_match_data;
      
      Fixes: eed0eabd ("MIPS: generic: Introduce generic DT-based board support")
      Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      a14bf1dc
  6. 07 Oct, 2019 24 commits
    • Paul Burton's avatar
      MIPS: futex: Restore \n after sync instructions · fd7710cb
      Paul Burton authored
      Commit 3c1d3f09 ("MIPS: futex: Emit Loongson3 sync workarounds
      within asm") inadvertently removed the newlines following
      __WEAK_LLSC_MB, which causes build failures for configurations in which
      __WEAK_LLSC_MB expands to a sync instruction:
      
        {standard input}: Assembler messages:
        {standard input}:9346: Error: symbol `sync3' is already defined
        {standard input}:9380: Error: symbol `sync3' is already defined
        ...
      
      Fix this by restoring the newlines to separate the sync instruction from
      anything following it (such as the 3: label), preventing inadvertent
      concatenation.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Fixes: 3c1d3f09 ("MIPS: futex: Emit Loongson3 sync workarounds within asm")
      fd7710cb
    • Aurabindo Jayamohanan's avatar
      mips: check for dsp presence only once before save/restore · 9662dd75
      Aurabindo Jayamohanan authored
      {save,restore}_dsp() internally checks if the cpu has dsp support.
      Therefore, explicit check is not required before calling them in
      {save,restore}_processor_state()
      Signed-off-by: default avatarAurabindo Jayamohanan <mail@aurabindo.in>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: alexios.zavras@intel.com
      Cc: gregkh@linuxfoundation.org
      Cc: armijn@tjaldur.nl
      Cc: allison@lohutok.net
      Cc: tglx@linutronix.de
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      9662dd75
    • Thomas Bogendoerfer's avatar
      MIPS: PCI: use information from 1-wire PROM for IOC3 detection · 5dc76a96
      Thomas Bogendoerfer authored
      IOC3 chips in SGI system are conntected to a bridge ASIC, which has
      a 1-wire prom attached with part number information. This changeset
      uses this information to create PCI subsystem information, which
      the MFD driver uses for further platform device setup.
      Signed-off-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Lee Jones <lee.jones@linaro.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Cc: Alessandro Zummo <a.zummo@towertech.it>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: linux-doc@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: netdev@vger.kernel.org
      Cc: linux-rtc@vger.kernel.org
      Cc: linux-serial@vger.kernel.org
      5dc76a96
    • Thomas Bogendoerfer's avatar
      nvmem: core: add nvmem_device_find · 8c2a2b8c
      Thomas Bogendoerfer authored
      nvmem_device_find provides a way to search for nvmem devices with
      the help of a match function simlair to bus_find_device.
      Reviewed-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Acked-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Signed-off-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Lee Jones <lee.jones@linaro.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Alessandro Zummo <a.zummo@towertech.it>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: linux-doc@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: netdev@vger.kernel.org
      Cc: linux-rtc@vger.kernel.org
      Cc: linux-serial@vger.kernel.org
      8c2a2b8c
    • Alexandre GRIVEAUX's avatar
      MIPS: CI20: DTS: Add Leds · 24b0cb4f
      Alexandre GRIVEAUX authored
      Adding leds and related triggers.
      Signed-off-by: default avatarAlexandre GRIVEAUX <agriveaux@deutnet.info>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: robh+dt@kernel.org
      Cc: mark.rutland@arm.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      24b0cb4f
    • Alexandre GRIVEAUX's avatar
      MIPS: CI20: DTS: Add IW8103 Wifi + bluetooth · 948f2708
      Alexandre GRIVEAUX authored
      Add IW8103 Wifi + bluetooth module to device tree and related power domain.
      Signed-off-by: default avatarAlexandre GRIVEAUX <agriveaux@deutnet.info>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: robh+dt@kernel.org
      Cc: mark.rutland@arm.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      948f2708
    • Alexandre GRIVEAUX's avatar
      MIPS: CI20: DTS: Add I2C nodes · 73f2b940
      Alexandre GRIVEAUX authored
      Adding missing I2C nodes and some peripheral:
      - PMU
      - RTC
      Signed-off-by: default avatarAlexandre GRIVEAUX <agriveaux@deutnet.info>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: robh+dt@kernel.org
      Cc: mark.rutland@arm.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      73f2b940
    • Alexandre GRIVEAUX's avatar
      MIPS: JZ4780: DTS: Add I2C nodes · f56a040c
      Alexandre GRIVEAUX authored
      Add the devicetree nodes for the I2C core of the JZ4780 SoC, disabled
      by default.
      Signed-off-by: default avatarAlexandre GRIVEAUX <agriveaux@deutnet.info>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: robh+dt@kernel.org
      Cc: mark.rutland@arm.com
      Cc: ralf@linux-mips.org
      Cc: jhogan@kernel.org
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: devicetree@vger.kernel.org
      f56a040c
    • Dmitry Korotin's avatar
      mips: Kconfig: Add ARCH_HAS_FORTIFY_SOURCE · a2ecb233
      Dmitry Korotin authored
      FORTIFY_SOURCE detects various overflows at compile and run time.
      (6974f0c4 ("include/linux/string.h:
      add the option of fortified string.h functions)
      
      ARCH_HAS_FORTIFY_SOURCE means that the architecture can be built and
      run with CONFIG_FORTIFY_SOURCE.
      
      Since mips can be built and run with that flag,
      select ARCH_HAS_FORTIFY_SOURCE as default.
      Signed-off-by: default avatarDmitry Korotin <dkorotin@wavecomp.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      a2ecb233
    • Huacai Chen's avatar
      MIPS: Loongson-3: Add CSR IPI support · ffe59ee3
      Huacai Chen authored
      CSR IPI and legacy MMIO use the same infrastructure, but CSR IPI is
      faster than legacy MMIO IPI. This patch enable CSR IPI if possible
      (except for MailBox, because CSR IPI is too complicated for MailBox).
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-mips@vger.kernel.org
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhuacai@gmail.com>
      ffe59ee3
    • Huacai Chen's avatar
      MIPS: Loongson: Add Loongson-3A R4 basic support · 7507445b
      Huacai Chen authored
      All Loongson-3 CPU family:
      
      Code-name         Brand-name       PRId
      Loongson-3A R1    Loongson-3A1000  0x6305
      Loongson-3A R2    Loongson-3A2000  0x6308
      Loongson-3A R2.1  Loongson-3A2000  0x630c
      Loongson-3A R3    Loongson-3A3000  0x6309
      Loongson-3A R3.1  Loongson-3A3000  0x630d
      Loongson-3A R4    Loongson-3A4000  0xc000
      Loongson-3B R1    Loongson-3B1000  0x6306
      Loongson-3B R2    Loongson-3B1500  0x6307
      
      Features of R4 revision of Loongson-3A:
      
        - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc.
        - Support variable ASID bits.
        - Support MSA and VZ extensions.
        - Support CPUCFG (CPU config) and CSR (Control and Status Register)
            extensions.
        - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way
            set-associative).
      
      Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is
      the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/
      2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors
      which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R
      (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in
      general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-mips@vger.kernel.org
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhuacai@gmail.com>
      7507445b
    • Huacai Chen's avatar
      MIPS: Loongson: Add CFUCFG&CSR support · 6a6f9b7d
      Huacai Chen authored
      Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and
      CSR (Control and Status Register) extensions. This patch add read/write
      functionalities for them.
      Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
      Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-mips@vger.kernel.org
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhuacai@gmail.com>
      6a6f9b7d
    • Mike Rapoport's avatar
      mips: sgi-ip27: switch from DISCONTIGMEM to SPARSEMEM · 397dc00e
      Mike Rapoport authored
      The memory initialization of SGI-IP27 is already half-way to support
      SPARSEMEM. It only had free_bootmem_with_active_regions() left-overs
      interfering with sparse_memory_present_with_active_regions().
      
      Replace these calls with simpler memblocks_present() call in prom_meminit()
      and adjust arch/mips/Kconfig to enable SPARSEMEM and SPARSEMEM_EXTREME for
      SGI-IP27.
      Co-developed-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
      Signed-off-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
      Signed-off-by: default avatarMike Rapoport <rppt@linux.ibm.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      397dc00e
    • Paul Burton's avatar
      MIPS: Check Loongson3 LL/SC errata workaround correctness · e4acfbc1
      Paul Burton authored
      When Loongson3 LL/SC errata workarounds are enabled (ie.
      CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the
      compiled kernel & ensure that the workaround is applied correctly. That
      is, ensure that:
      
        - Every LL or LLD instruction is preceded by a sync instruction.
      
        - Any branches from within an LL/SC loop to outside of that loop
          target a sync instruction.
      
      Reasoning for these conditions can be found by reading the comment above
      the definition of __SYNC_loongson3_war in arch/mips/include/asm/sync.h.
      
      This tool will help ensure that we don't inadvertently introduce code
      paths that miss the required workarounds.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      e4acfbc1
    • Paul Burton's avatar
      MIPS: genex: Don't reload address unnecessarily · 4dee90d7
      Paul Burton authored
      In ejtag_debug_handler() we must reload the address of
      ejtag_debug_buffer_spinlock if an sc fails, since the address in k0 will
      have been clobbered by the result of the sc instruction. In the case
      where we simply load a non-zero value (ie. there's contention for the
      lock) the address will not be clobbered & we can simply branch back to
      repeat the load from memory without reloading the address into k0.
      
      The primary motivation for this change is that it moves the target of
      the bnez instruction to an instruction within the LL/SC loop (the LL
      itself), which we know contains no other memory accesses & therefore
      isn't affected by Loongson3 LL/SC errata.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      4dee90d7
    • Paul Burton's avatar
      MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler · 12dbb04f
      Paul Burton authored
      In ejtag_debug_handler we use LL & SC instructions to acquire & release
      an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
      this requires that we insert a sync instruction prior to the LL in order
      to ensure correct behavior of the LL/SC loop.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      12dbb04f
    • Paul Burton's avatar
      MIPS: barrier: Make __smp_mb__before_atomic() a no-op for Loongson3 · ae4cd0b1
      Paul Burton authored
      Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already
      emit a full completion barrier as part of the inline assembly containing
      LL/SC loops for atomic operations. As such the barrier emitted by
      __smp_mb__before_atomic() is redundant, and we can remove it.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      ae4cd0b1
    • Paul Burton's avatar
      MIPS: barrier: Remove loongson_llsc_mb() · 7f56b123
      Paul Burton authored
      The loongson_llsc_mb() macro is no longer used - instead barriers are
      emitted as part of inline asm using the __SYNC() macro. Remove the
      now-defunct loongson_llsc_mb() macro.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      7f56b123
    • Paul Burton's avatar
      MIPS: syscall: Emit Loongson3 sync workarounds within asm · e84957e6
      Paul Burton authored
      Generate the sync instructions required to workaround Loongson3 LL/SC
      errata within inline asm blocks, which feels a little safer than doing
      it from C where strictly speaking the compiler would be well within its
      rights to insert a memory access between the separate asm statements we
      previously had, containing sync & ll instructions respectively.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      e84957e6
    • Paul Burton's avatar
      MIPS: futex: Emit Loongson3 sync workarounds within asm · 3c1d3f09
      Paul Burton authored
      Generate the sync instructions required to workaround Loongson3 LL/SC
      errata within inline asm blocks, which feels a little safer than doing
      it from C where strictly speaking the compiler would be well within its
      rights to insert a memory access between the separate asm statements we
      previously had, containing sync & ll instructions respectively.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      3c1d3f09
    • Paul Burton's avatar
      MIPS: cmpxchg: Omit redundant barriers for Loongson3 · a91f2a1d
      Paul Burton authored
      When building a kernel configured to support Loongson3 LL/SC workarounds
      (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) the inline assembly in
      __xchg_asm() & __cmpxchg_asm() already emits completion barriers, and as
      such we don't need to emit extra barriers from the xchg() or cmpxchg()
      macros. Add compile-time constant checks causing us to omit the
      redundant memory barriers.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      a91f2a1d
    • Paul Burton's avatar
      MIPS: cmpxchg: Emit Loongson3 sync workarounds within asm · 6a57d2d1
      Paul Burton authored
      Generate the sync instructions required to workaround Loongson3 LL/SC
      errata within inline asm blocks, which feels a little safer than doing
      it from C where strictly speaking the compiler would be well within its
      rights to insert a memory access between the separate asm statements we
      previously had, containing sync & ll instructions respectively.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      6a57d2d1
    • Paul Burton's avatar
      MIPS: bitops: Use smp_mb__before_atomic in test_* ops · 90267377
      Paul Burton authored
      Use smp_mb__before_atomic() rather than smp_mb__before_llsc() in
      test_and_set_bit(), test_and_clear_bit() & test_and_change_bit(). The
      _atomic() versions make semantic sense in these cases, and will allow a
      later patch to omit redundant barriers for Loongson3 systems that
      already include a barrier within __test_bit_op().
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      90267377
    • Paul Burton's avatar
      MIPS: bitops: Emit Loongson3 sync workarounds within asm · 5bb29275
      Paul Burton authored
      Generate the sync instructions required to workaround Loongson3 LL/SC
      errata within inline asm blocks, which feels a little safer than doing
      it from C where strictly speaking the compiler would be well within its
      rights to insert a memory access between the separate asm statements we
      previously had, containing sync & ll instructions respectively.
      Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@vger.kernel.org
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
      Cc: linux-kernel@vger.kernel.org
      5bb29275