- 13 Jan, 2020 2 commits
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Vasily Khoruzhick authored
Add cooling maps and thermal tripping points to prevent CPU overheating when running at the highest frequency. Tripping points are taken from A33 dts since A64 user manual doesn't mention when we should start throttling. Signed-off-by:
Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by:
Maxime Ripard <maxime@cerno.tech>
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Vasily Khoruzhick authored
Add CPU clock to the CPU nodes since it is a prerequisite for enabling DVFS. Signed-off-by:
Chen-Yu Tsai <wens@csie.org>
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- 06 Jan, 2020 8 commits
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Chen-Yu Tsai authored
A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by:
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Chen-Yu Tsai authored
A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by:
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Chen-Yu Tsai authored
The Libre Computer ALL-H5-CC board is an upgraded version of the ALL-H3-CC. Changes include: - Gigabit Ethernet via external RTL8211E Ethernet PHY - 16 MiB SPI NOR flash memory - PoE tap header - Line out jack removed Only H5 variant test samples were made available, and the vendor is not certain whether other SoC variants would be made or not. Furthermore the board is a minor upgrade compared to the ALL-H3-CC. Thus the device tree simply includes the one for the ALL-H3-CC, and adds the changes on top. Signed-off-by:
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Andre Przywara authored
The Allwinner R40 SoC contains four SPI controllers, using the newer sun6i design (but at the legacy addresses). The controller seems to be fully compatible to the A64 one, so no driver changes are necessary. The first three controllers can be used on two sets of pins, but SPI3 is only routed to one set on Port A. Only the pin groups for SPI0 on PortC and SPI1 on PortI are added here, because those seem to be the only one exposed on the Bananapi boards. Tested by connecting a SPI flash to a Bananapi M2 Berry SPI0 and SPI1 header pins. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
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Samuel Holland authored
By default, gpio-keys configures the pin to trigger wakeup IRQs on either edge. The lid switch should only trigger wakeup when opening the lid, not when closing it. Signed-off-by:
Samuel Holland <samuel@sholland.org> Signed-off-by:
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Chen-Yu Tsai authored
The CSI0 and CSI1 blocks are the same as found on the A20. However only CSI0 is supported upstream right now. Add a device node for CSI0 using the A20 compatible as a fallback, and the standard pinctrl options. Also add the MBUS interconnect. Signed-off-by:
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Chen-Yu Tsai authored
The CSI controller driver now supports the second CSI controller, CSI1. Add a device node for it. Pinmuxing options for the MCLK output, the standard 8-bit interface, and a secondary 24-bit interface are included. Signed-off-by:
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Chen-Yu Tsai authored
The CSI controller driver now supports the second CSI controller, CSI1. Add a device node for it. Pinmuxing options for the MCLK output, the standard 8-bit interface, and a secondary 24-bit interface are included. Signed-off-by:
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- 04 Jan, 2020 1 commit
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Maxime Ripard authored
Some old SoCs, while supporting LVDS, don't list the LVDS clocks and reset lines. Let's add them when relevant. Acked-by:
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- 03 Jan, 2020 3 commits
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Jagan Teki authored
tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0, tcon-ch1 which are referring tcon_top clocks via index numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1 respectively. Use the macro in place of index numbers, for more code readability. Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Reviewed-by:
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Andre Przywara authored
The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual Performance Monitoring Unit (PMU), which allows perf to use hardware events. The SoC integrator just needs to connect each per-core interrupt line to the GIC. The R40 manual does not really mention those IRQ lines, but experimentation in U-Boot shows that interrupts 152-155 are connected to the four cores (similar to the A20). Tested on a Bananapi M2 Berry, with perf and taskset to confirm the association between cores and interrupts. Signed-off-by:
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Andre Przywara authored
The GIC used in the R40 SoC is an ARM GIC-400 with virtualization support, so let's advertise the full 8K region of the GICC MMIO frame to enable KVM's usage of the GIC (as we do already for all other SoCs). Tested by running KVM on a Bananapi M2 Berry. Signed-off-by:
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- 27 Dec, 2019 1 commit
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Ondrej Jirman authored
There are two sensors, one for CPU, one for GPU. Signed-off-by:
Ondrej Jirman <megous@megous.com> Signed-off-by:
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- 26 Dec, 2019 6 commits
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Chen-Yu Tsai authored
The Libre Computer ALL-H3-IT board is a small single board computer that is roughly the same size as the Raspberry Pi Zero, or around 20% smaller than a credit card. The board features: - H2, H3, or H5 SoC from Allwinner - 2 DDR3 DRAM chips - Realtek RTL8821CU based WiFi module - 128 Mbit SPI-NOR flash - micro-SD card slot - micro HDMI video output - FPC connector for camera sensor module - generic Raspberri-Pi style 40 pin GPIO header - additional pin headers for extra USB host ports, ananlog audio and IR receiver Only H5 variant test samples were made available, but the vendor does have plans to include at least an H3 variant. Thus the device tree is split much like the ALL-H3-CC, with a common dtsi file for the board design, and separate dts files including the common board file and the SoC dtsi file. The other variants will be added as they are made available. Signed-off-by: -
Jagan Teki authored
Add MIPI DSI pipeline for Allwinner A64. - dsi node, with A64 compatible since it doesn't support DSI_SCLK gating unlike A33 - dphy node, with A64 compatible with A33 fallback since DPHY on A64 and A33 is similar - finally, attach the dsi_in to tcon0 for complete MIPI DSI Signed-off-by:
Merlijn Wajer <merlijn@wizzup.org> Signed-off-by:
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Vasily Khoruzhick authored
A64 has 3 thermal sensors: 1 for CPU, 2 for GPU. Signed-off-by:
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Ondrej Jirman authored
There are two sensors, one for CPU, one for GPU. Signed-off-by:
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Ondrej Jirman authored
There is just one sensor for the CPU. Signed-off-by:
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Ondrej Jirman authored
There are three sensors, two for each CPU cluster, one for GPU. Signed-off-by:
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- 20 Dec, 2019 5 commits
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Maxime Ripard authored
The MMC configuration clock controller in the A80 definition has a clock-names and reset-names property, even though the binding for that controller doesn't declare it. Remove it. Acked-by:
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Maxime Ripard authored
Even though it translates to the same thing down to the binary level, we should have an array of 2 number cells to describe each voltage state, which in turns create a validation warning. Let's fix this. Acked-by:
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Maxime Ripard authored
The TCON binding mandates a dmas phandle to the DMAengine channel used for that controller. However, since it's not used in the driver, some device trees have been missing it. Let's add it. Acked-by:
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Maxime Ripard authored
The V3s mixer node has an assigned clocks property, while the driver also enforces it. Since assigned-clocks is pretty fragile anyway, let's just remove it. Acked-by:
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Maxime Ripard authored
While this is functional, it's a best practice to always have the clocks and reset lines in order, in case we ever need to have compatibility code. Acked-by:
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- 16 Dec, 2019 7 commits
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Maxime Ripard authored
The Allwinner A80 SoC has a display clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Maxime Ripard authored
The Allwinner A80 SoC has a USB clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Reviewed-by:
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Maxime Ripard authored
The newer Allwinner SoCs have a DE2 clocks controller that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Reviewed-by:
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Chen-Yu Tsai authored
The R40 has five I2C controllers. Currently only I2C0 has its pinmux option defined. Add the options for the remaining four, and set them as the default, since each controller has only one possible pinmux configuration. Signed-off-by:
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Clément Péron authored
Allwinner device tree files used different comment style for copyright notice. Update this to keep a coherency. Signed-off-by:
Clément Péron <peron.clem@gmail.com> Signed-off-by:
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Clément Péron authored
Use a shorter SPDX identifier instead of pasting the whole license. Signed-off-by:
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Clément Péron authored
Some headers specify that files are under dual-licensed GPL2.0+ and X11. But in fact, it turns out that the full licenses texts associated are GPL2.0+ and MIT. Fix license headers to reflect real licenses associated. Signed-off-by:
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- 11 Dec, 2019 4 commits
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Clément Péron authored
With dual licensed SPDX identifier the "OR" should be uppercase. Signed-off-by:
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Stefan Mavrodiev authored
Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. This patch adds regulators for them to the pinctrl node. Exception is PL which is used by the RSB bus. To avoid circular dependencies, VCC-PL is omitted. On boards with eMMC, VCC-PC is supplied by ELDO1, instead of DCDC1. Signed-off-by:
Stefan Mavrodiev <stefan@olimex.com> [Maxime: Changed the r_pio comment a bit] Signed-off-by:
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Jernej Skrabec authored
Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:
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Jernej Skrabec authored
H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 10 Dec, 2019 3 commits
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Andre Przywara authored
Add the Performance Monitoring Unit (PMU) device tree node to the H3 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on an OrangePi Zero. Signed-off-by:
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Andre Przywara authored
Add the Performance Monitoring Unit (PMU) device tree node to the H5 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. As with the A64, the interrupt numbers from the manual were wrong (off by 4), the actual SPI IDs have been gathered in U-Boot, and were verified with perf in Linux. Tested with perf record and taskset on an OrangePi PC2. Signed-off-by:
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Andre Przywara authored
Add the Performance Monitoring Unit (PMU) device tree node to the H6 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on a Pine H64. Signed-off-by:
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