1. 22 May, 2020 3 commits
    • Thomas Zimmermann's avatar
    • Ben Skeggs's avatar
      drm/nouveau: fix out-of-tree module build · bbd540c0
      Ben Skeggs authored
      The $(srctree) addition a while back busted building the out-of-tree
      version of the module, and I've been hacking it up ever since.
      
      This allows us to work around the issue.
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      bbd540c0
    • James Jones's avatar
      drm: Generalized NV Block Linear DRM format mod · 82c8c4dd
      James Jones authored
      Builds upon the existing NVIDIA 16Bx2 block linear
      format modifiers by adding more "fields" to the
      existing parameterized
      DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK format modifier
      macro that allow fully defining a unique-across-
      all-NVIDIA-hardware bit layout using a minimal
      set of fields and values.  The new modifier macro
      DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D is
      effectively backwards compatible with the existing
      macro, introducing a superset of the previously
      definable format modifiers.
      
      Backwards compatibility has two quirks.  First,
      the zero value for the "kind" field, which is
      implied by the DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK
      macro, must be special cased in drivers and
      assumed to map to the pre-Turing generic kind of
      0xfe, since a kind of "zero" is reserved for
      linear buffer layouts on all GPUs.
      
      Second, it is assumed backwards compatibility
      is only needed when running on Tegra GPUs, and
      specifically Tegra GPUs prior to Xavier.  This
      is based on two assertions:
      
      -Tegra GPUs prior to Xavier used a slightly
       different raw bit layout than desktop GPUs,
       making it impossible to directly share block
       linear buffers between the two.
      
      -Support for the existing block linear modifiers
       was incomplete, making them useful only for
       exporting buffers created by nouveau and
       importing them to Tegra DRM as framebuffers for
       scan out.  There was no support for adding
       framebuffers using format modifiers in nouveau,
       nor importing dma-buf/PRIME GEM objects into
       nouveau userspace drivers with modifiers in Mesa.
      
      Hence it is assumed the prior modifiers were not
      intended for use on desktop GPUs, and as a
      corollary, were not intended to support sharing
      block linear buffers across two different NVIDIA
      GPUs.
      
      v2:
        - Added canonicalize helper function
      
      v3:
        - Added additional bit to compression field to
          support Tesla (NV5x,G8x,G9x,GT1xx,GT2xx) class
          chips.
      Signed-off-by: default avatarJames Jones <jajones@nvidia.com>
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      82c8c4dd
  2. 21 May, 2020 2 commits
  3. 20 May, 2020 2 commits
    • Dave Airlie's avatar
      Merge tag 'drm-intel-next-2020-05-15' of git://anongit.freedesktop.org/drm/drm-intel into drm-next · 6cf99161
      Dave Airlie authored
      UAPI Changes:
      
      - drm/i915: Show per-engine default property values in sysfs
      
          By providing the default values configured into the kernel via sysfs, it
          is much more convenient for userspace to restore those sane defaults, or
          at least know what are considered good baseline. This is useful, for
          example, to cleanup after any failed userspace prior to commencing new
          jobs.
      
      Cross-subsystem Changes:
      
      - video/hdmi: Add Unpack only function for DRM infoframe
      - Includes pull request gvt-next-2020-05-12
      
      Driver Changes:
      
      - Restore Cherryview back to full-ppgtt (Chris, Mika)
      - Document locking guidelines for i915 (Chris, Daniel, Joonas)
      - Fix GitLab #1746: Handle idling during i915_gem_evict_something busy loops (Chris)
      - Display WA #1105: Require linear fb stride to be multiple of 512 bytes on
        gen9/glk (Ville)
      - Add Wa_14010685332 for ICP/ICL (Matt R)
      - Restrict w/a 1607087056 for EHL/JSL (Swathi)
      - Fix interrupt handling for DP AUX transactions on Tigerlake (Imre)
      - Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" (Mika)
      - Fix HDC pipeline flush hardware bit on Gen12 (Mika)
      - Flush L3 when flushing render on Gen12 (Mika)
      - Invalidate aux table entries forcibly between BB on Gen12 (Mika)
      - Add aux table invalidate for all engines on Gen12 (Mika)
      - Force pte cacheline to main memory Gen8+ (Mika)
      - Add and enable TGL+ SAGV support (Stanislav)
      - Implement vm_ops->access on i915 mmaps for GDB (Chris, Kristian)
      - Replace zero-length array with flexible-array (Gustavo)
      - Improve batch buffer pool effectiveness to mitigate soft-rc6 hit (Chris)
      - Remove wait priority boosting (Chris)
      - Keep driver module referenced when PMU is active (Chris)
      - Sanitize RPS interrupts upon resume (Chris)
      - Extend pcode read timeout to 20 ms (Chris)
      - Wait for ACT sent before enabling MST pipe (Ville)
      - Extend support to async relocations to SNB (Chris)
      - Remove CNL pre-prod workarounds (Ville)
      - Don't enable WaIncreaseLatencyIPCEnabled when IPC is disabled (Sultan)
      - Record the active CCID from before reset (Chris)
      - Mark concurrent submissions with a weak-dependency (Chris)
      - Peel dma-fence-chains for await to allow engine-to-engine sync (Lionel)
      - Prevent using semaphores to chain up to external fences (Chris)
      - Fix GLK watermark calculations (Ville)
      - Emit await(batch) before MI_BB_START (Chris)
      - Reset execlists registers before HWSP (Chris)
      - Drop no-semaphore boosting in favor of fast timeslicing (Chris)
      - Fix enabled infoframe states of lspcon (Gwan-gyeong)
      - Program DP SDPs on pipe updates (Gwan-gyeong)
      - Stop sending DP SDPs on ddi disable (Gwan-gyeong)
      - Store CS timestamp frequency in Hz (Ville)
      
      - Remove unused HAS_FWTABLE macro (Pascal)
      - Use batchbuffer chaining for relocations to save ring space (Chris)
      - Try different engines for relocs if MI ops not supported (Chris, Tvrtko)
      - Lazily acquire the device wakeref for freeing objects (Chris)
      - Streamline display code arithmetics around rounding etc. (Ville)
      - Use bw state for per crtc SAGV evaluation (Stanislav)
      - Track active_pipes in bw_state (Stanislav)
      - Nuke mode.vrefresh usage (Ville)
      - Warn if the FBC is still writing to stolen on removal (Chris)
      - Added new PCode commands prepping for QGV rescricting (Stansilav)
      - Stop holding onto the pinned_default_state (Chris)
      - Propagate error from completed fences (Chris)
      - Ignore submit-fences on the same timeline (Chris)
      - Pull waiting on an external dma-fence into its routine (Chris)
      - Replace the hardcoded I915_FENCE_TIMEOUT with Kconfig (Chris)
      - Mark up the racy read of execlists->context_tag (Chris)
      - Tidy up the return handling for completed dma-fences (Chris)
      - Introduce skl_plane_wm_level accessor (Stanislav)
      - Extract SKL SAGV checking (Stanislav)
      - Make active_pipes check skl specific (Stanislav)
      - Suspend tasklets before resume sanitization (Chris)
      - Remove redundant exec_fence (Chris)
      - Mark the addition of the initial-breadcrumb in the request (Chris)
      - Transfer old virtual breadcrumbs to irq_worker (Chris)
      - Read the DP SDPs from the video DIP (Gwan-gyeong)
      - Program DP SDPs with computed configs (Gwan-gyeong)
      - Add state readout for DP VSC and DP HDR Metadata Infoframe SDP
        (Gwan-gyeong)
      - Add compute routine for DP PSR VSC SDP (Gwan-gyeong)
      - Use new DP VSC SDP compute routine on PSR (Gwan-gyeong)
      - Restrict qgv points which don't have enough bandwidth. (Stanislav)
      - Nuke pointless div by 64bit (Ville)
      
      - Static checker code fixes (Nathan, Mika, Chris)
      - Add logging function for DP VSC SDP (Gwan-gyeong)
      - Include HDMI DRM infoframe, DP HDR metadata and DP VSC SDP in the
        crtc state dump (Gwan-gyeong)
      - Make timeslicing explicit engine property (Chris, Tvrtko)
      - Selftest and debugging improvements (Chris)
      - Align variable names with BSpec (Ville)
      - Tidy up gen8+ breadcrumb emission code (Chris)
      - Turn intel_digital_port_connected() in a vfunc (Ville)
      - Use stashed away hpd isr bits in intel_digital_port_connected() (Ville)
      - Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() (Ville)
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200515160703.GA19043@jlahtine-desk.ger.corp.intel.com
      6cf99161
    • Dave Airlie's avatar
      Merge tag 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next · bfbe1744
      Dave Airlie authored
      amd-drm-next-5.8-2020-05-19:
      
      amdgpu:
      - Improved handling for CTF (Critical Thermal Fault) situations
      - Clarify AC/DC mode switches
      - SR-IOV fixes
      - XGMI fixes for RAS
      - Misc cleanups
      - Add autodump debugfs node to aid in GPU hang debugging
      
      UAPI:
      - Add a MEM_SYNC IB flag for handling proper acquire memory semantics if UMDs expect the kernel to handle this
        Used by AMDVLK: https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/os/amdgpu/amdgpuQueue.cpp#L1262Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      From: Alex Deucher <alexdeucher@gmail.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200519202505.4126-1-alexander.deucher@amd.com
      bfbe1744
  4. 19 May, 2020 3 commits
  5. 18 May, 2020 15 commits
  6. 15 May, 2020 2 commits
  7. 14 May, 2020 13 commits