- 03 Jun, 2013 1 commit
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Ben Widawsky authored
It's not terribly interesting to know that a parameter doesn't exist, and it can get in the way of interesting messages, especially with the staggered VECS merging as we've done. Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 31 May, 2013 39 commits
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Paulo Zanoni authored
It just prints whether it's supported/enabled/disabled. Feature requested by the power management team. v2: Checkpatch started complaining about seq_printf with 1 argument. Requested-by:
Kristen Accardi <kristen.c.accardi@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Paulo Zanoni authored
IPS is still enabled by default. Feature requested by the power management team. This should also help testing the feature on some early pre-production hardware where there were relationship problems between IPS and PSR. v2: Rebase on top of the newest IPS implementation. v3: Check i915_enable_ips at compute_config, not supports_ips, so the kernel parameter will be ignored at haswell_get_pipe_config. Requested-by: -
Paulo Zanoni authored
Intermediate Pixel Storage is a feature that should reduce the number of times the display engine wakes up memory to read pixels, so it should allow deeper PC states. IPS can only be enabled on ULT pipe A with 8:8:8 pipe pixel formats. With eDP 1920x1080 and correct watermarks but without FBC this moves my PC7 residency from 2.5% to around 38%. v2: - It's tied to pipe A, not port A - Add pipe_config support (Chris) - Add some assertions (Chris) - Rebase against latest dinq v3: - Don't ever set ips_enabled to false (Daniel) - Only check for ips_enabled at hsw_disable_ips (Daniel) v4: - Add hsw_compute_ips_config (Daniel) - Use the new dump_pipe_config (Daniel) Signed-off-by: -
Daniel Vetter authored
Now that we track the cpu transcoder we need accurately in the pipe config we can finally fix up the transcoder check. With the current code eDP on port D will be broken since we'd errornously cut the power. For reference see commit 2124b72e Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Fri Mar 22 14:07:23 2013 -0300 drm/i915: don't disable the power well yet v2: - Kill the now outdated comment (Paulo) - Add the missing crtc->base.enabled check and consolidate it (Paulo) - Smash all checks together, looks neater that way. v3: Kill the unused encoder variable. Cc: Takashi Iwai <tiwai@suse.de> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Xiang, Haihao authored
This will let userland only try to use the new ring when the appropriate kernel is present Signed-off-by:
Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Xiang, Haihao authored
A user can run batchbuffer via VEBOX ring. Signed-off-by:
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Xiang, Haihao authored
v2: Removed rebase relic VECS ring from i915_gem_request_info (Damien) v3: s/hsw/hws in debugfs which I introduced in v2 (Jon) Signed-off-by:
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Ben Widawsky authored
Similar to a patch originally written by: v2: Reversed the meanings of masked and enabled (Haihao) Made non-destructive writes in case enable/disabler rps runs first (Haihao) v3: Reword error message (Damien) Modify postinstall to do the right thing based on previous fixup. (Ben) CC: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by:
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Ben Widawsky authored
v2: Use the correct lock to protect PM interrupt regs, this was accidentally lost from earlier (Haihao) Fix return types (Ben) Reviewed-by:
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Ben Widawsky authored
The motivation here is we're going to add some new interrupt definitions and handling outside of the GT interrupts which is all we've managed so far (with some RPS exceptions). By consolidating the names in the future we can make thing a bit cleaner as we don't need to define register names twice, and we can leverage pretty decent overlap in HW registers since ILK. To explain briefly what is in the comments: there are two sets of interrupt masking/enabling registers. At least so far, the definitions of the two sets overlap. The old code setup distinct names for interrupts in each set, ie. one for global, and one for ring. This made things confusing when using the wrong defines in the wrong places. rebase: Modified VLV bits v2: Renamed GT_RENDER_MASTER to GT_RENDER_CS_MASTER (Damien) Reviewed-by:
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Ben Widawsky authored
It's overkill on older gens, but it's useful for newer gens. Reviewed-by:
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Ben Widawsky authored
PM interrupts have an expanded role on HSW. It helps route the EBOX interrupts. This patch is necessary to make the existing code which touches the mask, and enable registers more friendly to other code paths that also will need these registers. To be more explicit: At preinstall all interrupts are masked and disabled. This implies that preinstall should always happen before any enabling/disabling of RPS or other interrupts. The PMIMR is touched by the workqueue, so enable/disable touch IER and IIR. Similarly, the code currently expects IMR has no use outside of the RPS related interrupts so they unconditionally set 0, or ~0. We could use IER in the workqueue, and IMR elsewhere, but since the workqueue use-case is more transient the existing usage makes sense. Disable RPS events: IER := IER & ~GEN6_PM_RPS_EVENTS // Disable RPS related interrupts IIR := GEN6_PM_RPS_EVENTS // Disable any outstanding interrupts Enable RPS events: IER := IER | GEN6_PM_RPS_EVENTS // Enable the RPS related interrupts IIR := GEN6_PM_RPS_EVENTS // Make sure there were no leftover events (really shouldn't happen) v2: Shouldn't destroy PMIIR or PMIMR VEBOX interrupt state in enable/disable rps functions (Haihao) v3: Bug found by Chris where we were clearing the wrong bits at rps disable. expanded commit message v4: v3 was based off the wrong branch v5: Added the setting of PMIMR because of previous patch update CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: -
Ben Widawsky authored
At the moment, these values are wiped out anyway by the rps enable/disable. That will be changed in the next patch though. v2: Add post install setup to address issue found by Damien in the next patch. replaced WARN_ON(dev_priv->rps.pm_iir != 0); with rps.pm_iir = 0; With the v2 of this patch and the deferred pm enabling (which changed since the original patches) we're now able to get PM interrupts before we've brought up enabled rps. At this point in boot, we don't want to do anything about it, so we simply ignore it. Since writing the original assertion, the code has changed quite a bit, and I believe removing this assertion is perfectly safe. Signed-off-by:
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Ben Widawsky authored
Just duplicates ironlake_irq_preinstall for now. v2: Add new PCH_NOP check (Damien) Add SDEIMR comment (Damien) Signed-off-by:
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Ben Widawsky authored
HSW has some special requirements for the VEBOX. Splitting out the interrupt handler will make the code a bit nicer and less error prone when we begin to handle those. The slight functional change in this patch (queueing work while holding the spinlock) is intentional as it makes a subsequent patch a bit nicer. The change should also only effect HSW platforms. Reviewed-by:
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Paulo Zanoni authored
Now we compute the results for both 1/2 and 5/6 partitioning and then use hsw_find_best_result to choose which one to use. With this patch, Haswell watermarks support should be in good shape. The only improvement we're missing is the case where the primary plane is disabled: we always assume it's enabled, so we take it into consideration when calculating the watermarks. v2: - Check the latency when finding the best result Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Paulo Zanoni authored
We were previously only setting the WM_PIPE registers, now we are setting the LP watermark registers. This should allow deeper PC states, resulting in power savings. We're only using 1/2 data buffer partitioning for now. v2: Merge both hsw_compute_pri_wm_* functions (Ville) v3: - Simplify hsw_compute_wm_results (Ville) - Rebase due to changes on the previous patch v4: Unconfuse wm_lp/level (Ville) Signed-off-by: -
Paulo Zanoni authored
We were previously calling sandybridge_update_wm on HSW, but the SNB function didn't really match the HSW specification, so we were just writing the wrong values. With this patch, the haswell_update_wm function will set the correct values for the WM_PIPE registers, but it will still keep all the LP watermarks disabled. The patch may look a little bit over-complicated for now, but it's because much of the infrastructure for setting the LP watermarks is already in place, so we won't have too much code churn on the patch that sets the LP watermarks. v2: - Fix pixel_rate on panel fitter case (Ville) - Try to not overflow (Ville) - Remove useless variable (Ville) - Fix p->pri_horiz_pixels (Paulo) v3: - Fix rounding errors on hsw_wm_method2 (Ville) v4: - Fix memcmp bug (Paulo) Signed-off-by: -
Daniel Vetter authored
This was accidentally broken in the south error interrupt handling work: commit 8664281b Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Fri Apr 12 17:57:57 2013 -0300 drm/i915: report Gen5+ CPU and PCH FIFO underruns Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
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Ben Widawsky authored
v2: Add set_seqno which didn't exist before rebase (Haihao) Signed-off-by:
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Xiang, Haihao authored
The flag will be useful to help share code between IVB, and HSW as the programming is similar in many places with this as one of the major differences. Signed-off-by:
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Ben Widawsky authored
Historically we considered the render ring to have special flush semantics and everything else to fall under a more general umbrella. Probably by coincidence more than anything we decided to make the bsd ring have the default *other* flush. As the new vebox ring exposes, the bsd ring is actually the weird one. Doing this allows us to call gen6_ring_flush for the vebox because calling blt_ring_flush would be weird... This patch should have no functional change. Reviewed-by:
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Ben Widawsky authored
Like the other rings, the VECS supports semaphores. The semaphore stuff is a bit wonky so this patch on it's own should be nice for review. This patch should have no functional impact. v2: Fix the English parts of clarification (again, register names were right, text was reversed) (Damien) Restore the still valid invariant. (Damien) The bsd semaphore register should be MI_SEMAPHORE_SYNC_VVE (Damien) Signed-off-by:
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Ben Widawsky authored
The video enhancement command streamer is a new ring on HSW which does what it sounds like it does. This patch provides the most minimal inception of the ring. In order to support a new ring, we need to bump the number. The patch may look trivial to the untrained eye, but bumping the number of rings is a bit scary. As such the patch is not terribly useful by itself, but a pretty nice place to find issues during a bisection. Reviewed-by:
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Ben Widawsky authored
This replaces the existing MBOX update code with a more generalized calculation for emitting mbox updates. We also create a sentinel for doing the updates so we can more abstractly deal with the rings. When doing MBOX updates the code must be aware of the /other/ rings. Until now the platforms which supported semaphores had a fixed number of rings and so it made sense for the code to be very specialized (hardcoded). The patch does contain a functional change, but should have no behavioral changes. Signed-off-by:
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Ben Widawsky authored
Semaphores are tied very closely to the rings in the GPU. Trivial patch adds comments to the existing code so that when we add new rings we can include comments there as well. It also helps distinguish the ring to semaphore mailbox interactions by using the ringname in the semaphore data structures. This patch should have no functional impact. v2: The English parts (as opposed to register names) of the comments were reversed. (Damien) Signed-off-by:
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Mika Kuoppala authored
crtc is holding a reference to a cursor bo and it needs to be released when crtc is destroyed so that we don't leak the cursor bo. v2: Enhance set and move cursor so that disabled cursor is handled correctly (Ville Syrjälä) Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Chris Wilson authored
It appears that a beneficial side-effect of Mika's more accurate hangman work is to speed up hang detection and execution. This exposes a bug in the reset code that then treats repeated simulated hangs as an indication that the machine is wedged. Jiggle the code around so that we only do the simulation processing from the hangcheck and avoid confusing it with a real hang. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65060Signed-off-by:
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Daniel Vetter authored
- Correct cpu->pch display matching is already check when we detect the PCH type at driver load. - Plane/pipe state is already checked both when a) enabling, b) disabling and in c) the modeset state checker. No need to go overboard and also check it in in between a) and b). Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by:
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Daniel Vetter authored
All this pipe config abstraction adds another layer of complexity, so it's good to have better visibility into what's going on exactly. Doesn't dump out everything yet, and some bits are a bit duplicated but this should be a good start. Note that at boot-up a lot of the fields are 0 even for enabled pipes, this is simply because our hw state readout code doesn't support everything. v2: Remove a few more now redudant debug output lines. v3: Review from Paulo - use transcoder_name - fix up format specifiers - add missing ':' in debug output Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by:
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Wei Yongjun authored
Fix to return -ENOMEM in the kmap() error handling case instead of 0, as done elsewhere in this function. Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by:
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Jani Nikula authored
In the cloned case, changing just one output but keeping the other, the pipe state won't change and intel_crtc_update_dpms will be a nop, but we still need to update the dpms state of the output being changed. Only dvo, sdvo and crt are cloneable, so only those three have special dpms functions. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Daniel Vetter authored
This allows us to drop a bunch of ugly hacks and finally implement what commit cc464b2a Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Fri Jan 25 16:59:16 2013 -0200 drm/i915: set TRANSCODER_EDP even earlier tried to achieve, but that was reverted again in commit bba2181c Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Mar 22 10:53:40 2013 +0100 Revert "drm/i915: set TRANSCODER_EDP even earlier" Now we should always have a consistent cpu_transcoder in the pipe_config. v2: Fix up the code as spotted by Paulo: - read the register for real - assign the right pipes - break out if the hw state doesn't make sense v3: Shut up gcc. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Daniel Vetter authored
Well, as well as we can without completely revamping the drm vblank code. The issue are that - The vblank code needs to work on both ums and kms. - It deals always deals with pipes. - It doesn't take any of the kms locks. The last part is not really fixable without revamping the drm vblank code, since the drm core <-> driver interactions is a veritable pile of spaghettis. But the other pieces can be fixed by switching on the MODESET driver flag and either checking the hw state directly (ums case) or just querying our sw tracking (with broken locking, but that's not worse than what we've had). Note that this essentially reverts commit 702e7a56 Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Tue Oct 23 18:29:59 2012 -0200 drm/i915: convert PIPECONF to use transcoder instead of pipe for the ums case, which will fix a NULL deref (since we really don't have any crtcs set up). But the real reason to do this is to drop our reliance on the cpu_transcoder: By only checking intel_crtc->active we don't need to make sure that the pipe_config (or at least the cpu_transcoder) contain safe values even when the pipe is off. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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Imre Deak authored
Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
The patch changes all remaining is_cpu_edp() check with a check for port A. We can do this, since in all these cases ValleyView is handled separately and port A is always a CPU side eDP port. Signed-off-by:
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Imre Deak authored
On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we can calculate for both the clock divider for the 2MHz target rate at the same place. Afterwards we can also replace the is_cpu_edp() check with a check for port A. Signed-off-by:
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Imre Deak authored
Based on 3739850b - "drm/i915: disable the cpu edp port after the cpu pipe" and the bspec disabling sequence for IVB and older it seems we have to distinguish only the CPU vs. PCH port case, whether it's a DP or eDP doesn't seem to matter. For IVB and older on the CPU side we can only have eDP on port A, DP ports can only be on the PCH side. On VLV we have only CPU side eDP/DP ports, no PCH. So the condition for the disabling sequence we need for CPU ports is port == A || IS_VLV. This allows us to remove is_cpu_edp() completely in a later patch. v2: - simplify (and fix) the condition for CPU side ports and adjust the commit message accordingly (Daniel) Signed-off-by:
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Imre Deak authored
Signed-off-by:
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