1. 17 Jun, 2013 1 commit
    • Ido Reis's avatar
      wl18xx: FDSP Code RAM Corruption fix · e3b8bbb9
      Ido Reis authored
      In PG2.0 there is an issue where PHY's FDSP Code RAM sometimes gets
      corrupted when exiting from ELP mode. This issue is related to FDSP
      Code RAM clock implementation.
      
      PG2.1 introduces a HW fix for this issue that requires the driver to
      change the FDSP Code Ram clock settings (mux it to ATGP clock instead
      of its own clock).
      
      This workaround uses PHY_FPGA_SPARE_1 register and is relevant to WL8
      PG2.1 devices.
      
      The fix is also backward compatible with older PG2.0 devices where the
      register PHY_FPGA_SPARE_1 is not used and not connected.
      
      The fix is done in the wl18xx_pre_upload function (must be performed
      before uploading the FW code) and includes the following steps:
      
      1. Disable FDSP clock
      2. Set ATPG clock toward FDSP Code RAM rather than its own clock.
      3. Re-enable FDSP clock
      Signed-off-by: default avatarYair Shapira <yair.shapira@ti.com>
      Signed-off-by: default avatarIdo Reis <idor@ti.com>
      Signed-off-by: default avatarArik Nemtsov <arik@wizery.com>
      Signed-off-by: default avatarLuciano Coelho <coelho@ti.com>
      e3b8bbb9
  2. 14 Jun, 2013 26 commits
  3. 13 Jun, 2013 13 commits