1. 26 Aug, 2015 4 commits
    • Imre Deak's avatar
      drm/i915/bxt: don't allow cached GEM mappings on A stepping · e5756c10
      Imre Deak authored
      Due to a coherency issue on BXT A steppings we can't guarantee a
      coherent view of cached (CPU snooped) GPU mappings, so fail such
      requests. User space is supposed to fall back to uncached mappings in
      this case.
      
      v2:
      - limit the WA to A steppings, on later stepping this HW issue is fixed
      v3:
      - return error instead of trying to work around the issue in kernel,
        since that could confuse user space (Chris)
      
      Testcast: igt/gem_store_dword_batches_loop/cached-mapping
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      e5756c10
    • Imre Deak's avatar
      drm/i915/bxt: work around HW coherency issue when accessing GPU seqno · 319404df
      Imre Deak authored
      By running igt/store_dword_loop_render on BXT we can hit a coherency
      problem where the seqno written at GPU command completion time is not
      seen by the CPU. This results in __i915_wait_request seeing the stale
      seqno and not completing the request (not considering the lost
      interrupt/GPU reset mechanism). I also verified that this isn't a case
      of a lost interrupt, or that the command didn't complete somehow: when
      the coherency issue occured I read the seqno via an uncached GTT mapping
      too. While the cached version of the seqno still showed the stale value
      the one read via the uncached mapping was the correct one.
      
      Work around this issue by clflushing the corresponding CPU cacheline
      following any store of the seqno and preceding any reading of it. When
      reading it do this only when the caller expects a coherent view.
      
      v2:
      - fix using the proper logical && instead of a bitwise & (Jani, Mika)
      - limit the workaround to A stepping, on later steppings this HW issue
        is fixed
      v3:
      - use a separate get_seqno/set_seqno vfunc (Chris)
      
      Testcase: igt/store_dword_loop_render
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      319404df
    • Rodrigo Vivi's avatar
      drm/i915: Also call frontbuffer flip when disabling planes. · 8be6ca85
      Rodrigo Vivi authored
      We also need to call the frontbuffer flip to trigger proper
      invalidations when disabling planes. Otherwise we will miss
      screen updates when disabling sprites or cursor.
      
      On core platforms where HW tracking also works, this issue
      is totally masked because HW tracking triggers PSR exit
      however on VLV/CHV that has only SW tracking we miss screen
      updates when disabling planes.
      
      It was caught with kms_psr_sink_crc sprite_plane_onoff
      and cursor_plane_onoff subtests running on VLV/CHV.
      
      This is probably a regression since I can also get this
      with the manual test case, but with so many changes on atomic
      modeset I couldn't track exactly when this was introduced.
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      8be6ca85
    • Arun Siluvery's avatar
      drm/i915: Change SRM, LRM instructions to use correct length · f1afe24f
      Arun Siluvery authored
      MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
      variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
      (reg, addr) pairs so use fixed length for these instructions.
      
      v2: rebase
      
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
      Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      [danvet: Appease checkpatch as Mika spotted in i915_reg.h - it seems
      terminally unhappy about i915_cmd_parser.c so that would be a separate
      patch.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      f1afe24f
  2. 25 Aug, 2015 1 commit
  3. 14 Aug, 2015 35 commits