- 26 Sep, 2020 3 commits
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Olof Johansson authored
Merge tag 'tegra-for-5.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.10-rc1 These changes contain a bit of cleanup and chip support for the upcoming Tegra234 SoC. * tag 'tegra-for-5.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Add Tegra234 support soc/tegra: pmc: Reorder reset sources/levels definitions soc/tegra: misc: Add Tegra234 support soc/tegra: fuse: Add Tegra234 support soc/tegra: fuse: Implement tegra_is_silicon() soc/tegra: fuse: Extract tegra_get_platform() Link: https://lore.kernel.org/r/20200918150303.3938852-2-thierry.reding@gmail.comSigned-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'tee-dev-cleanup-for-v5.10' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers Simplify tee_device_register() and friends Uses cdev_device_add() instead of the cdev_add() device_add() combination. Initializes dev->groups instead of direct calls to sysfs_create_group() and friends. * tag 'tee-dev-cleanup-for-v5.10' of git://git.linaro.org:/people/jens.wiklander/linux-tee: tee: avoid explicit sysfs_create/delete_group by initialising dev->groups tee: replace cdev_add + device_add with cdev_device_add Link: https://lore.kernel.org/r/20200918144130.GB1219771@jadeSigned-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'renesas-drivers-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.10 (take two) - Add core support for the R-Car V3U (R8A779A0) SoC, including System Controller (SYSC) and Reset (RST) support, - Various Kconfig cleanups. * tag 'renesas-drivers-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: r8a779a0-sysc: Add r8a779a0 support soc: renesas: rcar-rst: Add support for R-Car V3U soc: renesas: Identify R-Car V3U soc: renesas: Sort driver description title soc: renesas: Use ARM32/ARM64 for menu description dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions dt-bindings: power: Add r8a779a0 SYSC power domain definitions Link: https://lore.kernel.org/r/20200918124800.15555-4-geert+renesas@glider.beSigned-off-by: Olof Johansson <olof@lixom.net>
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- 18 Sep, 2020 8 commits
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Thierry Reding authored
The PMC block is largely similar to that found on earlier chips, but not completely compatible. Allow binding to the instantiation found on Tegra234. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Move the definitions of reset sources and levels into a more natural location. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The MISC block is largely similar to that found on earlier chips, but not completely compatible. Allow binding to the instantiation found on Tegra234. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add support for FUSE block found on the Tegra234 SoC, which is largely similar to the IP found on previous generations. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
This function can be used by drivers to determine whether code is running on silicon or on a simulation platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
This function extracts the PRE_SI_PLATFORM field from the HIDREV register and can be used to determine which platform the kernel runs on (silicon, simulation, ...). Note that while only Tegra194 and later define this field, it should be safe to call this on prior generations as well since this field should read as 0, indicating silicon. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Sudeep Holla authored
If the dev->groups is initialised, the sysfs group is created as part of device_add call. There is no need to call sysfs_create/delete_group explicitly. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Sudeep Holla authored
Commit 233ed09d ("chardev: add helper function to register char devs with a struct device") added a helper function 'cdev_device_add'. Make use of cdev_device_add in tee_device_register to replace cdev_add and device_add. Since cdev_device_add takes care of setting the kobj->parent, drop explicit initialisation in tee_device_alloc. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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- 16 Sep, 2020 1 commit
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Yoshihiro Shimoda authored
Add support for R-Car V3U (R8A779A0) SoC power areas and register access, because register specification differs from R-Car Gen2/3. Inspired by patches in the BSP by Tho Vu. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-5-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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- 15 Sep, 2020 1 commit
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Olof Johansson authored
Merge tag 'scmi-updates-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers ARM SCMI updates for v5.10 Couple of main additions: SCMI system protocol support and ability to build SCMI driver as a single module which is needed by some transports like virtio as they may not be ready early during the boot. This also includes constification of scmi ops and related function pointers. * tag 'scmi-updates-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: firmware: arm_scmi: Enable building as a single module firmware: arm_scmi: Move scmi protocols registration into the driver firmware: arm_scmi: Move scmi bus init and exit calls into the driver firmware: smccc: Export both smccc functions firmware: arm_scmi: Fix NULL pointer dereference in mailbox_chan_free firmware: arm_scmi: Add SCMI device for system power protocol firmware: arm_scmi: Add system power protocol support firmware: arm_scmi: Constify static scmi-ops firmware: arm_scmi: Constify ops pointers in scmi_handle cpufreq: arm_scmi: Constify scmi_perf_ops pointers Link: https://lore.kernel.org/r/20200914075018.2rvytvghxyutcbk4@bogusSigned-off-by: Olof Johansson <olof@lixom.net>
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- 14 Sep, 2020 4 commits
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Sudeep Holla authored
Now, with all the plumbing in place to enable building scmi as a module instead of built-in modules, let us enable the same. Link: https://lore.kernel.org/r/20200907195046.56615-5-sudeep.holla@arm.comTested-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
In preparation to enable building SCMI as a single module, let us move the SCMI protocol registration call into the driver. This enables us to also add unregistration of the SCMI protocols. The main reason for this is to keep it simple instead of maintaining it as separate modules and dealing with all possible initcall races and deferred probe handling. We can move it as separate modules if needed in future. Link: https://lore.kernel.org/r/20200907195046.56615-4-sudeep.holla@arm.comTested-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
In preparation to enable building scmi as a single module, let us move the scmi bus {de-,}initialisation call into the driver. The main reason for this is to keep it simple instead of maintaining it as separate modules and dealing with all possible initcall races and deferred probe handling. We can move it as separate modules if needed in future. Link: https://lore.kernel.org/r/20200907195046.56615-3-sudeep.holla@arm.comTested-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
We need to export both arm_smccc_1_1_get_conduit and arm_smccc_get_version to allow several modules make use of them. Arm FFA, Arm SCMI and PTP drivers are few drivers that are planning to use these functions. Let us export them in preparation to add support for SCMI as module. Link: https://lore.kernel.org/r/20200907195046.56615-2-sudeep.holla@arm.comSigned-off-by: Sudeep Holla <sudeep.holla@arm.com>
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- 13 Sep, 2020 4 commits
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https://github.com/Broadcom/stblinuxOlof Johansson authored
This pull request contains Broadcom SoCs drivers changes for 5.10, please pull the following: - Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller and adds support for the 6318, 6328, 6362, 63268. - Florian adds support for tuning the Bus Interface Unit on 72164 and 72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the 64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB driver to support breakpoint notifications. * tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux: bus: brcmstb_gisb: Add support for breakpoint interrupts dt-bindings: bus: Document breakpoint interrupt for gisb-arb soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 MIPS: BMIPS: dts: add BCM63268 power domain support MIPS: BMIPS: dts: add BCM6362 power domain support MIPS: BMIPS: dts: add BCM6328 power domain support soc: bcm: add BCM63xx power domain driver MIPS: BMIPS: add BCM6318 power domain definitions MIPS: BMIPS: add BCM63268 power domain definitions MIPS: BMIPS: add BCM6362 power domain definitions MIPS: BMIPS: add BCM6328 power domain definitions dt-bindings: soc: brcm: add BCM63xx power domain binding soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache bus: brcmstb_gisb: Shorten prints Link: https://lore.kernel.org/r/20200912032153.1216354-3-f.fainelli@gmail.comSigned-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'memory-controller-drv-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.10 1. Fixes in several drivers for GCC warnings, including kerneldoc fixes and issues discovered while compile testing. 2. Enable compile testing of most of the drivers. 3. Use dev_err_probe() to simplify the code. 4. omap-gpmc: fix off by one errors, code cleanups and improvements. 5. tegra: remove the GPU from DRM IOMMU group so it would use its own; few minor fixes. 6. brcmstb_dpfe: fix memory leak and array index out of bounds. * tag 'memory-controller-drv-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (26 commits) memory: fsl-corenet-cf: Fix handling of platform_get_irq() error memory: omap-gpmc: Fix -Wunused-function warnings memory: tegra: Remove GPU from DRM IOMMU group memory: tegra186-emc: Simplify with dev_err_probe() memory: brcmstb_dpfe: Simplify with dev_err_probe() memory: samsung: exynos5422-dmc: add missing and fix kerneldoc memory: samsung: exynos5422-dmc: remove unused exynos5_dmc members memory: samsung: exynos5422-dmc: rename timing register fields variables memory: emif: Remove bogus debugfs error handling memory: omap-gpmc: Fix build error without CONFIG_OF memory: omap-gpmc: Fix a couple off by ones memory: brcmstb_dpfe: fix array index out of bounds memory: brcmstb_dpfe: Fix memory leak memory: tegra: Correct shift value of apew memory: Enable compile testing for most of the drivers memory: brcmstb_dpfe: add separate entry for compile test memory: tegra: tegra210-emc: fix indentation memory: renesas-rpc-if: simplify with PTR_ERR_OR_ZERO memory: omap-gpmc: consistently use !res for NULL checks memory: omap-gpmc: use WARN() instead of BUG() on wrong free ... Link: https://lore.kernel.org/r/20200907150611.11267-1-krzk@kernel.orgSigned-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'renesas-drivers-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.10 - Improve visual Kconfig structure. * tag 'renesas-drivers-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Align driver description titles soc: renesas: Use menu for Renesas SoC Link: https://lore.kernel.org/r/20200904114819.30254-4-geert+renesas@glider.beSigned-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'optee-i2c-fix-for-v5.10' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers Make sure I2C functions used in OP-TEE are reachable with IS_REACHABLE() * tag 'optee-i2c-fix-for-v5.10' of git://git.linaro.org:/people/jens.wiklander/linux-tee: drivers: optee: fix i2c build issue Link: https://lore.kernel.org/r/20200901101806.GA3286324@jadeSigned-off-by: Olof Johansson <olof@lixom.net>
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- 11 Sep, 2020 1 commit
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Geert Uytterhoeven authored
Renesas R-Car V3U DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V3U (R8A779A0) SoC, shared by driver and DT source files.
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- 10 Sep, 2020 6 commits
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Yoshihiro Shimoda authored
Add support for R-Car V3U (R8A779A0) to the R-Car RST driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599470390-29719-12-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Yoshihiro Shimoda authored
Add support for identifying the R-Car V3U (R8A779A0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599470390-29719-10-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
This patch sorts each driver by description title in alphabetical order. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87a6y2v54o.wl-kuninori.morimoto.gx@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
For easy understanding of architecture and alphabetical merging, this patch uses ARM32/ARM64 for description. This prepares for sorting the menu. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87bliiv54u.wl-kuninori.morimoto.gx@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Yoshihiro Shimoda authored
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V3U (R8A779A0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Yoshihiro Shimoda authored
Add power domain indices for R-Car V3U (r8a779a0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599470390-29719-5-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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- 09 Sep, 2020 1 commit
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Sudeep Holla authored
scmi_mailbox is obtained from cinfo->transport_info and the first call to mailbox_chan_free frees the channel and sets cinfo->transport_info to NULL. Care is taken to check for non NULL smbox->chan but smbox can itself be NULL. Fix it by checking for it without which, kernel crashes with below NULL pointer dereference and eventually kernel panic. Unable to handle kernel NULL pointer dereference at virtual address 0000000000000038 Modules linked in: scmi_module(-) Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Sep 2 2020 pstate: 80000005 (Nzcv daif -PAN -UAO BTYPE=--) pc : mailbox_chan_free+0x2c/0x70 [scmi_module] lr : idr_for_each+0x6c/0xf8 Call trace: mailbox_chan_free+0x2c/0x70 [scmi_module] idr_for_each+0x6c/0xf8 scmi_remove+0xa8/0xf0 [scmi_module] platform_drv_remove+0x34/0x58 device_release_driver_internal+0x118/0x1f0 driver_detach+0x58/0xe8 bus_remove_driver+0x64/0xe0 driver_unregister+0x38/0x68 platform_driver_unregister+0x1c/0x28 scmi_driver_exit+0x38/0x44 [scmi_module] ---[ end trace 17bde19f50436de9 ]--- Kernel panic - not syncing: Fatal exception SMP: stopping secondary CPUs Kernel Offset: 0x1d0000 from 0xffff800010000000 PHYS_OFFSET: 0x80000000 CPU features: 0x0240022,25806004 Memory Limit: none ---[ end Kernel panic - not syncing: Fatal exception ]--- Link: https://lore.kernel.org/r/20200908112611.31515-1-sudeep.holla@arm.com Fixes: 5c8a47a5 ("firmware: arm_scmi: Make scmi core independent of the transport type") Cc: Cristian Marussi <cristian.marussi@arm.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Cristian Marussi <cristian.marussi@arm.com> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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- 08 Sep, 2020 2 commits
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Cristian Marussi authored
Add SCMI device for system power protocol by just adding the name "syspower" to the list of supported core protocol devices. Link: https://lore.kernel.org/r/20200907174657.32466-3-cristian.marussi@arm.comSigned-off-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Cristian Marussi authored
Add bare protocol support for SCMI system power protocol as needed by an OSPM agent: basic initialization and SYSTEM_POWER_STATE_NOTIFIER core notification support. No event-handling logic is attached to such notification.. Link: https://lore.kernel.org/r/20200907174657.32466-2-cristian.marussi@arm.comSigned-off-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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- 07 Sep, 2020 5 commits
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Rikard Falkeborn authored
These are never modified, so make them const to allow the compiler to put them in read-only memory. Link: https://lore.kernel.org/r/20200906230452.33410-4-rikard.falkeborn@gmail.comSigned-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Rikard Falkeborn authored
These are never modified, so make them const to allow drivers to make them const. Link: https://lore.kernel.org/r/20200906230452.33410-3-rikard.falkeborn@gmail.comSigned-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Rikard Falkeborn authored
The perf_ops are not modified through this pointer. Make them const to indicate that. This is in preparation to make the scmi-ops pointers in scmi_handle const. Link: https://lore.kernel.org/r/20200906230452.33410-2-rikard.falkeborn@gmail.comAcked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Florian Fainelli authored
GISB breakpoint interrupts can be raised when a breakpoint has been enabled to match a specific master and/or GISB register address. Being able to print a message, similar to those done during target abort or timeout greatly helps debug systems. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
The GISB arbiter can have a third and optional interrupt to handle GISB breakpoints. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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- 06 Sep, 2020 1 commit
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Florian Fainelli authored
Change the RACPREFDATA(x) setting to prefetch the next 256-byte line after 4 consecutive lines have been used, instead of after 2 consecutive lines. This does improve the synthetic memcpy benchmark by an additional +0.5% on top of the previous change for Cortex-A72 CPUs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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- 04 Sep, 2020 3 commits
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Florian Fainelli authored
Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs since this provides an average of a 3.8% performance increase for synthetic memcpy benchmarks. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it according to the existing values we have. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it according to the existing values we have. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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