1. 21 Mar, 2011 26 commits
  2. 15 Mar, 2011 1 commit
  3. 14 Mar, 2011 13 commits
    • Linus Torvalds's avatar
      Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300 · 59766edc
      Linus Torvalds authored
      * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300:
        MN10300: atomic_read() should ensure it emits a load
        MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not exist
        MN10300: Proper use of macros get_user() in the case of incremented pointers
      59766edc
    • Linus Torvalds's avatar
      Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus · 2990821d
      Linus Torvalds authored
      * 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (26 commits)
        MIPS: Alchemy: Fix reset for MTX-1 and XXS1500
        MIPS: MTX-1: Make au1000_eth probe all PHY addresses
        MIPS: Jz4740: Add HAVE_CLK
        MIPS: Move idle task creation to work queue
        MIPS, Perf-events: Use unsigned delta for right shift in event update
        MIPS, Perf-events: Work with the new callchain interface
        MIPS, Perf-events: Fix event check in validate_event()
        MIPS, Perf-events: Work with the new PMU interface
        MIPS, Perf-events: Work with irq_work
        MIPS: Fix always CONFIG_LOONGSON_UART_BASE=y
        MIPS: Loongson: Fix potentially wrong string handling
        MIPS: Fix GCC-4.6 'set but not used' warning in arch/mips/mm/init.c
        MIPS: Fix GCC-4.6 'set but not used' warning in ieee754int.h
        MIPS: Remove unused code from arch/mips/kernel/syscall.c
        MIPS: Fix GCC-4.6 'set but not used' warning in signal*.c
        MIPS: MSP: Fix MSP71xx bpci interrupt handler return value
        MIPS: Select R4K timer lib for all MSP platforms
        MIPS: Loongson: Remove ad-hoc cmdline default
        MIPS: Clear the correct flag in sysmips(MIPS_FIXADE, ...).
        MIPS: Add an unreachable return statement to satisfy buggy GCCs.
        ...
      2990821d
    • Linus Torvalds's avatar
      Merge branch 'x86-fixes-for-linus' of... · 869c34f5
      Linus Torvalds authored
      Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
      
      * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
        x86: ce4100: Set pci ops via callback instead of module init
        x86/mm: Fix pgd_lock deadlock
        x86/mm: Handle mm_fault_error() in kernel space
        x86: Don't check for BIOS corruption in first 64K when there's no need to
      869c34f5
    • Linus Torvalds's avatar
      Revert "oom: oom_kill_process: fix the child_points logic" · 52d3c036
      Linus Torvalds authored
      This reverts the parent commit.  I hate doing that, but it's generating
      some discussion ("half of it is right"), and since I am planning on
      doing the 2.6.38 release later today we can punt it to stable if
      required. Let's not rock the boat right now.
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      52d3c036
    • Oleg Nesterov's avatar
      oom: oom_kill_process: fix the child_points logic · dc1b83ab
      Oleg Nesterov authored
      oom_kill_process() starts with victim_points == 0.  This means that
      (most likely) any child has more points and can be killed erroneously.
      
      Also, "children has a different mm" doesn't match the reality, we should
      check child->mm != t->mm.  This check is not exactly correct if t->mm ==
      NULL but this doesn't really matter, oom_kill_task() will kill them
      anyway.
      
      Note: "Kill all processes sharing p->mm" in oom_kill_task() is wrong
      too.
      Signed-off-by: default avatarOleg Nesterov <oleg@redhat.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      dc1b83ab
    • Florian Fainelli's avatar
      MIPS: Alchemy: Fix reset for MTX-1 and XXS1500 · 9ced9757
      Florian Fainelli authored
      Since commit 32fd6901 (MIPS: Alchemy: get rid of common/reset.c)
      Alchemy-based boards use their own reset function. For MTX-1 and XXS1500,
      the reset function pokes at the BCSR.SYSTEM_RESET register, but this does
      not work. According to Bruno Randolf, this was not tested when written.
      
      Previously, the generic au1000_restart() routine called the board specific
      reset function, which for MTX-1 and XXS1500 did not work, but finally made
      a jump to the reset vector, which really triggers a system restart. Fix
      reboot for both targets by jumping to the reset vector.
      Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
      To: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/2093/Acked-by: default avatarBruno Randolf <br1@einfach.org>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      9ced9757
    • Florian Fainelli's avatar
      MIPS: MTX-1: Make au1000_eth probe all PHY addresses · bf3a1eb8
      Florian Fainelli authored
      When au1000_eth probes the MII bus for PHY address, if we do not set
      au1000_eth platform data's phy_search_highest_address, the MII probing
      logic will exit early and will assume a valid PHY is found at address 0.
      For MTX-1, the PHY is at address 31, and without this patch, the link
      detection/speed/duplex would not work correctly.
      
      CC: stable@kernel.org
      Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
      To: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/2111/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      bf3a1eb8
    • Maurus Cuelenaere's avatar
      MIPS: Jz4740: Add HAVE_CLK · ab5330eb
      Maurus Cuelenaere authored
      Jz4740 supports the clock framework but doesn't have HAVE_CLK defined,
      so define it!
      Signed-off-by: default avatarMaurus Cuelenaere <mcuelenaere@gmail.com>
      To: linux-mips@linux-mips.org
      To: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/2112/Acked-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ab5330eb
    • Maksim Rayskiy's avatar
      MIPS: Move idle task creation to work queue · 6667deb6
      Maksim Rayskiy authored
      To avoid forking usermode thread when creating an idle task, move fork_idle
      to a work queue.
      
      If kernel starts with maxcpus= option which does not bring all available
      cpus online at boot time, idle tasks for offline cpus are not created. If
      later offline cpus are hotplugged through sysfs, __cpu_up is called in
      the context of the user task, and fork_idle copies its non-zero mm
      pointer.  This causes BUG() in per_cpu_trap_init.
      
      This also avoids issues with resource limits of the CPU writing to sysfs,
      containers, maybe others.
      Signed-off-by: default avatarMaksim Rayskiy <mrayskiy@broadcom.com>
      To: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/2070/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6667deb6
    • Deng-Cheng Zhu's avatar
      MIPS, Perf-events: Use unsigned delta for right shift in event update · ba9786f3
      Deng-Cheng Zhu authored
      Leverage the commit for ARM by Will Deacon:
      
      - 446a5a8b
          ARM: 6205/1: perf: ensure counter delta is treated as unsigned
      
          Hardware performance counters on ARM are 32-bits wide but atomic64_t
          variables are used to represent counter data in the hw_perf_event structure.
      
          The armpmu_event_update function right-shifts a signed 64-bit delta variable
          and adds the result to the event count. This can lead to shifting in sign-bits
          if the MSB of the 32-bit counter value is set. This results in perf output
          such as:
      
           Performance counter stats for 'sleep 20':
      
           18446744073460670464  cycles             <-- 0xFFFFFFFFF12A6000
                  7783773  instructions             #      0.000 IPC
                      465  context-switches
                      161  page-faults
                  1172393  branches
      
             20.154242147  seconds time elapsed
      
          This patch ensures that the delta value is treated as unsigned so that the
          right shift sets the upper bits to zero.
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Acked-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
      To: a.p.zijlstra@chello.nl
      To: fweisbec@gmail.com
      To: will.deacon@arm.com
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: wuzhangjin@gmail.com
      Cc: paulus@samba.org
      Cc: mingo@elte.hu
      Cc: acme@redhat.com
      Cc: matt@console-pimps.org
      Cc: sshtylyov@mvista.com
      Patchwork: http://patchwork.linux-mips.org/patch/2015/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      ba9786f3
    • Deng-Cheng Zhu's avatar
      MIPS, Perf-events: Work with the new callchain interface · 98f92f2f
      Deng-Cheng Zhu authored
      This is the MIPS part of the following commits by Frederic Weisbecker:
      
      - f72c1a93
          perf: Factorize callchain context handling
      
          Store the kernel and user contexts from the generic layer instead
          of archs, this gathers some repetitive code.
      
      - 56962b44
          perf: Generalize some arch callchain code
      
          - Most archs use one callchain buffer per cpu, except x86 that needs
            to deal with NMIs. Provide a default perf_callchain_buffer()
            implementation that x86 overrides.
      
          - Centralize all the kernel/user regs handling and invoke new arch
            handlers from there: perf_callchain_user() / perf_callchain_kernel()
            That avoid all the user_mode(), current->mm checks and so...
      
          - Invert some parameters in perf_callchain_*() helpers: entry to the
            left, regs to the right, following the traditional (dst, src).
      
      - 70791ce9
          perf: Generalize callchain_store()
      
          callchain_store() is the same on every archs, inline it in
          perf_event.h and rename it to perf_callchain_store() to avoid
          any collision.
      
          This removes repetitive code.
      
      - c1a65932
          perf: Drop unappropriate tests on arch callchains
      
          Drop the TASK_RUNNING test on user tasks for callchains as
          this check doesn't seem to make any sense.
      
          Also remove the tests for !current that is not supposed to
          happen and current->pid as this should be handled at the
          generic level, with exclude_idle attribute.
      Reported-by: default avatarWu Zhangjin <wuzhangjin@gmail.com>
      Acked-by: default avatarFrederic Weisbecker <fweisbec@gmail.com>
      Acked-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
      To: a.p.zijlstra@chello.nl
      To: will.deacon@arm.com
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: paulus@samba.org
      Cc: mingo@elte.hu
      Cc: acme@redhat.com
      Cc: dengcheng.zhu@gmail.com
      Cc: matt@console-pimps.org
      Cc: sshtylyov@mvista.com
      Patchwork: http://patchwork.linux-mips.org/patch/2014/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      98f92f2f
    • Deng-Cheng Zhu's avatar
      MIPS, Perf-events: Fix event check in validate_event() · c049b6a5
      Deng-Cheng Zhu authored
      Ignore events that are in off/error state or belong to a different PMU.
      
      This patch originates from the following commit for ARM by Will Deacon:
      
      - 65b4711f
          ARM: 6352/1: perf: fix event validation
      
          The validate_event function in the ARM perf events backend has the
          following problems:
      
          1.) Events that are disabled count towards the cost.
          2.) Events associated with other PMUs [for example, software events or
              breakpoints] do not count towards the cost, but do fail validation,
              causing the group to fail.
      
          This patch changes validate_event so that it ignores events in the
          PERF_EVENT_STATE_OFF state or that are scheduled for other PMUs.
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Acked-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
      To: a.p.zijlstra@chello.nl
      To: fweisbec@gmail.com
      To: will.deacon@arm.com
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: wuzhangjin@gmail.com
      Cc: paulus@samba.org
      Cc: mingo@elte.hu
      Cc: acme@redhat.com
      Cc: dengcheng.zhu@gmail.com
      Cc: matt@console-pimps.org
      Cc: sshtylyov@mvista.com
      Cc: ddaney@caviumnetworks.com
      Patchwork: http://patchwork.linux-mips.org/patch/2013/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      c049b6a5
    • Deng-Cheng Zhu's avatar
      MIPS, Perf-events: Work with the new PMU interface · 404ff638
      Deng-Cheng Zhu authored
      This is the MIPS part of the following commits by Peter Zijlstra:
      
      - a4eaf7f1
          perf: Rework the PMU methods
      
          Replace pmu::{enable,disable,start,stop,unthrottle} with
          pmu::{add,del,start,stop}, all of which take a flags argument.
      
          The new interface extends the capability to stop a counter while
          keeping it scheduled on the PMU. We replace the throttled state with
          the generic stopped state.
      
          This also allows us to efficiently stop/start counters over certain
          code paths (like IRQ handlers).
      
          It also allows scheduling a counter without it starting, allowing for
          a generic frozen state (useful for rotating stopped counters).
      
          The stopped state is implemented in two different ways, depending on
          how the architecture implemented the throttled state:
      
           1) We disable the counter:
              a) the pmu has per-counter enable bits, we flip that
              b) we program a NOP event, preserving the counter state
      
           2) We store the counter state and ignore all read/overflow events
      
      For MIPSXX, the stopped state is implemented in the way of 1.b as above.
      
      - 33696fc0
          perf: Per PMU disable
      
          Changes perf_disable() into perf_pmu_disable().
      
      - 24cd7f54
          perf: Reduce perf_disable() usage
      
          Since the current perf_disable() usage is only an optimization,
          remove it for now. This eases the removal of the __weak
          hw_perf_enable() interface.
      
      - b0a873eb
          perf: Register PMU implementations
      
          Simple registration interface for struct pmu, this provides the
          infrastructure for removing all the weak functions.
      
      - 51b0fe39
          perf: Deconstify struct pmu
      
          sed -ie 's/const struct pmu\>/struct pmu/g' `git grep -l "const struct pmu\>"`
      Reported-by: default avatarWu Zhangjin <wuzhangjin@gmail.com>
      Acked-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
      To: a.p.zijlstra@chello.nl
      To: fweisbec@gmail.com
      To: will.deacon@arm.com
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: wuzhangjin@gmail.com
      Cc: paulus@samba.org
      Cc: mingo@elte.hu
      Cc: acme@redhat.com
      Cc: dengcheng.zhu@gmail.com
      Cc: matt@console-pimps.org
      Cc: sshtylyov@mvista.com
      Cc: ddaney@caviumnetworks.com
      Patchwork: http://patchwork.linux-mips.org/patch/2012/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      404ff638