- 31 Jul, 2019 40 commits
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Alex Deucher authored
And fix up the fallout. Acked-by:
Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
And fix the fallout. Acked-by:
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Alex Deucher authored
And fix the fallout. Acked-by:
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Alex Deucher authored
Unused. Acked-by:
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Alex Deucher authored
Unused. Acked-by:
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Evan Quan authored
Per current logics, the features to enable are determined together by driver and pptable. This is not efficient in co-debug with firmware team. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Hawking Zhang authored
we should pass irq type, instead of irq client id, to irq_get/put interface Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Evan Quan authored
The power limit retrieval should be done per asic. Since we may need to lookup in the pptable and that's really asic specific. Signed-off-by:
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Evan Quan authored
There may be 1Mhz delta between target and actual frequency. That should be taken into consideration for current level check. Signed-off-by:
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Evan Quan authored
Enable arcturus UMD PSTATE support. Signed-off-by:
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Evan Quan authored
Make sure we can still get the accurate gfxclk/uclk/socclk frequency even on dpm disabled. Signed-off-by:
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Kevin Wang authored
remove redundacy debug log in smu. eg: [ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38 [ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38 [ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled [ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38 Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Evan Quan authored
Those bitmask prefixed by "SMU_" should be used. Signed-off-by:
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Evan Quan authored
Add missing feature maps for arcturus. Signed-off-by:
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Evan Quan authored
Support arcturus fan speed retrieval. Signed-off-by:
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Evan Quan authored
Enable arcturus real-time clock retrieval. Signed-off-by:
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Evan Quan authored
Support sensor reading for gpu loading, power and temperatures. Signed-off-by:
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Evan Quan authored
Initialize arcturus SMU metrics table. Signed-off-by:
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Evan Quan authored
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by:
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Evan Quan authored
No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN. v2: check return value of smu_feature_set_enabled Signed-off-by:
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Evan Quan authored
Commonly used for VCN powergate status retrieval for SW SMU. Signed-off-by:
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Evan Quan authored
Enable VCN powergate status report on Raven. Signed-off-by:
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Evan Quan authored
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by:
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Le Ma authored
Update for sdma ras ecc_irq and other minors. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20 reusable for Arcturus, align this base offset with Vega20. Signed-off-by:
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Evan Quan authored
As for now, only "Prefetcher" is guarded to be working from SMU firmware. Signed-off-by:
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Evan Quan authored
Arcturus VCN should powergate in the way as Navi. Signed-off-by:
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Evan Quan authored
Arcturus powerplay is ready to use. Signed-off-by:
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Evan Quan authored
Initialize base address for those IPs which are used in powerplay. Signed-off-by:
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Evan Quan authored
Enable arcturus SW SMU routines. Signed-off-by:
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Evan Quan authored
Arcturus ASIC specific powerplay interfaces. V2: correct SMU msg naming drop unnecessary debugs V3: rebase (Alex) Signed-off-by: -
Evan Quan authored
Correct header and fix typo. Signed-off-by:
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Evan Quan authored
It guides how driver should interface with SMU in arcturus. Signed-off-by:
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Evan Quan authored
This is especially useful in early bring up phase. v2: disabled by default (Alex) Signed-off-by:
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Evan Quan authored
New smcdpminfo table used in arcturus. Signed-off-by:
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Jay Cornwall authored
VCC moved out of user SGPR allocation in gfx10. It's now stored in SGPRs 106-107. Also fixes incorrect SGPR read offsets. Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Acked-by:
shaoyunl <shaoyun.liu@amd.com> Signed-off-by:
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Jay Cornwall authored
These moved from SGPRs in gfx9 to HWREG in gfx10. Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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Jay Cornwall authored
Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes). Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We were previously forcing the uclk for every state to max and reducing the switch time to prevent uclk switching from occuring. This workaround was previously needed in order to avoid hangs + underflow under certain display configurations. Now that DC has the proper fix complete we can drop the hacks and improve power for most display configurations. [How] We still need the function pointers hooked up to grab the real uclk states from pplib. The rest of the prior hack can be reverted. The key requirements here are really just DC support, updated firmware, and support for disabling p-state support when needed in pplib/smu. When these requirements are met uclk switching works without underflow or hangs. Fixes: 02316e96 ("drm/amd/display: Force uclk to max for every state") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] In order to support uclk switching on NV10 the SOC bounding box needs to be updated. [How] We currently read the constants from the gpu info FW, but supporting workarounds in DC for different versions of the FW adds additional complexity to the codebase. NV10 has been released so it's cleanest to keep the bounding box and source code in sync by embedding the bounding box like we do for other ASICs. Fixes: 02316e96 ("drm/amd/display: Force uclk to max for every state") Signed-off-by:
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