- 04 Oct, 2015 4 commits
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Wei Fang authored
Need to free the memory allocated for 'fd' if failed to read all of the remainder name. Signed-off-by:
Wei Fang <fangwei1@huawei.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
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Vladimir Zapolskiy authored
According to LPC32xx User's Manual all values measured in clock cycles are programmable from 1 to 16 clocks (4 bits) starting from 0 in bitfield, the current version of calculated clock cycles is too conservative. Correctness of 0 bitfield value (i.e. programmed 1 clock timing) is proven with actual NAND chip devices. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
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Vladimir Zapolskiy authored
In case if quotient of controller clock rate to device clock rate does not fit into 4 bit value, choose the maximum acceptable value 0xF, which stands for 16 clocks. Signed-off-by:
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Vladimir Zapolskiy authored
No functional change, move bitfield calculations to macro definitions with added clock rate argument, which are in turn defined by new common SLCTAC_CLOCKS(c, n, s) macro definition. Signed-off-by:
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- 02 Oct, 2015 9 commits
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Boris BREZILLON authored
Use the nand_check_erased_ecc_chunk() function to test if the ECC error was triggered by an erased page containing a few bitflips. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
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Boris BREZILLON authored
sunxi_nfc_user_data_to_buf() is exposed as an inline function, replace the NFC_BUF_TO_USER_DATA() macro by an inline function to be consistent. Signed-off-by:
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Boris BREZILLON authored
The ECC engine is protecting a few OOB bytes. Retrieve them from the USER_DATA register instead of reading them in raw mode (ie without the ECC protection). Signed-off-by:
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Boris BREZILLON authored
Add helper functions to factorize the code dealing extra OOB bytes in the normal and syndrome ECC implementations. Signed-off-by:
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Boris BREZILLON authored
The sunxi_nfc_hw_ecc_read/write_chunk() functions have been created to factorize the code in the normal and syndrome ECC implementation. Make use of them where appropriate. Signed-off-by:
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Boris BREZILLON authored
The logic behind normal and syndrome ECC handling is pretty much the same, the only difference is the ECC bytes placement. Create two functions to read/write ECC chunks. Those functions will later be used by the sunxi_nfc_hw_ecc_read/write_page() and sunxi_nfc_hw_syndrome_ecc_read/write_page() functions. Signed-off-by:
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Boris BREZILLON authored
The code used to enable/disable the hardware ECC engine is repeated in a lot of places. Create two functions to avoid code duplication. Signed-off-by:
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Stefan Roese authored
Remove the BUG macros and return with error (if possible) instead. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Stefan Roese authored
Remove tab in empty line. Signed-off-by:
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- 01 Oct, 2015 1 commit
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Boris BREZILLON authored
The ->init_size() hook was introduced to let NAND controller drivers support NAND devices that could not be described in the nand_ids table. Since then, the core has added support for extended-id parsing and full-id description, thus allowing to describe pretty much all existing NANDs. Moreover, this hook is not used by any mainline driver, and should not be used by new drivers, because detecting the NAND chip is not something controller specific. Signed-off-by:
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- 30 Sep, 2015 9 commits
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Brian Norris authored
The cmdlinepart parser is already supported in the default probe. Signed-off-by: -
Brian Norris authored
These really aren't needed, especially now that we embed the soc struct in our private struct, so we can stash things there if needed. Signed-off-by: -
Brian Norris authored
Removes an unnecessary allocation and saves a little bit of pointer chasing. Signed-off-by: -
Brian Norris authored
Removes an unnecessary allocation and saves a little bit of pointer chasing. Signed-off-by: -
Boris BREZILLON authored
Suffix mask macros with _MSK and add new helper macros to avoid manually shifting values. Signed-off-by:
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Brian Norris authored
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Brian Norris authored
This must have been implicitly included on the builds I tested. Reported by numerous test bots: drivers/mtd/nand/vf610_nfc.c: In function 'vf610_nfc_resume': drivers/mtd/nand/vf610_nfc.c:660:2: error: implicit declaration of function 'pinctrl_pm_select_default_state' [-Werror=implicit-function-declaration] pinctrl_pm_select_default_state(dev); ^ Signed-off-by:Stefan Agner <stefan@agner.ch>
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Boris BREZILLON authored
If we fail to allocate a partition structure in the middle of the partition creation process, the already allocated partitions are never removed, which means they are still present in the partition list and their resources are never freed. Signed-off-by:
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Brian Norris authored
This reverts commit 7827e3ac. There are some 64-bit arithmetic issues on some architectures, so let's wait until we get a better patch for this. Signed-off-by:
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- 29 Sep, 2015 17 commits
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Dongsheng Yang authored
We should prevent user to erasing mtd device with an unaligned offset or length. Signed-off-by:
Dongsheng Yang <yangds.fnst@cn.fujitsu.com> Signed-off-by:
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Stefan Agner authored
Signed-off-by:
Bill Pringlemeir <bpringlemeir@nbsps.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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Stefan Agner authored
This adds hardware ECC support using the BCH encoder in the NFC IP. The ECC encoder supports up to 32-bit correction by using 60 error correction bytes. There is no sub-page ECC step, ECC is calculated always across the whole page (up to 2k pages). Limitations: - HW ECC: Only 2K page with 64+ OOB. - HW ECC: Only 24 and 32-bit error correction implemented. Raw writes have been tested using the generic nand_write_page_raw implementation. However, raw reads are currently not possible because the controller need to know whether we are going to use the ECC mode already at NAND_CMD_READ0 command time. At this point we do not have the information whether it is a raw read or a regular read at driver level... Signed-off-by:
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Stefan Agner authored
This driver supports Freescale NFC (NAND flash controller) found on Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has been tested using 8-bit and 16-bit NAND interface on the ARM based Vybrid SoC VF500 and VF610 platform. parameter page reading. Limitations: - Untested on MPC5125 and M54418. - DMA and pipelining not used. - 2K pages or less. - No chip select, one NAND chip per controller. - No hardware ECC. Some paths have been hand-optimized and evaluated by measurements made using mtd_speedtest.ko on a 100MB MTD partition. Colibri VF50 eb write % eb read % page write % page read % rel/opt 5175 11537 4560 11039 opt 5164 -0.21 11420 -1.01 4737 +3.88 10918 -1.10 none 5113 -1.20 11352 -1.60 4490 -1.54 10865 -1.58 Colibri VF61 eb write % eb read % page write % page read % rel/opt 5766 13096 5459 12846 opt 5883 +2.03 13064 -0.24 5561 +1.87 12802 -0.34 none 5701 -1.13 12980 -0.89 5488 +0.53 12735 -0.86 rel = using readl_relaxed/writel_relaxed in optimized paths opt = hand-optimized by combining multiple accesses into one read/write The measurements have not been statistically verfied, hence use them with care. The author came to the conclusion that using the relaxed variants of readl/writel are not worth the additional code. Signed-off-by:Albert ARIBAUD <albert.aribaud@3adev.fr> Signed-off-by:
Alexey Klimov <klimov.linux@gmail.com> Signed-off-by:
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Brian Norris authored
After a bit of poking around wondering why my 32-bit user-space can't seem to send a proper ioctl(BLKPG) to an MTD on my 64-bit kernel (ARM64), I noticed that struct blkpg_ioctl_arg is actually pretty unsuitable for use in the ioctl() ABI, due to its use of raw pointers, and its lack of alignment/packing restrictions (32-bit arch'es tend to pack the 4 fields into 4 32-bit words, whereas 64-bit arch'es would add padding after the third int, and make this 6 32-bit words). Anyway, this means BLKPG deserves some special compat_ioctl handling. Do the conversion in a small shim for MTD. block/compat_ioctl.c already has compat support for the block subsystem, but it does so by a re-marshalling data to/from user-space (see compat_blkpg_ioctl()). Personally, I think this approach is cleaner. Tested only on MTD, with an ARM32 user space on an ARM64 kernel. Signed-off-by: -
Brian Norris authored
Tested only with single I/O, but the datasheet says it supports dual and quad. Signed-off-by: -
Furquan Shaikh authored
This patch fixes timeout issues seen on large NOR flash (e.g., 16MB w25q128fw) when using ioctl(MEMERASE) with offset=0 and length=16M. The input parameters matter because spi_nor_erase() uses a different code path for full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7) opcode. Fix: use a different timeout for full-chip erase than for other commands. While most operations can be expected to perform relatively similarly across a variety of NOR flash types and sizes (and therefore might as well use a similar timeout to keep things simple), full-chip erase is unique, because the time it typically takes to complete: (1) is much larger than most operations and (2) scales with the size of the flash. Let's base our timeout on the original comments stuck here -- that a 2MB flash requires max 40s to erase. Small survey of a few flash datasheets I have lying around: Chip Size (MB) Max chip erase (seconds) ---- -------- ------------------------ w25q32fw 4 50 w25q64cv 8 30 w25q64fw 8 100 w25q128fw 16 200 s25fl128s 16 ~256 s25fl256s 32 ~512 From this data, it seems plenty sufficient to say we need to wait for 40 seconds for each 2MB of flash. After this change, it might make some sense to decrease the timeout for everything else, as even the most extreme operations (single block erase?) shouldn't take more than a handful of seconds. But for safety, let's leave it as-is. It's only an error case, after all, so we don't exactly need to optimize it. Signed-off-by:
Furquan Shaikh <furquan@google.com> Signed-off-by:
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Yao Yuan authored
It is a 512KiB flash with 4 KiB erase sectors. Signed-off-by:
Yuan Yao <yao.yuan@freescale.com> Signed-off-by:
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Tom Englund authored
The module pcmciamtd doesn't generate a mtd node for PRETEC 4MB SRAM cards without the id and hash added to pcmciamtd.c Tested on 3 different 4MB pretec sram cards. Signed-off-by:
Tom Englund <tomenglund26@gmail.com> Signed-off-by:
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Graham Moore authored
Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. Signed-off-by:
Graham Moore <grmoore@opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by:
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Enrico Jorns authored
A read id operation followed by 0x00 reads the device ID while a read id operation followed by 0x20 reads the possible ONFI identifier. As the READID function did not propagate the second id parameter but had a hard-coded call for 0x90 0x00, reading the ONFI identifier was not possible and thus chips werde not detected (tested with MT29F8G08ABABAWP) Signed-off-by:
Enrico Jorns <ejo@pengutronix.de> Signed-off-by:
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fangwei authored
c->oobbuf hasn't been kmalloced in jffs2_dataflash_setup, so there is no need to free it. Signed-off-by:
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Brian Norris authored
This driver uses some custom macros for printing. Let's use the standard pr_fmt()/pr_{err,warn}(). Signed-off-by: -
Brian Norris authored
I'm not sure why we have a PAGE_SIZE restriction on this partition parser. If we really wanted the restriction, I would expect it to be a restriction for *all* parsers, so we'd move it to the MTD core At any rate, while small partitions may not be useful (they'll often be smaller than the eraseblock size and therefore can only be used read-only), they still have use as a read-only partition. This restriction is especially annoying because it aborts the entire MTD's cmdline parsing, leaving it unpartitioned. So, let's kill the restriction and only check for zero-sized partitions, which I expect we don't want to allow. Signed-off-by: -
Joachim Eastwood authored
s25fl016k can be found on Embedded Artists' LPC4357 Developer's Kit where is used in quad mode by the LPC4357 SPIFI controller. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
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Johannes Thumshirn authored
Destroy mtd_idr on module_exit, reclaiming the allocated memory. This was detected by the following semantic patch (written by Luis Rodriguez <mcgrof@suse.com>) <SmPL> @ defines_module_init @ declarer name module_init, module_exit; declarer name DEFINE_IDR; identifier init; @@ module_init(init); @ defines_module_exit @ identifier exit; @@ module_exit(exit); @ declares_idr depends on defines_module_init && defines_module_exit @ identifier idr; @@ DEFINE_IDR(idr); @ on_exit_calls_destroy depends on declares_idr && defines_module_exit @ identifier declares_idr.idr, defines_module_exit.exit; @@ exit(void) { ... idr_destroy(&idr); ... } @ missing_module_idr_destroy depends on declares_idr && defines_module_exit && !on_exit_calls_destroy @ identifier declares_idr.idr, defines_module_exit.exit; @@ exit(void) { ... +idr_destroy(&idr); } </SmPL> Signed-off-by:Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by:
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Robert Jarzmik authored
After the conversion of pxa architecture to common clock framework, the NAND clock can be disabled on driver exit. In this case, it happens that if the driver used the NAND and set the DFI arbitration bit, the next access to a static memory controller area, such as an ethernet card, will stall the system bus, and the core will be stalled forever. This is especially true on pxa31x SoCs, where the NDCR was augmented with a new bit to prevent this lockups by giving full ownership of the DFI arbiter to the SMC, in change SCr#6. Fix this by clearing the DFI arbritration bit in driver exit. This effectively prevents a lockup on zylonite when removing pxa3xx-nand module, and using ethernet afterwards. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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