- 19 Sep, 2019 7 commits
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Stephen Boyd authored
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names * clk-bulk-fix: clk: Make clk_bulk_get_all() return a valid "id" * clk-at91: clk: at91: allow 24 Mhz clock as input for PLL clk: at91: select parent if main oscillator or bypass is enabled clk: at91: fix update bit maps on CFG_MOR write * clk-sprd: clk: sprd: add missing kfree
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Stephen Boyd authored
Merge branches 'clk-cdce-regulator', 'clk-bcm', 'clk-evict-parent-cache' and 'clk-actions' into clk-next - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Evict parents from parent cache when they're unregistered * clk-cdce-regulator: clk: clk-cdce925: Add regulator support dt-bindings: clock: cdce925: Add regulator documentation * clk-bcm: clk: bcm2835: Mark PLLD_PER as CRITICAL clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support clk: bcm2835: Introduce SoC specific clock registration dt-bindings: bcm2835-cprman: Add bcm2711 support * clk-evict-parent-cache: clk: Evict unregistered clks from parent caches * clk-actions: clk: actions: Fix factor clk struct member access
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Stephen Boyd authored
* clk-renesas: clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain dt-bindings: clk: emev2: Rename bindings documentation file clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper * clk-rockchip: clk: rockchip: Add clock controller for the rk3308 clk: rockchip: Add dt-binding header for rk3308 dt-bindings: Add bindings for rk3308 clock controller clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver * clk-const: clk: spear: Make structure i2s_sclk_masks constant * clk-simplify: clk/ti: Use kmemdup rather than duplicating its implementation clk: fix devm_platform_ioremap_resource.cocci warnings
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Stephen Boyd authored
- Set clk_init_data pointer inside clk_hw to NULL after registration * clk-init-destroy: clk: Overwrite clk_hw::init with NULL during clk_register() clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered clk: ti: Don't reference clk_init_data after registration clk: qcom: Remove error prints from DFS registration rtc: sun6i: Don't reference clk_init_data after registration clk: zx296718: Don't reference clk_init_data after registration clk: milbeaut: Don't reference clk_init_data after registration clk: socfpga: deindent code to proper indentation phy: ti: am654-serdes: Don't reference clk_init_data after registration clk: sprd: Don't reference clk_init_data after registration clk: socfpga: Don't reference clk_init_data after registration clk: sirf: Don't reference clk_init_data after registration clk: qcom: Don't reference clk_init_data after registration clk: meson: axg-audio: Don't reference clk_init_data after registration clk: lochnagar: Don't reference clk_init_data after registration clk: actions: Don't reference clk_init_data after registration * clk-doc: clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h clk: Document of_parse_clkspec() some more clk: Remove extraneous 'for' word in comments * clk-imx: (32 commits) clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: imx: imx8mn: fix audio pll setting clk: imx8mn: Add necessary frequency support for ARM PLL table clk: imx8mn: Add missing rate_count assignment for each PLL structure clk: imx8mn: fix int pll clk gate clk: imx8mn: Add GIC clock clk: imx8mn: Fix incorrect parents clk: imx8mm: Fix incorrect parents clk: imx8mq: Fix sys3 pll references clk: imx8mq: Unregister clks when of_clk_add_provider failed clk: imx8mm: Unregister clks when of_clk_add_provider failed clk: imx8mq: Mark AHB clock as critical clk: imx8mn: Keep uart clocks on for early console clk: imx: Remove unused function statement clk: imx7ulp: Make sure earlycon's clock is enabled clk: imx8mm: Switch to platform driver clk: imx: imx8mm: fix audio pll setting ... * clk-allwinner: clk: sunxi-ng: h6: Allow I2S to change parent rate clk: sunxi-ng: v3s: add Allwinner V3 support clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add the missing PLL_DDR1
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Stephen Boyd authored
- Support qcom SM8150 RPMh clks - Set floor ops for qcom sd clks - Support qcom QCS404 WCSS clks - Support for Mediatek MT6779 SoCs - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) * clk-qcom: clk: qcom: rcg: Return failure for RCG update clk: qcom: fix QCS404 TuringCC regmap clk: qcom: clk-rpmh: Add support for SM8150 dt-bindings: clock: Document SM8150 rpmh-clock compatible clk: qcom: clk-rpmh: Convert to parent data scheme dt-bindings: clock: Document the parent clocks clk: qcom: gcc: Use floor ops for SDCC clocks clk: qcom: gcc-qcs404: Use floor ops for sdcc clks clk: qcom: gcc-sdm845: Use floor ops for sdcc clks clk: qcom: define probe by index API as common API clk: qcom: Add WCSS gcc clock control for QCS404 clk: qcom: msm8916: Don't build by default clk: qcom: gcc: Add global clock controller driver for SM8150 dt-bindings: clock: Document gcc bindings for SM8150 clk: qcom: clk-alpha-pll: Add support for Trion PLLs clk: qcom: clk-alpha-pll: Remove post_div_table checks clk: qcom: clk-alpha-pll: Remove unnecessary cast * clk-mtk: clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider clk: mediatek: Register clock gate with device clk: mediatek: add pericfg clocks for MT8183 dt-bindings: clock: mediatek: add pericfg for MT8183 clk: mediatek: Add MT6779 clock support clk: mediatek: Add dt-bindings for MT6779 clocks dt-bindings: mediatek: bindings for MT6779 clk clk: reset: Modify reset-controller driver * clk-armada: clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: mvebu: ap806: Fix clock name for the cluster clk: mvebu: add CPU clock driver for Armada 7K/8K clk: mvebu: add helper file for Armada AP and CP clocks dt-bindings: ap806: add the cluster clock node in the syscon file * clk-ingenic: clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro clk: ingenic/jz4740: Fix "pll half" divider not read/written properly * clk-meson: (23 commits) clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock clk: meson: g12a: add support for SM1 GP1 PLL dt-bindings: clk: meson: add sm1 periph clock controller bindings clk: meson: axg-audio: add g12a reset support dt-bindings: clock: meson: add resets to the audio clock controller clk: meson: g12a: expose CPUB clock ID for G12B clk: meson: g12a: add notifiers to handle cpu clock change clk: meson: add g12a cpu dynamic divider driver clk: core: introduce clk_hw_set_parent() clk: meson: remove clk input helper clk: meson: remove ee input bypass clocks clk: meson: clk-regmap: migrate to new parent description method clk: meson: meson8b: migrate to the new parent description method clk: meson: axg: migrate to the new parent description method clk: meson: gxbb: migrate to the new parent description method clk: meson: g12a: migrate to the new parent description method clk: meson: remove ao input bypass clocks clk: meson: axg-aoclk: migrate to the new parent description method clk: meson: gxbb-aoclk: migrate to the new parent description method ...
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Stephen Boyd authored
Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk-data' and 'clk-debugfs' into clk-next - Add SDIO gate to aspeed driver - Support aspeed AST2600 SoC - Add missing of_node_put() calls in various clk drivers - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs * clk-aspeed: clk: Add support for AST2600 SoC clk: aspeed: Move structures to header clk: aspeed: Add SDIO gate * clk-unused: clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0' clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops' clk: composite: Drop unused clk.h include clk: Si5341/Si5340: remove redundant assignment to n_den clk: qoriq: Fix -Wunused-const-variable * clk-of-node-put: clk: ti: dm814x: Add of_node_put() to prevent memory leak clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup() clk: davinci: pll: Add of_node_put() in of_davinci_pll_init() clk: versatile: Add of_node_put() in cm_osc_setup() * clk-const-bulk-data: clk: Constify struct clk_bulk_data * where possible * clk-debugfs: clk: Drop !clk checks in debugfs dumping clk: Use seq_puts() in possible_parent_show() clk: Assert prepare_lock in clk_core_get_boundaries clk: Add clk_min/max_rate entries in debugfs
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Stephen Boyd authored
These recursive functions have checks for !clk being passed in, but the callers are always looping through lists and therefore the pointers can't be NULL. Drop the checks to simplify the code. Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190826234729.145593-1-sboyd@kernel.org
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- 18 Sep, 2019 14 commits
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Peng Fan authored
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Suggested-by:
Jacky Bai <ping.bai@nxp.com> Reviewed-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.comSigned-off-by:
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Peng Fan authored
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Suggested-by:
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Peng Fan authored
When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dc ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by:
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Peng Fan authored
According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to output unstable clock until lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. In the end of set rate, BYPASS will be cleared. When prepare clock, also need to take care to avoid glitch. So we also follow Spec to set BYPASS before RESETB changed from 0 to 1. And add a check if the RESETB is already 0, directly return 0; Fixes: 8646d4dc ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by:
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Ben Peled authored
Add driver support for AP807 clock. Signed-off-by:
Ben Peled <bpeled@marvell.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.comSigned-off-by:
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Ben Peled authored
Factor out the code that is only useful to AP806 so it will be easier to support AP807. No functional changes. Signed-off-by:
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Omri Itach authored
Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK is half the rate of DDR clock, so its derrived from Sample At Reset configuration. The clock frequency is required for AP806 AXI monitor profiling feature. Signed-off-by:
Omri Itach <omrii@marvell.com> Signed-off-by:
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Miquel Raynal authored
"SaR" means Sample at Reset. DIP switches can be changed on the board, their states at reset time is available through a register read. Signed-off-by:
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Ben Peled authored
Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU clocks. Signed-off-by:
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Christine Gharzuzi authored
This patch allows same flow to be executed on chips with different register mappings like AP806 and, in the future, AP807. Note: this patch has no functional effect, and only prepares the driver for additional chips to be supported by retrieving the right device data depenging on the compatible property. Signed-off-by:
Christine Gharzuzi <chrisg@marvell.com> Signed-off-by:
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Miquel Raynal authored
Add AP807 clock compatible to the bindings. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Miquel Raynal authored
Add AP807 CPU clock compatible to the bindings. Signed-off-by:
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Chunyan Zhang authored
The number of config registers for different pll clocks probably are not same, so we have to use malloc, and should free the memory before return. Fixes: 3e37b005 ("clk: sprd: add adjustable pll support") Signed-off-by:
Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by:
Chunyan Zhang <zhang.lyra@gmail.com> Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.comSigned-off-by:
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Eugen Hristev authored
The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by:
Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.comAcked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver") Signed-off-by:
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- 17 Sep, 2019 14 commits
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Bjorn Andersson authored
The adreno driver expects the "id" field of the returned clk_bulk_data to be filled in with strings from the clock-names property. But due to the use of kmalloc_array() in of_clk_bulk_get_all() it receives a list of bogus pointers instead. Zero-initialize the "id" field and attempt to populate with strings from the clock-names property to resolve both these issues. Fixes: 616e45df ("clk: add new APIs to operate on all available clocks") Fixes: 8e3e791d ("drm/msm: Use generic bulk clock function") Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20190913024029.2640-1-bjorn.andersson@linaro.orgReviewed-by:
Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
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Manivannan Sadhasivam authored
Since the helper "owl_factor_helper_round_rate" is shared between factor and composite clocks, using the factor clk specific helper function like "hw_to_owl_factor" to access its members will create issues when called from composite clk specific code. Hence, pass the "factor_hw" struct pointer directly instead of fetching it using factor clk specific helpers. This issue has been observed when a composite clock like "sd0_clk" tried to call "owl_factor_helper_round_rate" resulting in pointer dereferencing error. While we are at it, let's rename the "clk_val_best" function to "owl_clk_val_best" since this is an owl SoCs specific helper. Fixes: 4bb78fc9 ("clk: actions: Add factor clock support") Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Taniya Das authored
In case of update config failure, return -EBUSY, so that consumers could handle the failure gracefully. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.orgSigned-off-by:
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Lubomir Rintel authored
Sometimes an extraneous "---help---" follows "help". That is probably a copy&paste error stemming from their inconsistent use. Remove those. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20190822093126.594013-1-lkundrak@v3.skSigned-off-by:
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Masahiro Yamada authored
Add a header include guard just in case. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Link: https://lkml.kernel.org/r/20190820030536.1181-1-yamada.masahiro@socionext.comSigned-off-by:
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Stephen Boyd authored
We leave a dangling pointer in each clk_core::parents array that has an unregistered clk as a potential parent when that clk_core pointer is freed by clk{_hw}_unregister(). It is impossible for the true parent of a clk to be set with clk_set_parent() once the dangling pointer is left in the cache because we compare parent pointers in clk_fetch_parent_index() instead of checking for a matching clk name or clk_hw pointer. Before commit ede77858 ("clk: Remove global clk traversal on fetch parent index"), we would check clk_hw pointers, which has a higher chance of being the same between registration and unregistration, but it can still be allocated and freed by the clk provider. In fact, this has been a long standing problem since commit da0f0b2c ("clk: Correct lookup logic in clk_fetch_parent_index()") where we stopped trying to compare clk names and skipped over entries in the cache that weren't NULL. There are good (performance) reasons to not do the global tree lookup in cases where the cache holds dangling pointers to parents that have been unregistered. Let's take the performance hit on the uncommon registration path instead. Loop through all the clk_core::parents arrays when a clk is unregistered and set the entry to NULL when the parent cache entry and clk being unregistered are the same pointer. This will fix this problem and avoid the overhead for the "normal" case. Based on a patch by Bjorn Andersson. Fixes: da0f0b2c ("clk: Correct lookup logic in clk_fetch_parent_index()") Reviewed-by:Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by:
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Weiyi Lu authored
Enable the runtime PM support and forward the struct device pointer for registration of MT8183 mcucfg clocks. Signed-off-by:
Weiyi Lu <weiyi.lu@mediatek.com> Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.comSigned-off-by:
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Weiyi Lu authored
Allow those clocks under a power domain to do the runtime pm operation by forwarding the struct device pointer from clock provider. Signed-off-by:
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Chunfeng Yun authored
Add pericfg clocks for MT8183, it's used when support USB remote wakeup Cc: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.comAcked-by:
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Chunfeng Yun authored
This patch adds binding of pericfg for MT8183. Signed-off-by:
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Stefan Wahren authored
The VPU firmware assume that the PLLD_PER isn't modified by the ARM core. Otherwise this could cause firmware lookups. So mark the clock as critical to avoid this. Signed-off-by:
Stefan Wahren <wahrenst@gmx.net> Reviewed-by:
Eric Anholt <eric@anholt.net>
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Stefan Wahren authored
The new BCM2711 supports an additional clock for the emmc2 block. So add a new compatible and register this clock only for BCM2711. Signed-off-by:
Matthias Brugger <mbrugger@suse.com> Acked-by:
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Stefan Wahren authored
In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we extend the description with a SoC support flag. This approach avoids long and mostly redundant lists of clock IDs. Since PLLH is specific to BCM2835, we register only rest of the clocks as common to all SoC. Suggested-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Stefan Wahren authored
The new BCM2711 supports an additional clock for the emmc2 block. So we need an additional compatible. Signed-off-by:
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- 16 Sep, 2019 2 commits
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Eugen Hristev authored
Selecting the right parent for the main clock is done using only main oscillator enabled bit. In case we have this oscillator bypassed by an external signal (no driving on the XOUT line), we still use external clock, but with BYPASS bit set. So, in this case we must select the same parent as before. Create a macro that will select the right parent considering both bits from the MOR register. Use this macro when looking for the right parent. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by:
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Eugen Hristev authored
The regmap update bits call was not selecting the proper mask, considering the bits which was updating. Update the mask from call to also include OSCBYPASS. Removed MOSCEN which was not updated. Fixes: 1bdf0232 ("clk: at91: make use of syscon/regmap internally") Signed-off-by:
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- 09 Sep, 2019 3 commits
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mtk01761 authored
Add MT6779 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by:
mtk01761 <wendell.lin@mediatek.com> Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.comSigned-off-by:
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mtk01761 authored
Add MT6779 clock dt-bindings, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by:
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mtk01761 authored
This patch adds the binding documentation for apmixedsys, audiosys, camsys, imgsys, ipesys, infracfg, mfgcfg, mmsys, topckgen, vdecsys, and vencsys for Mediatek MT6779. Signed-off-by:
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