1. 15 May, 2020 1 commit
  2. 14 May, 2020 20 commits
  3. 13 May, 2020 19 commits
    • DENG Qingfang's avatar
      net: dsa: mt7530: set CPU port to fallback mode · 38152ea3
      DENG Qingfang authored
      Currently, setting a bridge's self PVID to other value and deleting
      the default VID 1 renders untagged ports of that VLAN unable to talk to
      the CPU port:
      
      	bridge vlan add dev br0 vid 2 pvid untagged self
      	bridge vlan del dev br0 vid 1 self
      	bridge vlan add dev sw0p0 vid 2 pvid untagged
      	bridge vlan del dev sw0p0 vid 1
      	# br0 cannot send untagged frames out of sw0p0 anymore
      
      That is because the CPU port is set to security mode and its PVID is
      still 1, and untagged frames are dropped due to VLAN member violation.
      
      Set the CPU port to fallback mode so untagged frames can pass through.
      
      Fixes: 83163f7d ("net: dsa: mediatek: add VLAN support for MT7530")
      Signed-off-by: default avatarDENG Qingfang <dqfext@gmail.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      38152ea3
    • Daniel González Cabanelas's avatar
      net: mvneta: speed down the PHY, if WoL used, to save energy · 5e3768a4
      Daniel González Cabanelas authored
      Some PHYs connected to this ethernet hardware support the WoL feature.
      But when WoL is enabled and the machine is powered off, the PHY remains
      waiting for a magic packet at max speed (i.e. 1Gbps), which is a waste of
      energy.
      
      Slow down the PHY speed before stopping the ethernet if WoL is enabled,
      and save some energy while the machine is powered off or sleeping.
      
      Tested using an Armada 370 based board (LS421DE) equipped with a Marvell
      88E1518 PHY.
      Signed-off-by: default avatarDaniel González Cabanelas <dgcbueu@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5e3768a4
    • Colin Ian King's avatar
      sfc: fix dereference of table before it is null checked · 6545be82
      Colin Ian King authored
      Currently pointer table is being dereferenced on a null check of
      table->must_restore_filters before it is being null checked, leading
      to a potential null pointer dereference issue.  Fix this by null
      checking table before dereferencing it when checking for a null
      table->must_restore_filters.
      
      Addresses-Coverity: ("Dereference before null check")
      Fixes: e4fe938c ("sfc: move 'must restore' flags out of ef10-specific nic_data")
      Signed-off-by: default avatarColin Ian King <colin.king@canonical.com>
      Acked-by: default avatarEdward Cree <ecree@solarflare.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6545be82
    • Michael Walle's avatar
      net: phy: at803x: add cable diagnostics support · 6cb75767
      Michael Walle authored
      The AR8031/AR8033 and the AR8035 support cable diagnostics. Adding
      driver support is straightforward, so lets add it.
      
      The PHY just do one pair at a time, so we have to start the test four
      times. The cable_test_get_status() can block and therefore we can just
      busy poll the test completion and continue with the next pair until we
      are done.
      The time delta counter seems to run at 125MHz which just gives us a
      resolution of about 82.4cm per tick.
      
      100m cable, A/B/C/D open:
        Cable test started for device eth0.
        Cable test completed for device eth0.
        Pair: Pair A, result: Open Circuit
        Pair: Pair A, fault length: 107.94m
        Pair: Pair B, result: Open Circuit
        Pair: Pair B, fault length: 104.64m
        Pair: Pair C, result: Open Circuit
        Pair: Pair C, fault length: 105.47m
        Pair: Pair D, result: Open Circuit
        Pair: Pair D, fault length: 107.94m
      
      1m cable, A/B connected, C shorted, D open:
        Cable test started for device eth0.
        Cable test completed for device eth0.
        Pair: Pair A, result: OK
        Pair: Pair B, result: OK
        Pair: Pair C, result: Short within Pair
        Pair: Pair C, fault length: 0.82m
        Pair: Pair D, result: Open Circuit
        Pair: Pair D, fault length: 0.82m
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6cb75767
    • Christoph Hellwig's avatar
      ipv6: set msg_control_is_user in do_ipv6_getsockopt · 1b2f08df
      Christoph Hellwig authored
      While do_ipv6_getsockopt does not call the high-level recvmsg helper,
      the msghdr eventually ends up being passed to put_cmsg anyway, and thus
      needs msg_control_is_user set to the proper value.
      
      Fixes: 1f466e1f ("net: cleanly handle kernel vs user buffers for ->msg_control")
      Reported-by: default avatarEric Dumazet <eric.dumazet@gmail.com>
      Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      1b2f08df
    • David S. Miller's avatar
      Merge branch 'net-phy-broadcom-cable-tester-support' · 87f785e9
      David S. Miller authored
      Michael Walle says:
      
      ====================
      net: phy: broadcom: cable tester support
      
      Add cable tester support for the Broadcom PHYs. Support for it was
      developed on a BCM54140 Quad PHY which RDB register access.
      
      If there is a link partner the results are not as good as with an open
      cable. I guess we could retry if the measurement until all pairs had at
      least one valid result.
      
      changes since v1:
       - added Reviewed-by: tags
       - removed "div by 2" for cross shorts, just mention it in the commit
         message. The results are inconclusive if the tests are repeated. So
         just report the length as is for now.
       - fixed typo in commit message
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      87f785e9
    • Michael Walle's avatar
      net: phy: bcm54140: add cable diagnostics support · f956af3f
      Michael Walle authored
      Use the generic cable tester functions from bcm-phy-lib to add cable
      tester support.
      
      100m cable, A/B/C/D open:
        Cable test started for device eth0.
        Cable test completed for device eth0.
        Pair: Pair A, result: Open Circuit
        Pair: Pair B, result: Open Circuit
        Pair: Pair C, result: Open Circuit
        Pair: Pair D, result: Open Circuit
        Pair: Pair A, fault length: 106.60m
        Pair: Pair B, fault length: 103.32m
        Pair: Pair C, fault length: 104.96m
        Pair: Pair D, fault length: 106.60m
      
      1m cable, A/B connected, pair C shorted, D open:
        Cable test started for device eth0.
        Cable test completed for device eth0.
        Pair: Pair A, result: OK
        Pair: Pair B, result: OK
        Pair: Pair C, result: Short within Pair
        Pair: Pair D, result: Open Circuit
        Pair: Pair C, fault length: 0.82m
        Pair: Pair D, fault length: 1.64m
      
      1m cable, A/B connected, pair C shorted with D:
        Cable test started for device eth0.
        Cable test completed for device eth0.
        Pair: Pair A, result: OK
        Pair: Pair B, result: OK
        Pair: Pair C, result: Short to another pair
        Pair: Pair D, result: Short to another pair
        Pair: Pair C, fault length: 1.64m
        Pair: Pair D, fault length: 1.64m
      
      The granularity of the length measurement seems to be 82cm.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f956af3f
    • Michael Walle's avatar
      net: phy: broadcom: add cable test support · 11ecf8c5
      Michael Walle authored
      Most modern broadcom PHYs support ECD (enhanced cable diagnostics). Add
      support for it in the bcm-phy-lib so they can easily be used in the PHY
      driver.
      
      There are two access methods for ECD: legacy by expansion registers and
      via the new RDB registers which are exclusive. Provide functions in two
      variants where the PHY driver can choose from. To keep things simple for
      now, we just switch the register access to expansion registers in the
      RDB variant for now. On the flipside, we have to keep a bus lock to
      prevent any other non-legacy access on the PHY.
      
      The results of the intra-pair tests are inconclusive (at least for the
      BCM54140). Most of the times half the length is reported but sometimes
      the length is correct.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      11ecf8c5
    • Michael Walle's avatar
      net: phy: broadcom: add bcm_phy_modify_exp() · e184a907
      Michael Walle authored
      Add the convenience function to do a read-modify-write. This has the
      additional benefit of saving one write to the selection register.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e184a907
    • Michael Walle's avatar
      net: phy: broadcom: add exp register access methods without buslock · 7d7e7bce
      Michael Walle authored
      Add helper to read and write expansion registers without taking the mdio
      lock.
      
      Please note, that this changes the semantics of the read and write.
      Before there was no lock between selecting the expansion register and
      the actual read/write. This may lead to access failures if there are
      parallel accesses. Instead take the bus lock during the whole access
      cycle.
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7d7e7bce
    • Oleksij Rempel's avatar
      net: phy: tja11xx: add cable-test support · ea13d718
      Oleksij Rempel authored
      Add initial cable testing support.
      This PHY needs only 100usec for this test and it is recommended to run it
      before the link is up. For now, provide at least ethtool support, so it
      can be tested by more developers.
      
      This patch was tested with TJA1102 PHY with following results:
      - No cable, is detected as open
      - 1m cable, with no connected other end and detected as open
      - a 40m cable (out of spec, max lenght should be 15m) is detected as OK.
      
      Current patch do not provide polarity test support. This test would
      indicate not proper wire connection, where "+" wire of main phy is
      connected to the "-" wire of the link partner.
      Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ea13d718
    • Christoph Hellwig's avatar
      net: ignore sock_from_file errors in __scm_install_fd · 6e8a4f9d
      Christoph Hellwig authored
      The code had historically been ignoring these errors, and my recent
      refactoring changed that, which broke ssh in some setups.
      
      Fixes: 2618d530 ("net/scm: cleanup scm_detach_fds")
      Reported-by: default avatarIdo Schimmel <idosch@idosch.org>
      Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
      Tested-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Tested-by: default avatarIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6e8a4f9d
    • David S. Miller's avatar
      Merge branch 'dwmac-meson8b-Ethernet-RX-delay-configuration' · 4fda8601
      David S. Miller authored
      Martin Blumenstingl says:
      
      ====================
      dwmac-meson8b Ethernet RX delay configuration
      
      The Ethernet TX performance has been historically bad on Meson8b and
      Meson8m2 SoCs because high packet loss was seen. I found out that this
      was related (yet again) to the RGMII TX delay configuration.
      In the process of discussing the big picture (and not just a single
      patch) [0] with Andrew I discovered that the IP block behind the
      dwmac-meson8b driver actually seems to support the configuration of the
      RGMII RX delay (at least on the Meson8b SoC generation).
      
      Since I sent the first RFC I got additional documentation from Jianxin
      (many thanks!). Also I have discovered some more interesting details:
      - Meson8b Odroid-C1 requires an RX delay (by either the PHY or the MAC)
        Based on the vendor u-boot code (not upstream) I assume that it will
        be the same for all Meson8b and Meson8m2 boards
      - Khadas VIM2 seems to have the RX delay built into the PCB trace
        length. When I enable the RX delay on the PHY or MAC I can't get any
        data through. I expect that we will have the same situation on all
        GXBB, GXM, AXG, G12A, G12B and SM1 boards. Further clarification is
        needed here though (since I can't visually see these lengthened
        traces on the PCB). This will be done before sending patches for
        these boards.
      
      Dependencies for this series:
      There is a soft dependency for patch #2 on commit f2253143
      "dt-bindings: net: dwmac: increase 'maxItems' for 'clocks',
      'clock-names' properties" which is currently in Rob's -next tree.
      That commit is needed to make the dt-bindings schema validation
      pass for patch #2. That patch has been for ~4 weeks in Robs tree,
      so I assume that is not going to be dropped.
      
      Changes since RFC v2 at [2]:
      - dropped $ref: /schemas/types.yaml#definitions/uint32 from the
        "amlogic,rx-delay-ns" in patch #1 ("Don't need to define the
        type when in standard units." says Rob - thanks, I learned
        something new). Also use "default: 0" for for this property
        instead of explaining it in the description text.
      - added a note to the cover-letter about a hidden dependency for
        dt-binding schema validation in patch #2
      - Added Andrew's Reviewed-by to patches 1-7. Thank you again for
        the quick and detailed reviews, I appreciate this!
      - error out if the (optional) timing-adjustment clock is missing
        but we're asked to enable the RGMII RX delay. The MAC won't
        work in this specific case and either the RX delay has to be
        provided by the PHY or the timing-adjustment clock has to be
        added.
      - dropped the dts patches (#9-11) which were only added to give
        an overview how this is going to be used. those will be sent
        separately
      - dropped the RFC prefix
      
      Changes since RFC v1 at [1]:
      - add support for the timing adjustment clock input (dt-bindings and
        in the driver) thanks to the input from the unnamed Ethernet engineer
        at Amlogic. This is the missing link between the fclk_div2 clock and
        the Ethernet controller on Meson8b (no traffic would flow if that
        clock was disabled)
      - add support fot the amlogic,rx-delay-ns property. The only supported
        values so far are 0ns and 2ns. The registers seem to allow more
        precise timing adjustments, but I could not make that work so far.
      - add more register documentation (for the new RX delay bits) and
        unified the placement of existing register documentation. Again,
        thanks to Jianxin and the unnamed Ethernet engineer at Amlogic
      - DO NOT MERGE: .dts patches to show the conversion of the Meson8b
        and Meson8m2 boards to "rgmii-id". I didn't have time for all arm64
        patches yet, but these will switch to phy-mode = "rgmii-txid" with
        amlogic,rx-delay-ns = <0> (because the delay seems to be provided by
        the PCB trace length).
      
      [0] https://patchwork.kernel.org/patch/11309891/
      [1] https://patchwork.kernel.org/cover/11310719/
      [2] https://patchwork.kernel.org/cover/11518257/
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4fda8601
    • Martin Blumenstingl's avatar
      net: stmmac: dwmac-meson8b: add support for the RX delay configuration · 9308c476
      Martin Blumenstingl authored
      Configure the PRG_ETH0_ADJ_* bits to enable or disable the RX delay
      based on the various RGMII PHY modes. For now the only supported RX
      delay settings are:
      - disabled, use for example for phy-mode "rgmii-id"
      - 0ns - this is treated identical to "disabled", used for example on
        boards where the PHY provides 2ns TX delay and the PCB trace length
        already adds 2ns RX delay
      - 2ns - for whenever the PHY cannot add the RX delay and the traces on
        the PCB don't add any RX delay
      
      Disabling the RX delay (in case u-boot enables it, which is the case
      for example on Meson8b Odroid-C1) simply means that PRG_ETH0_ADJ_ENABLE,
      PRG_ETH0_ADJ_SETUP, PRG_ETH0_ADJ_DELAY and PRG_ETH0_ADJ_SKEW should be
      disabled (just disabling PRG_ETH0_ADJ_ENABLE may be enough, since that
      disables the whole re-timing logic - but I find it makes more sense to
      clear the other bits as well since they depend on that setting).
      
      u-boot on Odroid-C1 uses the following steps to enable a 2ns RX delay:
      - enabling enabling the timing adjustment clock
      - enabling the timing adjustment logic by setting PRG_ETH0_ADJ_ENABLE
      - setting the PRG_ETH0_ADJ_SETUP bit
      
      The documentation for the PRG_ETH0_ADJ_DELAY and PRG_ETH0_ADJ_SKEW
      registers indicates that we can even set different RX delays. However,
      I could not find out how this works exactly, so for now we only support
      a 2ns RX delay using the exact same way that Odroid-C1's u-boot does.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9308c476
    • Martin Blumenstingl's avatar
      net: stmmac: dwmac-meson8b: Make the clock enabling code re-usable · a54dc4a4
      Martin Blumenstingl authored
      The timing adjustment clock will need similar logic as the RGMII clock:
      It has to be enabled in the driver conditionally and when the driver is
      unloaded it should be disabled again. Extract the existing code for the
      RGMII clock into a new function so it can be re-used.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a54dc4a4
    • Martin Blumenstingl's avatar
      net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock · e4227bff
      Martin Blumenstingl authored
      The PRG_ETHERNET registers have a built-in timing adjustment circuit
      which can provide the RX delay in RGMII mode. This is driven by an
      external (to this IP, but internal to the SoC) clock input. Fetch this
      clock as optional (even though it's there on all supported SoCs) since
      we just learned about it and existing .dtbs don't specify it.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e4227bff
    • Martin Blumenstingl's avatar
      net: stmmac: dwmac-meson8b: Add the PRG_ETH0_ADJ_* bits · c92d1d23
      Martin Blumenstingl authored
      The PRG_ETH0_ADJ_* are used for applying the RGMII RX delay. The public
      datasheets only have very limited description for these registers, but
      Jianxin Pan provided more detailed documentation from an (unnamed)
      Amlogic engineer. Add the PRG_ETH0_ADJ_* bits along with the improved
      description.
      Suggested-by: default avatarJianxin Pan <jianxin.pan@amlogic.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c92d1d23
    • Martin Blumenstingl's avatar
      net: stmmac: dwmac-meson8b: Move the documentation for the TX delay · 889df203
      Martin Blumenstingl authored
      Move the documentation for the TX delay above the PRG_ETH0_TXDLY_MASK
      definition. Future commits will add more registers also with
      documentation above their register bit definitions. Move the existing
      comment so it will be consistent with the upcoming changes.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      889df203
    • Martin Blumenstingl's avatar
      net: stmmac: dwmac-meson8b: use FIELD_PREP instead of open-coding it · 3649abe4
      Martin Blumenstingl authored
      Use FIELD_PREP() to shift a value to the correct offset based on a
      bitmask instead of open-coding the logic.
      No functional changes.
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      3649abe4