1. 14 May, 2018 25 commits
  2. 03 May, 2018 1 commit
  3. 02 May, 2018 4 commits
  4. 23 Apr, 2018 5 commits
  5. 18 Apr, 2018 3 commits
    • Greg Ungerer's avatar
      ARM: dts: imx6ull: add UART5 input select register definitions · 9b483b88
      Greg Ungerer authored
      The iMX6ULL UART5_RX_DATA_SELECT_INPUT DAISY Register has some different
      bit definitions to that same register in the iMX6UL.
      
      The bits for the iMX6UL:
      
      000 CSI_DATA00_ALT8 — Selecting Pad: CSI_DATA00 for Mode: ALT8
      001 CSI_DATA01_ALT8 — Selecting Pad: CSI_DATA01 for Mode: ALT8
      010 GPIO1_IO04_ALT8 — Selecting Pad: GPIO1_IO04 for Mode: ALT8
      011 GPIO1_IO05_ALT8 — Selecting Pad: GPIO1_IO05 for Mode: ALT
      100 UART5_TX_DATA_ALT0 — Selecting Pad: UART5_TX_DATA for Mode: ALT
      101 UART5_RX_DATA_ALT0 — Selecting Pad: UART5_RX_DATA for Mode: ALT
      
      But for the iMX6ULL:
      
      000 CSI_DATA00_ALT8 — Selecting Pad: CSI_DATA00 for Mode: ALT8
      001 CSI_DATA01_ALT8 — Selecting Pad: CSI_DATA01 for Mode: ALT8
      010 GPIO1_IO04_ALT8 — Selecting Pad: GPIO1_IO04 for Mode: ALT8
      011 GPIO1_IO05_ALT8 — Selecting Pad: GPIO1_IO05 for Mode: ALT
      100 UART1_TX_DATA_ALT9 — Selecting Pad: UART1_TX_DATA for Mode: ALT9
      101 UART1_RX_DATA_ALT9 — Selecting Pad: UART1_RX_DATA for Mode: ALT9
      110 UART5_TX_DATA_ALT0 — Selecting Pad: UART5_TX_DATA for Mode: ALT0
      111 UART5_RX_DATA_ALT0 — Selecting Pad: UART5_RX_DATA for Mode: ALT0
      
      Specifically for a board I am working on with the serial console on UART5
      I need to be able to enable UART5_RX_DATA_ALT0 mode. There is no definition
      for the iMX6ULL version of that in imx6ul-pinfunc.h or imx6ull-pinfunc.h.
      
      Add definitions for the missing UART5 input select register bits of the
      iMX6ULL.
      Signed-off-by: default avatarGreg Ungerer <gerg@linux-m68k.org>
      Acked-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      9b483b88
    • Jagan Teki's avatar
      ARM: dts: imx6q: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support · 3fe08835
      Jagan Teki authored
      i.CoreM6 1.5 is an another i.CoreM6 QDL cpu modules which can be connected
      to EDIMM starter kit design with eMMC and MIPI-CSI interfaces suitable for
      Android and video capture application.
      
      notable features:
      CPU			NXP i.MX6 S/DL/D/Q, Up to 4 x Cortex-A9@800MHz
      Memory  		Up to 2 GB DDR3-1066
      Video Interfaces	Up to 1 Parallel Up to 2 LVDS HDMI 1.4
      			port 8 bit CSI INPUT MIPI-CSI INPUT
      1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc
      Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      3fe08835
    • Jagan Teki's avatar
      ARM: dts: imx6q-icore-ofcap12: Switch LVDS timings from panel-simple · 38107179
      Jagan Teki authored
      Switch to use koe_tx31d200vm0baa LVDS timings from
      panel-simple instead hard coding the same in dts.
      Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      38107179
  6. 16 Apr, 2018 2 commits