- 22 Jan, 2018 4 commits
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James Hogan authored
Now that we are using assembler macros to implement VZ instructions on toolchains which don't support them, pass VZ guest Cop0 register names to the __{read,write}_{32bit,ulong,64bit}_gc0_register macros in $n format rather than register numbers. This is to make them consistent with the normal root Cop0 register access macros which they were originally based on. Signed-off-by:James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17773/
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James Hogan authored
Update VZ guest register & guest TLB access helpers to use the new assembly macros for parsing register names and creating custom assembly macro instructions, which has a number of advantages: - Better code can be generated on toolchains which don't support VZ, more closely matching those which do, since there is no need to bounce values via the $at register. Some differences still remain due to the inability to safely fill branch delay slots and R6 compact branch forbidden slots with explicitly encoded instructions, resulting in some extra NOPs added by the assembler. - Some code duplication between toolchains which do and don't support VZ instructions is removed, since the helpers are only implemented once. When the toolchain doesn't implement the instruction an assembly macro implements it instead. - Instruction encodings are kept together in the source. On a generic kernel with KVM VZ support enabled this change saves about 2.5KiB of kernel code when TOOLCHAIN_SUPPORTS_VIRT=n, bringing it down to about 0.5KiB more than when TOOLCHAIN_SUPPORTS_VIRT=y on r6, and just 68 bytes more on r2. Signed-off-by:
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James Hogan authored
Implement a parse_r assembler macro in asm/mipsregs.h to parse a register in $n form, and a few C macros for defining assembler macro instructions. These can be used to more transparently support older binutils versions which don't support for example the msa, virt, xpa, or crc instructions. In particular they overcome the difficulty of turning a register name in $n form into an instruction encoding suitable for giving to .word / .hword, which is particularly problematic when needed from inline assembly where the compiler is responsible for register allocation. Traditionally this had required the use of $at and an extra MOV instruction, but for CRC instructions with multiple GP register operands that approach becomes more difficult. Three assembler macro creation helpers are added: - _ASM_MACRO_0(OP, ENC) This is to define an assembler macro for an instruction which has no operands, for example the VZ TLBGR instruction. - _ASM_MACRO_2R(OP, R1, R2, ENC) This is to define an assembler macro for an instruction which has 2 register operands, for example the CFCMSA instruction. - _ASM_MACRO_3R(OP, R1, R2, R3, ENC) This is to define an assembler macro for an instruction which has 3 register operands, for example the crc32 instructions. - _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) This is to define an assembler macro for a Cop0 move instruction, with 2 register operands and an optional register select operand which defaults to 0, for example the VZ MFGC0 instruction. Suggested-by:
Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
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Miodrag Dinic authored
Provide amendments to the MIPS generic platform framework so that the new generic-based board Ranchu can be chosen to be built. The Ranchu board is intended to be used by Android emulator. The name "Ranchu" originates from Android development community. "Goldfish" and "Ranchu" are terms used for two generations of virtual boards used by Android emulator. The name "Ranchu" is a newer one among the two, and this patch deals with Ranchu. However, for historical reasons, some devices/drivers still contain the name "Goldfish". MIPS Ranchu machine includes a number of Goldfish devices. The support for Virtio devices is also included. Ranchu board supports up to 16 Virtio devices which can be attached using Virtio MMIO Bus. This is summarized in the following picture: ABUS ||----MIPS CPU || | IRQs ||----Goldfish PIC------------(32)-------- || | | | | | | | | | ||----Goldfish TTY------ | | | | | | | | || | | | | | | | | ||----Goldfish RTC-------- | | | | | | | || | | | | | | | ||----Goldfish FB----------- | | | | | | || | | | | | | ||----Goldfish Events--------- | | | | | || | | | | | ||----Goldfish Audio------------ | | | | || | | | | ||----Goldfish Battery------------ | | | || | | | ||----Android PIPE------------------ | | || | | ||----Virtio MMIO Bus | | || | | | | | || | | (virtio-block)--------- | || (16) | | || | (virtio-net)------------------ Device Tree is created on the QEMU side based on the information about devices IO map and IRQ numbers. Kernel will load this DTB using UHI boot protocol DTB handover mode. Signed-off-by:Miodrag Dinic <miodrag.dinic@mips.com> Signed-off-by:
Goran Ferenc <goran.ferenc@mips.com> Signed-off-by:
Aleksandar Markovic <aleksandar.markovic@mips.com> Reviewed-by:
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- 18 Jan, 2018 20 commits
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Mathieu Malaterre authored
For reference: * https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation Fix non-fatal warning: arch/mips/kernel/branch.c:418: warning: Excess function parameter 'returns' description in '__compute_return_epc_for_insn' Signed-off-by:
Mathieu Malaterre <malat@debian.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Maciej W. Rozycki <macro@mips.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18031/ [jhogan@kernel.org: Expand subject slightly] Signed-off-by:
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Jiaxun Yang authored
The 32-bit support was broken at runtime, it doesn't boot anymore, witch is hard to debug because even early printk isn't working, also there are some build warnings. Some newer bootloader may not support 32-bit ELF. So we decide to drop 32-bit support. Make loongson64 a pure 64-bit arch. Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18174/Signed-off-by:
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Paul Cercueil authored
The GCW Zero (http://www.gcw-zero.com) is a retro-gaming focused handheld game console, successfully kickstarted in ~2012, running Linux. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Acked-by:
Philippe Ombredanne <pombredanne@nexb.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18490/Signed-off-by:
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Paul Cercueil authored
Game Consoles Worldwide, mostly known under the acronym GCW, is the creator of the GCW Zero open-source video game system. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18489/Signed-off-by:
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Maarten ter Huurne authored
According to config2, the associativity would be 5-ways, but the documentation states 4-ways, which also matches the documented L2 cache size of 256 kB. Signed-off-by:
Maarten ter Huurne <maarten@treewalker.org> Reviewed-by:
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Paul Cercueil authored
Provide just enough bits (clocks, clocksource, uart) to allow a kernel to boot on the JZ4770 SoC to a initramfs userspace. Signed-off-by:
PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Reviewed-by:
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Paul Cercueil authored
Previously, the mips_machtype variable was always initialized to MACH_INGENIC_JZ4740 even if running on different SoCs. Signed-off-by:
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Paul Cercueil authored
Add a machtype ID for the JZ4780 SoC, which was missing, and one for the newly supported JZ4770 SoC. Signed-off-by:
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Paul Burton authored
jz4740_init_cmdline appends all arguments from argv (in fw_arg1) to arcs_cmdline, up to argc (in fw_arg0). The common code in fw_init_cmdline will do the exact same thing when run on a system where fw_arg0 isn't a pointer to kseg0 (it'll also set _fw_envp but we don't use it). Remove the custom implementation & use the generic code. Signed-off-by:
Paul Burton <paul.burton@mips.com> Reviewed-by:
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Paul Burton authored
Platforms using DT will typically call __dt_setup_arch from plat_mem_setup. This in turn calls early_init_dt_scan. When CONFIG_CMDLINE is set, this leads to its value being copied into boot_command_line by early_init_dt_scan_chosen. If this happens before the code setting up boot_command_line in arch_mem_init runs, that code will go on to append CONFIG_CMDLINE (via builtin_cmdline) to boot_command_line again, duplicating it. For some command line parameters (eg. earlycon) this can be a problem. Set up boot_command_line before early_init_dt_scan_chosen gets called such that it will not write CONFIG_CMDLINE in this scenario & the arguments aren't duplicated. Signed-off-by:
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Paul Cercueil authored
Add support for the clocks provided by the CGU in the Ingenic JZ4770 SoC. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18482/Signed-off-by:
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Paul Cercueil authored
This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4770-cgu driver. Signed-off-by:
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Paul Cercueil authored
This commit permits the PLLs to be dynamically enabled and disabled when their children clocks are enabled and disabled. Signed-off-by:
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Paul Cercueil authored
The second PLL of the JZ4770 does not have a bypass bit. This commit makes it possible to support it with the current common CGU code. Signed-off-by:
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Paul Cercueil authored
Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by:
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Paul Cercueil authored
The CGU common code does not modify the pointed clk_ops structure, so it should be marked as const. Signed-off-by:
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Mathieu Malaterre authored
Replace pointer comparison to 0 with NULL in prepare_ftrace_return to improve code readability. Identified with coccinelle script 'badzero.cocci'. Signed-off-by:
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Corentin Labbe authored
MIPS_GENERIC selects some options conditional on BIG_ENDIAN which does not exist. Replace BIG_ENDIAN with CPU_BIG_ENDIAN which is the correct kconfig name. Note that BMIPS_GENERIC does the same which confirms that this patch is needed. Fixes: eed0eabd ("MIPS: generic: Introduce generic DT-based board support") Signed-off-by:
Corentin Labbe <clabbe.montjoie@gmail.com> Reviewed-by:
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James Hogan authored
Make doesn't expand shell style "vmlinuz.{32,ecoff,bin,srec}" to the 4 separate files, so none of these files get cleaned up by make clean. List the files separately instead. Fixes: ec335292 ("MIPS: Remove all generated vmlinuz* files on "make clean"") Signed-off-by: -
Daniel Sabogal authored
vmlinuz is not built by default for platforms using COMPRESSION_FNAME (e.g. Malta) due to an erroneous check on ZBOOT Signed-off-by:
Daniel Sabogal <dsabogalcc@gmail.com> Reviewed-by:
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- 09 Jan, 2018 5 commits
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Felix Fietkau authored
dma_mapping_error() already checks if ops->mapping_error is a null pointer Signed-off-by:
Felix Fietkau <nbd@nbd.name> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17881/Signed-off-by:
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James Hogan authored
Make read_c0_prid() use the new constant accessor macros so that it can potentially be optimised or removed by the compiler. This is particularly important under virtualisation, where even with hardware assisted virtualisation (VZ), access to the PRid register may need to be emulated by the hypervisor. In particular this helps eliminate the read of the PRid register in the rather frequently called add_interrupt_randomness() (which calls into arch/mips/include/asm/timex.h) when the prid is unused but the read can't be removed due to the inline asm being marked __volatile__. Reported-by:
Yann LeDu <Yann.LeDu@imgtec.com> Signed-off-by:
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James Hogan authored
Some Cop0 registers are constant and have no side effects when read. There is no need for the inline asm to read these to be marked __volatile__, and doing so prevents them from being removed by the compiler. Add a few new accessor macros to handle these registers more efficiently (especially for the sake of running in a guest where redundant access to the register may trap to the hypervisor): __read_const_32bit_c0_register() __read_const_64bit_c0_register() __read_const_ulong_c0_register() Signed-off-by:
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Huacai Chen authored
Add Jiaxun Yang as the MIPS/Loongson-2 maintainer and add Huacai Chen as the MIPS/Loongson-3 maintainer. [ralf@linux-mips.org: Don't put all of drivers/platform/mips/ into these two entries but rather only the files required even though at this time the Loongson platforms are the only users of drivers/platform/mips/.] Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
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Ralf Baechle authored
Add drivers/platform/mips to the MIPS architecture MAINTAINERS entry. Signed-off-by:
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- 12 Dec, 2017 6 commits
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Aleksandar Markovic authored
Mark intentional fall throughs in switch statements with a consistent comment. In most of the cases, a new comment line containing text "fall through" is inserted. In some of the cases, existing comment contained a variation of the text "fall through" (for example, "FALL THROUGH" or "drop through"). In such cases, the existing comment is modified to contain "fall through". Lastly, in two cases, code segments were described in comments as "fall througs", but were in reality "breaks out" of switch statement. In such cases, existing comments are accordingly modified. Apart from making code easier to follow and debug, this change enables some static code analysers to interpret newly inserted comments as their annotations (and, therefore, not issue warnings of type "fall through in switch statement", which is desireable, since marked fallthroughs are intentional). Signed-off-by:
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Aleksandar Markovic authored
Replace several instances of multiple assignment with individual assignments. Signed-off-by:
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Aleksandar Markovic authored
Move invocation of fpu_emu() to be out of if statement condition. This makes code easier to follow and debug, and fixes a checkpatch warning. Signed-off-by:
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Aleksandar Markovic authored
Declare function srl128() as static, since it it used just locally to the source file. This also removes a sparse warning for corresponding file. Signed-off-by:
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Aleksandar Markovic authored
Avoid duplicate definition of macro DPXMULT(). Move its definition to a header. Signed-off-by:
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Aleksandar Markovic authored
Remove an unnecessary header inclusion of "ieee754dp.h". Signed-off-by:
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- 11 Dec, 2017 1 commit
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Linus Torvalds authored
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- 10 Dec, 2017 4 commits
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Jeff Layton authored
HPFS does not set SB_I_VERSION and does not use the i_version counter internally. Signed-off-by:
Jeff Layton <jlayton@redhat.com> Signed-off-by:
Mikulas Patocka <mikulas@twibright.com> Reviewed-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Jiri Slaby authored
sign_extend32 counts the sign bit parameter from 0, not from 1. So we have to use "11" for 12th bit, not "12". This mistake means we have not allowed negative op and cmp args since commit 30d6e0a4 ("futex: Remove duplicated code and fix undefined behaviour") till now. Fixes: 30d6e0a4 ("futex: Remove duplicated code and fix undefined behaviour") Signed-off-by:
Jiri Slaby <jslaby@suse.cz> Cc: Ingo Molnar <mingo@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Darren Hart <dvhart@infradead.org> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linuxLinus Torvalds authored
Pull btrfs fixes from David Sterba: "This contains a few fixes (error handling, quota leak, FUA vs nobarrier mount option). There's one one worth mentioning separately - an off-by-one fix that leads to overwriting first byte of an adjacent page with 0, out of bounds of the memory allocated by an ioctl. This is under a privileged part of the ioctl, can be triggerd in some subvolume layouts" * tag 'for-4.15-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux: btrfs: Fix possible off-by-one in btrfs_search_path_in_tree Btrfs: disable FUA if mounted with nobarrier btrfs: fix missing error return in btrfs_drop_snapshot btrfs: handle errors while updating refcounts in update_ref_for_cow btrfs: Fix quota reservation leak on preallocated files
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds authored
Pull ARM SoC fixes from Olof Johansson: - A revert of all SCPI changes from the 4.15 merge window. They had regressions on the Amlogic platforms, and the submaintainer isn't around to fix these bugs due to vacation, etc. So we agreed to revert and revisit in next release cycle. - A series fixing a number of bugs for ARM CCN interconnect, around module unload, smp_processor_id() in preemptable context, and fixing some memory allocation failure checks. - A handful of devicetree fixes for different platforms, fixing warnings and errors that were previously ignored by the compiler. - The usual set of mostly minor fixes for different platforms. * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) ARM64: dts: meson-gx: fix UART pclk clock name ARM: omap2: hide omap3_save_secure_ram on non-OMAP3 builds arm: dts: nspire: Add missing #phy-cells to usb-nop-xceiv ARM: dts: Fix dm814x missing phy-cells property ARM: dts: Fix elm interrupt compiler warning bus: arm-ccn: fix module unloading Error: Removing state 147 which has instances left. bus: arm-cci: Fix use of smp_processor_id() in preemptible context bus: arm-ccn: Fix use of smp_processor_id() in preemptible context bus: arm-ccn: Simplify code bus: arm-ccn: Check memory allocation failure bus: arm-ccn: constify attribute_group structures. firmware: arm_scpi: Revert updates made during v4.15 merge window arm: dts: marvell: Add missing #phy-cells to usb-nop-xceiv arm64: dts: sort vendor subdirectories in Makefile alphabetically meson-gx-socinfo: Fix package id parsing ARM: meson: fix spelling mistake: "Couln't" -> "Couldn't" ARM: dts: meson: fix the memory region of the GPIO interrupt controller ARM: dts: meson: correct the sort order for the the gpio_intc node MAINTAINERS: exclude other Socionext SoC DT files from ARM/UNIPHIER entry arm64: dts: uniphier: remove unnecessary interrupt-parent ...
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