- 06 Nov, 2019 2 commits
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Olof Johansson authored
Merge tag 'sunxi-fixes-for-5.4-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt One patch to add back the PMU node that was removed because the interrupts were improper in a previous fixes PR. * tag 'sunxi-fixes-for-5.4-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: a64: Re-add PMU node ARM: sunxi: Fix CPU powerdown on A83T ARM: dts: sun8i-a83t-tbs-a711: Fix WiFi resume from suspend ARM: dts: sun7i: Drop the module clock from the device tree dt-bindings: media: sun4i-csi: Drop the module clock media: dt-bindings: Fix building error for dt_binding_check arm64: dts: allwinner: a64: sopine-baseboard: Add PHY regulator delay arm64: dts: allwinner: a64: Drop PMU node arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay Link: https://lore.kernel.org/r/45023fa6-b2bc-4934-b85c-3e7841dde0b1.lettre@localhostSigned-off-by:
Olof Johansson <olof@lixom.net>
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Andre Przywara authored
As it was found recently, the Performance Monitoring Unit (PMU) on the Allwinner A64 SoC was not generating (the right) interrupts. With the SPI numbers from the manual the kernel did not receive any overflow interrupts, so perf was not happy at all. It turns out that the numbers were just off by 4, so the PMU interrupts are from 148 to 151, not from 152 to 155 as the manual describes. This was found by playing around with U-Boot, which typically does not use interrupts, so the GIC is fully available for experimentation: With *every* PPI and SPI enabled, an overflowing PMU cycle counter was found to set a bit in one of the GICD_ISPENDR registers, with careful counting this was determined to be number 148. Tested with perf record and perf top on a Pine64-LTS. Also tested with tasksetting to every core to confirm the assignment between IRQs and cores. This somewhat "revert-fixes" commit ed3e9406 ("arm64: dts: allwinner: a64: Drop PMU node"). Fixes: 34a97fcc ("arm64: dts: allwinner: a64: Add PMU node") Fixes: ed3e9406 ("arm64: dts: allwinner: a64: Drop PMU node") Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
Maxime Ripard <maxime@cerno.tech>
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- 04 Nov, 2019 20 commits
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git://git.infradead.org/linux-mvebuOlof Johansson authored
mvebu dt64 for 5.5 (part 1) - Add new Marvell CN9130 SoC support (CN9130 is made of one AP807 and one internal CP115, similar to the Armada 7K/8K using AP806 and CP110). - Reorganize EspressoBin device tree to add new variant of the boards (Armada 3270 based) - Add firmware node for turris Mox (Armada 3720 based) * tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu: (23 commits) arm64: dts: armada-3720-turris-mox: add firmware node arm64: dts: marvell: add ESPRESSObin variants arm64: dts: marvell: Add support for Marvell CN9132-DB arm64: dts: marvell: Add support for Marvell CN9131-DB arm64: dts: marvell: Add support for Marvell CN9130-DB arm64: dts: marvell: Add support for Marvell CN9130 SoC support arm64: dts: marvell: Add support for CP115 arm64: dts: marvell: Externalize PCIe macros from CP11x file arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file arm64: dts: marvell: Prepare the introduction of CP115 arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment arm64: dts: marvell: Add AP807-quad cache description arm64: dts: marvell: Add AP806-quad cache description arm64: dts: marvell: Add AP806-dual cache description arm64: dts: marvell: Add support for AP807/AP807-quad dt-bindings: marvell: Declare the CN913x SoC compatibles dt-bindings: marvell: Convert the SoC compatibles description to YAML arm64: dts: marvell: Move clocks to AP806 specific file arm64: dts: marvell: Prepare the introduction of AP807 based SoCs MAINTAINERS: Add new Marvell CN9130-based files to track ... Link: https://lore.kernel.org/r/87zhhc3bo6.fsf@FE-laptopSigned-off-by:
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git://git.infradead.org/linux-mvebuOlof Johansson authored
mvebu dt for 5.5 (part 1) - Enable L2 cache parity and ECC on a Armada XP SoC family and allow to use in on the Armada 38x SoCs too. - Use correct name for the rs5c372a on synology (Kirkwood based) - Rename "sa-sram" node to "sram" on dove * tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu: ARM: dts: armada-xp: add label to sdram-controller node ARM: dts: mvebu: add sdram controller node to Armada-38x ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg ARM: dts: dove: Rename "sa-sram" node to "sram" ARM: dts: kirkwood: synology: Fix rs5c372 RTC entry Link: https://lore.kernel.org/r/8736f44q9l.fsf@FE-laptopSigned-off-by:
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Olof Johansson authored
Merge tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.5-rc1 Adds support for DP and XUSB on various boards, enables SMMU support for more devices and fixes a couple of DTC warnings and inconsistencies that are reported at runtime. These changes along with some of the driver changes in other branches allow suspend/resume support on Tegra210 devices (e.g. Jetson TX1 and Jetson Nano). * tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits) arm64: tegra: Add Jetson Nano SC7 timings arm64: tegra: Add Jetson TX1 SC7 timings arm64: tegra: Enable wake from deep sleep on RTC alarm arm64: tegra: Add PMU on Tegra210 arm64: tegra: Add blank lines for better readability arm64: tegra: Enable DisplayPort on Jetson AGX Xavier arm64: tegra: p2888: Rename regulators for consistency arm64: tegra: Enable DP support on Jetson TX2 arm64: tegra: Fix compatible for SOR1 arm64: tegra: Enable DP support on Jetson Nano arm64: tegra: Add SOR0_OUT clock on Tegra210 arm64: tegra: Assume no CLKREQ presence by default arm64: tegra: Enable SMMU for VIC on Tegra186 arm64: tegra: Enable XUSB host controller on Jetson TX2 arm64: tegra: Enable SMMU for XUSB host on Tegra186 arm64: tegra: Enable XUSB pad controller on Jetson TX2 arm64: tegra: Add ethernet alias on Jetson AGX Xavier arm64: tegra: Fix compatible string for EQOS on Tegra194 arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM arm64: tegra: Fix base address for SOR1 on Tegra194 ... Link: https://lore.kernel.org/r/20191102144521.3863321-8-thierry.reding@gmail.comSigned-off-by:
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Olof Johansson authored
Merge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.5-rc1 Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the STMPE ADC found on Toradex T30 modules as well as fixes for eDP support on Venice2. * tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: cardhu-a04: Add CPU Operating Performance Points ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS ARM: tegra: trimslice: Add CPU Operating Performance Points ARM: tegra: paz00: Add CPU Operating Performance Points ARM: tegra: paz00: Set up voltage regulators for DVFS ARM: tegra: Add CPU Operating Performance Points for Tegra30 ARM: tegra: Add CPU Operating Performance Points for Tegra20 ARM: tegra: Add Tegra30 CPU clock ARM: tegra: Add Tegra20 CPU clock ARM: tegra: Add External Memory Controller node on Tegra30 ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6 ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30 ARM: tegra: Add eDP power supplies on Venice2 ARM: tegra: Add SOR0_OUT clock on Tegra124 ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.comSigned-off-by:
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Olof Johansson authored
Merge tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.5-rc1 This contains various updates to device tree bindings and includes that are related to driver changes in other Tegra branches. * tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller dt-bindings: memory: tegra30: Convert to Tegra124 YAML dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT Link: https://lore.kernel.org/r/20191102144521.3863321-1-thierry.reding@gmail.comSigned-off-by:
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Olof Johansson authored
Merge tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual bunch of DT patches, with this time mostly: - Mali GPU support for the H6 - Two new crypto drivers enablement - A few fixes to our DTs, fixed through the validation effort - New boards: NanoPi Duo2 * tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits) dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2 ARM: dts: sun8i: add FriendlyARM NanoPi Duo2 arm64: allwinner: h6: Enable GPU node for Tanix TX6 arm64: dts: allwinner: bluetooth for Emlid Neutis N5 ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins ARM: dts: sun9i: a80: Add Security System node ARM: dts: sun8i: a83t: Add Security System node arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6 arm64: dts: allwinner: sun50i: Add crypto engine node on H5 arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64 ARM: dts: sun8i: H3: Add Crypto Engine node ARM: dts: sun8i: R40: add crypto engine node dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine arm64: dts: allwinner: Add mali GPU supply for H6 boards arm64: dts: allwinner: Add ARM Mali GPU node for H6 ARM: dts: sun8i: a83t: a711: Add touchscreen node ARM: dts: sun5i: olinuxino micro: Fix AT24 node name ARM: dts: sun9i: Add missing watchdog clocks arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3 arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth ... Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhostSigned-off-by:
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Geert Uytterhoeven authored
"debounce_interval" was never supported. Link: https://lore.kernel.org/r/20191101160356.32034-3-geert+renesas@glider.beSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: Barry Song <baohua@kernel.org> Signed-off-by:
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Geert Uytterhoeven authored
The standard DT property is called "#interrupt-cells". Link: https://lore.kernel.org/r/20191101160356.32034-2-geert+renesas@glider.beSigned-off-by:
Chanho Min <chanho.min@lge.com> Signed-off-by:
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Geert Uytterhoeven authored
The standard DT property is called "#interrupt-cells". Link: https://lore.kernel.org/r/20191101160356.32034-1-geert+renesas@glider.beSigned-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Olof Johansson authored
Merge tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas DT binding updates for v5.5 (take two) - JSON schema conversion, - Core support for the new R-Car M3-W+ (r8a77961) SoC, - Board compatible updates. * tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: power: rcar-sysc: Document r8a77961 support dt-bindings: reset: rcar-rst: Document r8a77961 support dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+ dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema Link: https://lore.kernel.org/r/20191101155842.31467-7-geert+renesas@glider.beSigned-off-by:
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Olof Johansson authored
Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM64 DT updates for v5.5 (take two) - Video-Input and Serial-ATA support on RZ/G2N, - Color Management Module support on various R-Car Gen3 SoCs, - Initial support for the R-Car M3-W+ (r8a77961) SoC on the Salvator-XS board. * tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+ arm64: dts: renesas: Add Renesas R8A77961 SoC support arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960 dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions arm64: dts: renesas: r8a774b1: Add SATA controller node arm64: dts: renesas: rcar-gen3: Add CMM units arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.beSigned-off-by:
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Olof Johansson authored
Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt PRM reset control dts changes for v5.5 merge window This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. * tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap5: Add PRM data ARM: dts: am43xx: Add PRM data ARM: dts: am33xx: Add PRM data ARM: dts: omap4: add PRM nodes ARM: dts: dra7: add PRM nodes soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.comSigned-off-by:
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Lubomir Rintel authored
Make sure UART3, where the console is, is called ttyS2. That is consistent with the early console. Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.skSigned-off-by:
Lubomir Rintel <lkundrak@v3.sk> Signed-off-by:
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Lubomir Rintel authored
Ponted out by DTC: <stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.skSigned-off-by:
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Lubomir Rintel authored
There's a typo there that rightfully upsets DTS: <stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus unit address format error, expected "e0000620" Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.skSigned-off-by:
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Lubomir Rintel authored
It should have one and DTC is indeed unhappy about its absence: <stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or ranges property, but no unit name Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.skSigned-off-by:
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Manivannan Sadhasivam authored
Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers in this SoC with maximum of 32 gpios. Except GPIOC, all controllers are capable of generating edge/level interrupts from first 8 lines. Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.orgSigned-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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git://github.com/hisilicon/linux-hisiOlof Johansson authored
ARM64: DT: Hisilicon SoCs DT updates for 5.5 - add Mali450 MP4 GPU node in the hi6220 SoC * tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.comSigned-off-by:
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Olof Johansson authored
Merge tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt Realtek ARM64 based SoC DT for v5.5 Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs. Add reset controllers for RTD129x and start using them for UARTs. * tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: arm64: dts: realtek: Add RTD129x UART resets arm64: dts: realtek: Add RTD129x reset controller nodes dt-bindings: reset: Add Realtek RTD1295 arm64: dts: realtek: Add watchdog node for RTD129x arm64: dts: realtek: Add oscillator for RTD129x arm64: dts: realtek: Add RTD1296 and Synology DS418 dt-bindings: arm: realtek: Document RTD1296 and Synology DS418 arm64: dts: realtek: Add RTD1293 and Synology DS418j arm64: dts: realtek: Change dual-license from MIT to BSD dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j dt-bindings: arm: realtek: Tidy up conversion to json-schema Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.deSigned-off-by:
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Olof Johansson authored
Merge branch 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/dt * 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: ARM: configs: keystone: enable cpts ARM: dts: k2l-netcp: add cpts refclk_mux node ARM: dts: k2hk-netcp: add cpts refclk_mux node ARM: dts: k2e-netcp: add cpts refclk_mux node ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b ARM: dts: keystone-clocks: add input fixed clocks Link: https://lore.kernel.org/r/1572372856-20598-2-git-send-email-santosh.shilimkar@oracle.comSigned-off-by:
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- 02 Nov, 2019 4 commits
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Olof Johansson authored
Merge tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.5 - Arria10 - modify QSPI read-delay property - Agilex - Add QSPI support - Enable USB and LEDs - Add service layer, fpga manager support - Stratix10 - Update QSPI reg address * tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: add service layer, fpga manager and fpga region arm64: agilex: enable USB and LEDs on agilex devkit arm64: dts: altera: update QSPI reg addresses for Stratix10 arm64: dts: agilex: add QSPI support for Intel Agilex ARM: dts: arria10: Modify QSPI read_delay for Arria10 Link: https://lore.kernel.org/r/20191029143737.24850-1-dinguyen@kernel.orgSigned-off-by:
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Karl Palsson authored
Adds bindings for the newly added NanoPi Duo2 board. Signed-off-by:
Karl Palsson <karlp@tweak.net.au> Signed-off-by:
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Karl Palsson authored
This is an Allwinner H3 based board, with 512MB ram, a USB OTG port, microsd slot, an onboard AP6212A wifi/bluetooth module, and a CSI connector. Full details and schematic available from vendor: http://wiki.friendlyarm.com/wiki/index.php/NanoPi_Duo2Signed-off-by:
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Clément Péron authored
Unlike other H6 boards, Tanix TX6 doesn't have a PMIC so we can enable the GPU without providing a specific power supply. Signed-off-by:
Clément Péron <peron.clem@gmail.com> Signed-off-by:
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- 01 Nov, 2019 14 commits
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Geert Uytterhoeven authored
Add initial support for the Renesas Salvator-X 2nd version development board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM. The memory map is as follows: - Bank0: 4GiB RAM : 0x000048000000 -> 0x000bfffffff 0x000480000000 -> 0x004ffffffff - Bank1: 4GiB RAM : 0x000600000000 -> 0x006ffffffff Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by:
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Geert Uytterhoeven authored
Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC. This includes: - Cortex-A57 and Cortex-A53 CPU cores (incl. L2 caches and power state definitions), - Power Management Unit, - PSCI firmware, - Pin Function Controller, - Clock, Reset, System, and Interrupt Controllers, - SCIF2 serial console, - Product Register, - ARM Architectured Timer, and various placeholders to allow to use salvator-xs.dtsi. Based on r8a7796.dtsi. Signed-off-by: -
Geert Uytterhoeven authored
CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961. Relax dependencies by handling both symbols. Signed-off-by:
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Geert Uytterhoeven authored
Renesas R-Car M3-W+ DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car M3-W+ (R8A77961) SoC, shared by driver and DT source files.
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Geert Uytterhoeven authored
Add DT binding documentation for the System Controller in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by:
Eugeniu Rosca <erosca@de.adit-jv.com> Acked-by:
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Geert Uytterhoeven authored
Add DT binding documentation for the Reset block in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
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Geert Uytterhoeven authored
Add device tree binding documentation for the Renesas Salvator-XS board equipped with an R-Car M3-W+ (R8A77961) SoC. Signed-off-by:
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Geert Uytterhoeven authored
Add device tree binding documentation for the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by:
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Geert Uytterhoeven authored
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to preserve compatibility with the definitions for R-Car M3-W (R8A77960). Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2) are not included, as they are used as internal clock sources only, and never referenced from DT. Signed-off-by: -
Geert Uytterhoeven authored
Add power domain indices for the R-Car M3-W+ (R8A77961) SoC. Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s Manual (Jul. 31, 2019). Signed-off-by:
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Georgii Staroselskii authored
The Emlid Neutis N5 board has AP6212 BT+WiFi chip. This patch is in line with 8558c6e2 ("ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board") and other commits that add Bluetooth support for similar boards. Signed-off-by:
Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by:
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Karl Palsson authored
uart1 and uart3 had existing pin definitions for the rts/cts pairs. Add definitions for uart2 as well. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Corentin Labbe authored
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A80 SoC Device-tree. Signed-off-by:
Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by:
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Corentin Labbe authored
The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A83T SoC Device-tree. Signed-off-by:
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