Merge tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Merge "Rockchip dts64 updates for v4.7 - part2" from Heiko Stübner:

Adding the new rk3399 core devicetree support as well as a board
dts for the evaluation board of this chip and similar to the arm32
side also move the rk3368 thermal data into the core soc dtsi, as
there really is no need to keep it separate.

* tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  dt-bindings: document rockchip rk3399-evb board
  arm64: dts: rockchip: add dts file for RK3399 evaluation board
  arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
  dt-bindings: rockchip-dw-mshc: add description for rk3399
  clk: rockchip: export some necessary rk3399 clock ids
  clk: rockchip: rename rga clock-id on rk3399
  clk: rockchip: add general gpu soft-reset on rk3399
  arm64: dts: rockchip: move the rk3368 thermal data into rk3368.dtsi
  clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
  clk: rockchip: add dt-binding header for rk3399

This merges fixes from linux-4.6 into the next/dt64 tree to avoid
a later merge conflict.

* renesas/fixes-2:
  arm64: dts: r8a7795: Don't disable referenced optional scif clock
  ARM: shmobile: timer: Fix preset_lpj leading to too short delays
  Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
  ARM: dts: r8a7791: Don't disable referenced optional clocks

Use "rockchip,rk3399-evb" compatible string for Rockchip RK3399
evaluation board.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch add rk3399-evb.dts for RK3399 evaluation board.
Tested on RK3399 evb.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch adds core dtsi file for Rockchip RK3399 SoCs.

The RK3399 has big/little architecture, which needs a separate
node for the PMU of each microarchitecture, for now it missing
the pmu node since the old one could not work well.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Merge "ARM64: DT: Hisilicon hip05 and hip06 updates for 4.7" Wei Xu:

- Fix its node without msi-cells for hip05
- Add nor flash node for hip05 D02 board
- Add initial dts for hip06 D03 board
- Reorder and add the hip06 D03 binding in the binding document

* tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
  Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
  arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
  arm64: dts: hip05: Add nor flash support
  arm64: dts: hip05: fix its node without msi-cells

Merge tag 'renesas-arm64-dt2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Merge "Second Round of Renesas ARM64 Based SoC DT Updates for v4.7" from Simon Horman:

* Don't disable referenced optional clocks in DT of r8a7795 SoC
* Populate EXTALR in DT of salvator-x board
* Enable PCIe in DT of salvator-x board

* tag 'renesas-arm64-dt2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: Don't disable referenced optional clocks
  arm64: dts: salvator-x: populate EXTALR
  arm64: dts: r8a7795: enable PCIe on Salvator-X
  arm64: dts: r8a7795: Add PCIe nodes
  arm64: dts: r8a7795: Use USB3.0 fallback compatibility string
  arm64: dts: r8a7795: Add CAN support
  arm64: dts: r8a7795: Add CAN external clock support

Add "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk3399 platform.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip06 D03 board.

Meanwhile, reorder the soc/board name alphabetically.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

The Hip06 soc has same cpu topology compared with Hip05, four clusters
and each cluster has quard Cortex-A57, but with different IO part,
like HNS, SAS and PCI, they are all upgraded. There are also not same
in ITS, MBIGEN and SMMU, etc.

This patch adds the initial dts for hip06 d03 board.

Note, there is no serial, because the soc use LPC uart, the serial node
is not needed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

This patch is to add support nor-flash. Notice, the pre-defined
partitions may not be used.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Fix commit abf9c25d ("arm64: dts: hip05: Append all gicv3 ITS
entries"), it forgets the property msi-cell, see arm,gic-v3.txt.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Reported-by: Jürg Billeter <j@bitron.ch>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

It can be used for the watchdog.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the disabled external scif clock node so that it
is not disabled to prevent this.
Reported-by: Jürg Billeter <j@bitron.ch>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: fix for v4.6 extracted from a larger patch targeted at v4.7]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add a master clock node generated by a 25MHz crystal oscillator.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Include the development base board, which is equipped with some
devices such as EEPROM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Pull "Broadcom ARM64-based SoC Device Tree changes" from Florian Fainelli:

- Anup enables a bunch of standard peripherals in the Northstar 2 DTS: PL330
  DMA, GIC maintenance interrupt, PL022 SPI controller

- Anup also re-orgnanizes the clock Device Tree fragments into a separate file
  for consistency with how other Broadcom SoCs are doing this

- Luke switches the SMP enable-method and reboot from a spin-table + syscon to
  the standard PSCI 1.0 firmware interface

* tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2 secondary core enablement via PSCI
  arm64: dts: Add ARM PL022 SPI DT nodes for NS2
  arm64: dts: Move NS2 clock DT nodes to separate DT file
  arm64: dts: Add maintenance interrupt for GIC in NS2 DT
  arm64: dts: Add ARM PL330 DMA DT node for NS2

Merge "First part of X-Gene DTS changes queued for v4.7" from Duc Dang:

This patch set only includes a single change to
fix the compatible string for SATA controllers on
X-Gene v2 SOC platforms.

* tag 'xgene-dts-for-v4.7-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Fix compatible string for X-Gene 2 SATA controller DTS node

Pull "ARM64: DT: Hisilicon Hi6220 soc and hikey board updates for 4.7" from Wei Xu

- Reserve memory regions for Hi6220
- Add sp804 timer node for Hi6220
- Add cpu and cluster level's low power state for Hi6220
- Add gpio configuration nodes for Hi6220
- Add pinctrl configuration nodes for Hi6220
- Add spi related nodes for Hi6220
- Add i2c nodes for Hi6220
- Add i2c nodes to work with mezzanine boards
- Add usb nodes for Hi6220
- Add mailobx node for Hi6220
- Add SRAM node and stub clock node for Hi6220
- Add pinctrl nodes for uarts and enable them
- Add LED nodes for hi6220-hikey board
- Add hi655x pmic node for Hi6220
- Add dwmmc nodes for Hi6220
- Add wifi nodes support for Hi6220-Hikey board
- Register thermal sensor for Hi6220
- Register Hi6220's thermal zone for power allocator
- Add L2 cache topology for Hi6220

* tag 'hi6220-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: Add L2 cache topology to Hi6220
  arm64: dts: register Hi6220's thermal zone for power allocator
  arm64: dts: register Hi6220's thermal sensor
  arm64: dts: add wifi nodes support for hi6220-hikey
  arm64: dts: add dwmmc nodes for hi6220
  arm64: dts: hikey: Add hi655x pmic dts node
  arm64: dts: add LED nodes for hi6220-hikey
  arm64: dts: hi6220: add pinctrl for uarts and enable them
  arm64: dts: add Hi6220's stub clock node
  arm64: dts: add mailbox node for Hi6220
  arm64: dts: Add hi6220 usb node
  arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards
  arm64: dts: add all hi6220 i2c nodes
  arm64: dts: add Hi6220 spi configuration nodes
  arm64: dts: add Hi6220 pinctrl configuration nodes
  arm64: dts: Add Hi6220 gpio configuration nodes
  arm64: dts: enable idle states for Hi6220
  arm64: dts: add sp804 timer node for Hi6220
  arm64: dts: Reserve memory regions for hi6220

Merge tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64

Pull "ARMv8 Juno DT updates for v4.7" from Sudeep Holla:

Just one update: Support for external expansion bus useful for
additional hardware e.g.LogicTile Express daughterboards (Brian Starkey)

* tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: Add external expansion bus to DT

Merge tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64

Merge "arm64: tegra: Changes for v4.7-rc1" from Thierry Reding

A couple of cleanups and fixes to various device trees, enable power and
volume keys on Jetson TX1, use stdout-path to define the serial port (so
it doesn't have to be specified on the kernel command-line) and add
Google Pixel C (a.k.a. Smaug) support.

* tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Enable cros-ec and charger on Smaug
  arm64: tegra: Add pinmux for Smaug board
  arm64: tegra: Add stdout-path for various boards
  arm64: tegra: Remove unused #power-domain-cells property
  arm64: tegra: Add gpio-keys nodes for Smaug
  arm64: tegra: Enable power and volume keys on Jetson TX1
  arm64: tegra: Add support for Google Pixel C
  arm64: tegra: Replace legacy *,wakeup property with wakeup-source
  arm64: tegra: Fix copy/paste typo in several DTS includes
  arm64: tegra: Remove 0, prefix from unit-addresses

Merge tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64

Merge "Samsung Device Tree ARM64 updates and improvements for v4.7" from Krzysztof Kozlowski:

1. Add PL330 DMA controller and Thermal Management Unit to Exynos 7.

* tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: Add nodes for pdma0 and pdma1 for exynos7
  arm64: dts: exynos: Add TMU node for exynos7

We export some clock IDs for the reference drivers need them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The rga clock supplying the working clock on the rk3399 is actually
called rga-core in the manual. As the clock id has neither been
assigned nor released with a full kernel release, we can still change
the id to the more appropriate naming.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the id for the general gpu soft-reset, that got documented only in
newer TRM versions.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

In order to be standard to manage for rockchip SoCs,  move the thermal
data into rk3368 dtsi, we needn't to add a new file for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Declare PSCI-1.0 node and enable CPU_ON method via PSCI.  Spin-table
memreserve has been removed as well as syscon based reset, as PSCI-1.0
expects reset implementation in firmware.
Signed-off-by: Luke Starrett <luke.starrett@broadcom.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

On all shmobile ARM SoCs, loop-based delays may complete early, which
can be after only 1/3 (Cortex A9) or 1/2 (Cortex A7 or A15) of the
minimum required time.

This is caused by calculating preset_lpj based on incorrect assumptions
about the number of clock cycles per loop:
  - All of Cortex A7, A9, and A15 run __loop_delay() at 1 loop per
    CPU clock cycle,
  - As of commit 11d4bb1b ("ARM: 7907/1: lib: delay-loop: Add
    align directive to fix BogoMIPS calculation"), Cortex A8 runs
    __loop_delay() at 1 loop per 2 instead of 3 CPU clock cycles.

On SoCs with Cortex A7 and/or A15 CPU cores, this went unnoticed, as
delays use the ARM arch timer if available. R-Car Gen2 doesn't work if
the arch timer is disabled. However, APE6 can be used without the arch
timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This reverts commit 19417bd9 ("ARM: dts: porter: Enable SCIF_CLK
frequency and pins") as according to
http://elinux.org/File:R-CarM2-KOELSCH_PORTER-B_PORTER_C_Comparison.pdf
the external oscillator for SCIF_CLK is not mounted on the porter boards.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

clk_get on a disabled clock node will return EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their clocks property.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them to prevent this.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Some "please, no space before tabs" checkpatch warnings slipped through
the recent addition of the rk3399 dt-binding header, so fix them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch adds the L2 cache topology on Hi6220. Hi6220 has two
clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

With profiling Hi6220's power modeling so get dynamic coefficient and
sustainable power. So pass these parameters from DT.

Now enable power allocator with only one actor for CPU part, so directly
use cluster0's thermal sensor for monitoring temperature.
Reviewed-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Bind thermal sensor driver for Hi6220.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add wifi nodes support for hi6220-hikey
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add all three dwmmc nodes description for hi6220
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>