Merge tag 'renesas-soc3-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Third Round of Renesas ARM Based SoC Updates for v3.20" from Simon
Horman:

* Special-case PM domains with memory-controllers

* tag 'renesas-soc3-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: R-Mobile: Special-case PM domains with memory-controllers
  ARM: shmobile: R-Mobile: Generalize adding/looking up special PM domains
  ARM: shmobile: R-Mobile: Consolidate rmobile_pd_suspend_*()
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-soc2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Second Round of Renesas ARM Based SoC Updates for v3.20" from Simon
Horman:

* Add DT support for PM domains

* tag 'renesas-soc2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: R-Mobile: Add DT support for PM domains
  ARM: shmobile: R-Mobile: Store SYSC base address in rmobile_pm_domain
  ARM: shmobile: R-Mobile: Use generic_pm_domain.attach_dev() for pm_clk setup
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge "ARM: STi: SoC changes for v3.20, round 1" from Maxime Coquelin:

Highlights:
-----------
 - Add support for STiH418 SoC

* tag 'sti-soc-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti:
  ARM: STi: Add STiH418 SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/soc

Merge "at91: cleanup for 3.20 #2" from Nicolas Ferre:

Second batch of cleanup for 3.20:
- By reworking the PM code, we can remove the AT91 more specific initialization
- We are using DT for SRAM initialization now, so we can remove its explicit
  mapping
- The PMC clock driver now hosts IDLE function for at91rm9200 with other
  SoCs ones.

* tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (37 commits)
  ARM: at91: move at91rm9200_idle() to clk/at91/pmc.c
  ARM: at91: remove unused at91_init_sram
  ARM: at91: sama5d4: remove useless call to at91_init_sram
  ARM: at91: remove useless map_io
  ARM: at91: pm: prepare for multiplatform
  ARM: at91: pm: add UDP and UHP checks to newer SoCs
  ARM: at91: pm: use the mmio-sram pool to access SRAM
  ARM: at91: pm: rework cpu detection
  ARM: at91: dts: sama5d3: add ov2640 camera sensor support
  ARM: at91: dts: sama5d3: change name of pinctrl of ISI_MCK
  ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset}
  ARM: at91: dts: sama5d3: move the isi mck pin to mb
  ARM: at91: dts: sama5d3: add missing pins of isi
  ARM: at91: dts: sama5d3: split isi pinctrl
  ARM: at91: dts: sama5d3: add isi clock
  ARM: at91/dt: ethernut5: use at91sam9xe.dtsi
  ARM: at91/dt: Add a dtsi for at91sam9xe
  ARM: at91/dt: add SRAM nodes
  ARM: at91/dt: at91rm9200ek: enable RTC
  ARM: at91/dt: rm9200: add RTC node
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Enable smp for HiP01 board.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
[olof: split off the dts change to a separate commit]
Signed-off-by: Olof Johansson <olof@lixom.net>

As hix5hd2 and hip01 has the same secondary_startup
so rename hix5hd2_secondary_startup to
to hisi_secondary_startup.

the hip01 will use hisi_secondary_startup for the
secondary core boot.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

As hix5hd2 and hip01 has the same .smp_prepare_cpus
in struct smp_operations, so rename hix5hd2_smp_prepare_cpus
to hisi_common_smp_prepare_cpus.

the hip01 will use hisi_common_smp_prepare_cpus in its
struct smp_operations.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Enable Hisilicon HiP01 SoC. This HiP01 SoC series support both
one core or dual cores and quad cores. The core is Cortex A9.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Add the support of Hisilicon HiP01 debug uart.
The uart of hip01 is 8250 compatible.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'new-atlas7mach-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/soc

Merge "CSR new atlas7 machine, and delete old marco machine for 3.20" from
Barry Song:

drop CSR Marco machine and add Atlas7 new machine

This is the init support for CSR Atlas7 new SoC. Old Marco has never
shipped to customers and been dropped.

* tag 'new-atlas7mach-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
  ARM: sirf: add Atlas7 machine support
  ARM: sirf: move to debug_ll_io_init and drop map_io
  ARM: sirf: move platsmp to support Atlas7 SoC
  ARM: sirf: drop Marco machine
  ARM: sirf: drop Marco support in reset controller module
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'atlas7-lldebug-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/soc

Merge "CSR atlas7 debug ports for 3.20" from Barry Song:

add debug ports for CSRatlas7 SoC

Because Marco chip has never shipped to customers and has been replaced
by Atlas7, so we do the below
- drop Marco's debug port
- add debug ports for Atlas7

* tag 'atlas7-lldebug-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
  ARM: sirf: add two debug ports for CSRatlas7 SoC
  ARM: sirf: drop Marco low-level debug port
Signed-off-by: Olof Johansson <olof@lixom.net>

CSRatlas7 is next-gen auto SoC from CSR.
It could bring to customers most integrated SoC solution:
- World leading Bluetooth 4.0 and GNSS baseband
- Audio processing, analog CODEC and ADC by DSP
- Analog video input
- SDR accelerators
- CAN bus support by Cortex-M3
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

This patch moves to debug_ll_io_init(), then finally drops CSR map_io()
machine callbacks.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

This patch breaks Marco SMP support, but Marco project has been dropped.
So it corrects cpu1 jump/flag address for Atlas7 and removes scu related
logic as scu doesn't expose in cortex-a7.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

Marco will not be supported any more. it has been replaced by CSR
Atlas7.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

Marco will not be supported any more. It has been replaced by CSR
Atlas7.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

this patch adds UART0 and UART1 as LLUART port, as the new Atlas7
registers layout are different, it also refines some names of old
hard-coded MARCOs and uses CONFIG_DEBUG_UART_PHYS/DEBUG_UART_VIRT
to define different base addresses for multiple ports.
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

Move at91rm9200_idle() along with at91sam9_idle() in clk/at91/pmc.c.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

SRAM initialization is now done through the mmio-sram driver and
at91_init_sram() is not called anymore, remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Now that the SRAM is initialized by the mmio-sram driver, .map_io is useless.
remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Split at91_pm_init() in three variants that are called by the respective SoCs
.init_machine. This allows to remove the of_machine_is_compatible() calls and
move at91_pm_init() out of arch_initcall() which is required for multiplatform.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Check UDP and UHP on sam9x5, sam9n12 and the sama5 series.
Check UHP on the sam9g45.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Now that the SRAM is part of a genpool, use it to allocate memory to use for the
slowclock implementation.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Store SoC differences in a struct to remove cpu_is_* usage.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

This patch adds support to STiH418 SoC.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

Add a special case for PM domains containing a memory-controller.
Such a PM domain must not be turned off if memory is in use.

On sh73a0 PM domains A4BC0 and A4BC1 each contain an SDRAM Bus State
Controller (SBSC). On r8a73a4 PM domain A3BC contains two DDR Bus
Controllers (DBSC).  In both cases, there are no other devices in these
PM domains, so they were eligible for power down, crashing the system.

On r8a7740 the DDR3 Bus State Controller (DBSC3) is located in A4S,
whose child domain A3SM contains the CPU core. Hence A4S is never turned
off, and no crash happened.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Make adding special PM domains to an array, and looking them up
later, more generic, so it can be used for all special hardware blocks.
The type of PM domain is also stored, so rmobile_setup_pm_domain() can
use a switch() statement instead of a chain of if/else statements.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Consolidate the identical rmobile_pd_suspend_*() routines that just
return -EBUSY to prevent a PM domain from being powered down into a
single rmobile_pd_suspend_busy().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

According to v4l2 dt document, we add:
  a camera host: ISI port.
  a i2c camera sensor: ov2640 port.
to sama5d3xmb.dtsi.

The ov2640 node defines the pinctrls, clocks and refer to isi port.
The ISI node also has a reference to the ov2640 port.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

For sama5d3xmb board, the pins: pinctrl_isi_pck_as_mck is pck1, and
used to provide MCK for camera sensor.

We change its name to: pinctrl_pck1_as_isi_mck.

As we want camera sensor instead of ISI to configure the pck1 (ISI_MCK) pin.
So we remove this pinctrl from ISI DT node. It will be added in sensor's
DT node.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

For sama5d3xmb board, the pins: pinctrl_isi_{power,reset} is used to
power-down or reset camera sensor.
So we should let camera sensor instead of ISI to configure the pins.

This patch will change pinctrl name from pinctrl_isi_{power,reset} to
pinctrl_sensor_{power,reset}. And remove these two pinctrl from ISI's
DT node. We will add these two pinctrl to sensor's DT node.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

The mck is decided by the board design, move it to mb related
dtsi file.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

The ISI has 12 data lines, add the missing two data lines.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

As the ISI has 12 data lines, however we only use 8 data lines with
sensor module. So, split the data line into two groups which make
it can be choosed depends on the hardware design.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Add ISI peripheral clock in sama5d3.dtsi.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

The ethernut5 is actually based on an at91sam9xe, use the correct dts include.

Cc: Martin Reimann <martin.reimann@egnite.de>
Cc: Tim Schendekehl <tim.schendekehl@egnite.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

at91sam9xe is slightly different from at91sam9260, in particular it has a
different SRAM size and location.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Add nodes for the SRAM available on atmel SoCs
For the at91sam9260 and the at91sam9g20, address mirroring is used to create a
single contiguous SRAM range instead of declaring two separate banks.

Also remove leftover TODOs in the sam9g45 file
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>