- 25 Apr, 2013 1 commit
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Thomas Abraham authored
On device tree enabled exynos platforms, retrieve the physical base address of the chip-id controller from device tree and create a virtual I/O mapping for the chip-id controller. This helps to remove the chip-id controller entry from the statically defined I/O mapping tables. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- 08 Apr, 2013 39 commits
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Subash Patel authored
PDMA0@0x121000 changes are added into the architecture DTS file. Signed-off-by:
Subash Patel <subash.rp@samsung.com> Signed-off-by:
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Amit Daniel Kachhap authored
Add cpufreq controller device node for Exynos5440 SoC for passing parameters like controller base address, interrupt and cpufreq table. This node is added outside cpu0 as this driver is now a platform driver and a new device structure is needed. Cc: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by:
Amit Daniel Kachhap <amit.daniel@samsung.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Thomas Abraham authored
The Exynos5440 common clock driver has changed the clock ID's for some of the clocks. Fix the gmac clock entries in Exynos5440 dtsi file accordingly. Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Signed-off-by:
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Kukjin Kim authored
This patch adds SD5v1.dts file for supporting SD5v1(Exynos5440) board. Signed-off-by: -
Subash Patel authored
Updated the bootargs to boot the system with rootfs in /dev/sda2 instead of ramdisk. Signed-off-by:
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Subash Patel authored
PMU in exynos5440 generates one interrupt per core and needs to be passed from DT to GIC to register it. Signed-off-by:
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Byungho An authored
This patch adds node for GMAC for exynos5440 SoC supported by GMAC driver. Signed-off-by:
Byungho An <bh74.an@samsung.com> Signed-off-by:
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Thomas Abraham authored
Exynos5440 pin-controller generates eight interrupts to support gpio interrupts. List those interrupt numbers in the pin-controller node. Signed-off-by:
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Vikas Sajjan authored
Add DT binding documentation for the FIMD IP block found in Samsung SoCs. Signed-off-by:
Vikas Sajjan <vikas.sajjan@linaro.org> Reviewed-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Vikas Sajjan authored
This patch adds FIMD related nodes for the Origen Quad board. Signed-off-by:
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Vikas Sajjan authored
This patch adds a common FIMD device node for all Exynos4 SoCs. Signed-off-by:
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Sylwester Nawrocki authored
This patch adds device tree node for the SYSREG registers block found in Samsung S5P/Exynos SoC series. The SYSREG module generates control signals for the ARM CPU and various IP blocks and buses. SYSREG block registers are exposed through APB bus interface. A sysreg device tree node is to be associated with mfd syscon driver and all SYSREG clients should use regmap interface it provides. It allows to eliminate any possible races and conflicts should different drivers attempt to concurrently access same register. Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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Leela Krishna Amudala authored
Add display timing node to exynos5250-smdk5250.dts Signed-off-by:
Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by:
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Leela Krishna Amudala authored
This adds common FIMD device node for all Exynos5 SoCs Signed-off-by:
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Giridhar Maruthy authored
Exynos5440 has GIC which has virtualization support in them. These are used by KVM. Signed-off-by:
Giridhar Maruthy <giridhar.m@samsung.com> Signed-off-by:
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Doug Anderson authored
The exynox4210-ehci and exynos4210-ohci nodes need a clock specified using the common clock framework. Document it. Signed-off-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
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Doug Anderson authored
This is a fixup to two device tree nodes that have already landed but without clock nodes since the transition to common clock happened at the same time. Signed-off-by:
Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by:
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Alexander Graf authored
The exynos 5250 SoC supports A15 style architected timers. Indicate this through the device tree. This is required by KVM. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Alexander Graf authored
The GIC in the exynos5250 SoC is A15 compliant. Show this through the device tree, so that we can use the GIC for KVM. Also add the respective A15 memory regions and interrupt links. Signed-off-by:
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Sachin Kamat authored
Added HDMI hot plug and regulator nodes to Arndale DT file. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
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Sachin Kamat authored
Added MFC codec node to Arndale DT file. Signed-off-by:
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Sachin Kamat authored
Added vmmc regulator node to Arndale DT file. Signed-off-by:
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Amit Daniel Kachhap authored
Added S5M8767 PMIC DT nodes for Arndale board. Only the used LDO's/BUCK are defined here. Also the nodes describe the default/reset state LDO's and no power mangement tuning is implemented. The usage desription can be found in s5m8767 device tree binding documentation. Signed-off-by:
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Tushar Behera authored
Added GPIO buttons DT node to Arndale board file. Signed-off-by:
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Sachin Kamat authored
This is required to keep the existing functionality of having no write protect pin on Arndale board. Signed-off-by:
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Tushar Behera authored
Signed-off-by:
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Thomas Abraham authored
Add default pin state information for all client nodes that require pin configuration support using pinctrl interface. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Tested-by:
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Thomas Abraham authored
Add default pin state information for all client nodes that require pin configuration support using pinctrl interface. Signed-off-by:
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Sachin Kamat authored
Added documentaion about G2D bindings. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Inki Dae <inki.dae@samsung.com> Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to Origen4412 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to SMDK4412 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to exynos4x12.dtsi file. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to Origen4210 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to SMDKV310 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to Exynos4210. Signed-off-by:
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Kukjin Kim authored
Conflicts: arch/arm/boot/dts/exynos4.dtsi arch/arm/boot/dts/exynos5440.dtsi
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Thomas Abraham authored
The functions exynos4_clk_init and exynos4_clk_register_fixed_ext are applicable only on Exynos4 non-dt platforms. But when building Exynos5 platforms without including Exynos4 platforms, the following errors show up. arch/arm/mach-exynos/built-in.o: In function `exynos_init_time': arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init' arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext' Fix this compilation errors by marking these calls as Exynos4 specific. Signed-off-by:
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Tushar Behera authored
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by:Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Sylwester Nawrocki authored
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by:
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