- 01 Jul, 2020 40 commits
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Chris Park authored
[Why] All YCbCr420 resolutions 5K and above have tiling and discoloration issues. The issue can be remedied by forcing ODM combine from 5K to 8K. 10K resolution requires ODM 4:1. The mechanism of what the real problem is, that is inherent in ODM combine programming, doesn't seem to be pointed at singular register programming (CLK, MPC, DCSURF, etc.), and needs more in-depth programming sequence review for these new use case scenarios. Until then, workaround to enable ODM combine is proposed. While it is not our policy, HW spreadsheet also recommends turning on ODM for these scenario to lower the voltage. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Brandon Syu authored
[Why] There is using pixelclk AVFS for dppclk, that would cause issue. [How] To use dispclk AVFS for both dispclk and dppclk. There would choose dppclk for request voltage when dispclk wouldn't be updated case. If dispclk need to be updated, then it'll choose the bigger one from dppclk and dispclk for request voltage. Signed-off-by:
Brandon Syu <Brandon.Syu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Eric Yang authored
[Why] If optimized init is done in FW. DCN init be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Dale Zhao authored
[WHY] Check max_tmds_clk_mhz firstly will restrict pixel clock under HDMI 1.4, thus HDMI2.0 port can't correctly support 4K 60Hz. [HOW] Fine tune the logic to check max_forum_tmds_clk_mhz firstly. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
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Jake Wang authored
[Why & How] Need to check if local_sink is NULL before accessing. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why] DC global validation can fail when userspace requests to draw large plane without performing the clipping themselves. This is observed in the IGT kms_plane panning tests for 4K displays where they draw an 8K plane without any clipping while expecting only the top 4K to be drawn. [How] DRM already has helpers to take care of the clipping necessary and to mark whether a plane is visible or not, so make use of these helpers in DM before passing the plane to DC. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Update scratch information for boot status Signed-off-by:
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Camille Cho authored
[Why] dc_link_set_psr_allow_active() always returns true, even in the case that PSR is not supported. [How] Hook up the return value of dc_link_set_psr_allow_active(). Signed-off-by:
Camille Cho <Camille.Cho@amd.com> Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Side-by-side and Top-and-bottom stereo configurations fail DML mode validation due to Viewport exceeded. This is because we consider the planes as being pipe split in pipe population so we end up doubling the viewport width, eg. from 4k to 8k. [How] These pipes technically aren't hsplit, so add a check for determining whether is_hsplit should be set. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] assr is content protection for eDP, in order to use it we need to call psp ta (dtm) [How] We have a enable_assr callback, hook into this and call the correct psp cmd id to enable assr. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Michael Strauss authored
[WHY] Currently DC doesn't check requested pixel clock against an EDID specified TMDS max clock if it exists, passing modes that should fail [HOW] Add max TMDS clk to edid caps and perform check during validation Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
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Yi-Ling Chen authored
[why] dc->hwss->edp_backlight_control is null, it would casue it only be off main-link of eDP. It is not worng behavior for eDP power sequence off. [how] Must use hwseq->funcs.edp_backlight_control finction pointer for edp backlight. Signed-off-by:
Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Mikita Lipski authored
[why] The calculation of virtual channel payload would not take link settings in account. As we calculate VCPI slots needed both PBN for stream and also PBN per time slot. Before we would use generic PBN per time slot, which would not change with link settings causing wrong Payload allocation. [how] Provide PBN per time slot for each Virtual channel payload calculation. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
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Wyatt Wood authored
[Why] Hw lock manager adds the ability to lock pipe, cursor, and dig in fw. [How] Send hw lock command to fw to lock pipe, cursor, and dig. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Sonny Jiang authored
Enable asic Verde, Tahiti and Pitcairn UVD block. Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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Sonny Jiang authored
Enable Oland UVD block. Signed-off-by:
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Sonny Jiang authored
Signed-off-by:
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Sonny Jiang authored
Implement SI uvd_ctx_rreg/wreg functions. Signed-off-by:
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Sonny Jiang authored
Implement SI UVD. The SI UVD firmware requires validation. v2: squash in missing brace fix (Colin Ian King) Signed-off-by:
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Sonny Jiang authored
Add SI UVD registers files. Signed-off-by:
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Sonny Jiang authored
Fix packet_type0 definition in sid. Signed-off-by:
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Sonny Jiang authored
For implement UVD on SI asic, add Oland, Pitcairn, Verde, Tahiti firmwares. Signed-off-by:
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Alex Deucher authored
drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Qingqing Zhuo authored
when compiled with allmodconfig option, there are error messages as below: ERROR: modpost: "mod_color_is_table_init" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_get_table" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_set_table_init_state" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! To fix the issue, this commits removes CONFIG_DRM_AMD_DC_DCN guard in color/makefile. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> CC: Lewis Huang <Lewis.Huang@amd.com> CC: Aric Cyr <Aric.Cyr@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Harry Wentland <hwentlan@amd.com> CC: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> CC: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> CC: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
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James Zhu authored
SOC15_WAIT_ON_RREG's return value needn't always been handled by caller. new design is to fix this kind of unused variable. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Wenhui Sheng authored
sdma fw isn't released when module exit Reviewed-by:
Wenhui Sheng <Wenhui.Sheng@amd.com> Signed-off-by:
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Wenhui Sheng authored
invoke amdgpu_ring_fini for each sdma instance Reviewed-by:
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Wenhui Sheng authored
On Navi12 platform, node power_dpm_force_performance_level doesn't work correctly in one-VF mode with at least three smu messages not supported: SMU_MSG_SetSoftMaxByFreq SMU_MSG_SetSoftMinByFreq SMU_MSG_TransferTableDram2Smu Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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John Clements authored
support for setting up XGMI FB address regions Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Kevin Wang authored
the module parameter sched_hw_submission is probably from user mode, and the kernel need to check whether it is legal. 1. align hw sched jobs to power of 2 and set minimum number is 2. 2. use kernel api is_power_of_2() to simplify driver code. Signed-off-by:
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Alvin Lee authored
[Why] We need to update each p-state in the bounding box [How] Update states when assigning values to clocks v2: squash in patch to set min values (Alex) Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Colin Ian King authored
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Nirmoy Das authored
Remove unused amdgpu_xgmi_hive_try_lock() and smu7_reset_asic_tasks(). Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Alex Deucher authored
It's only applicable on newer asics. We could end up here when using DC on older asics like SI or KV. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1170Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
If there are no supported callbacks. We'll fall back to the nominal clocks. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1170Reviewed-by:
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James Zhu authored
Include header file vcn_v2_0.h Signed-off-by:
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