- 09 Apr, 2012 22 commits
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Daniel Vetter authored
This got copy-pasted from an older version. The newer kinds of workarounds don't need this anymore. Shame on me for not noticing when picking up the vlv irq patch. Reviewed-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-Off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Ben Widawsky authored
We can now open-code the get/put irq functions as they were just abstracting single register definitions. It would be nice to merge this in with the IRQ handling code... but that is too much work for me at present. In addition I could probably collapse this in to a lot of the Ironlake stuff, but I don't think it's worth the potential regressions. This patch itself should not effect functionality. CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ben Widawsky authored
- gen6 put/get only need one argument rflags and gflags are always the same (see above explanation) - remove a couple redundantly defined IRQs - reordered some lines to make things go in descending order Every ring has its own interrupts, enables, masks, and status bits that are fed into the main interrupt enable/mask/status registers. At one point in time it seemed like a good idea to make our functions support the notion that each interrupt may have a different bit position in the corresponding register (blitter parser error may be bit n in IMR, but bit m in blitter IMR). It turned out though that the HW designers did us a solid on Gen6+ and this unfortunate situation has been avoided. This allows our interrupt code to be cleaned up a bit. I jammed this into one commit because there should be no functional change with this commit, and staging it into multiple commits was unnecessarily artificial IMO. CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: -
Eugeni Dodonov authored
DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC and DDID we need to consult SFUSE_STRAP values. Signed-off-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by:
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Eugeni Dodonov authored
Watermark line time registers for display low power watermark. v2: improve bit names as suggested by Chris Wilson Signed-off-by:
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Eugeni Dodonov authored
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP and FDI. Signed-off-by:
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Eugeni Dodonov authored
Those are used to control the display core clock. v2: change the enable bit setting, spotted by Rodrigo Vivi. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Eugeni Dodonov authored
Different registers are identified by their target id and offset. To simplify their programming, they are called as <RegisterName><TargetId>. For example, SSCCTL register accessed through SBI at target id 6 and offset 0c is called SBI_SSCCTL6. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Eugeni Dodonov authored
Multiple clocks can drive different outputs. v2: use the port enums to access individual ports v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Eugeni Dodonov authored
This PLL control can drive DDI ports at desired frequencies for DisplayPort and FDI connections. Reviewed-by:
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Eugeni Dodonov authored
Pixel clock gating control for Lynx point. Reviewed-by:
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Eugeni Dodonov authored
Those are responsible for the Sideband Interface programming. v2: rename SBI bits to better reflect their meaning Reviewed-by:
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Eugeni Dodonov authored
Those registers are used to train DDI buffer translations for each link type. v2: access each port registers through the DDI_BUF_TRANS macro Signed-off-by:
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Eugeni Dodonov authored
There is one instance of those registers for each DDI port. v2: access registers via the DDI_BUF_CTL() macro Reviewed-by:
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Eugeni Dodonov authored
There is one set of those registers for each port. Signed-off-by:
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Eugeni Dodonov authored
This is one set of those registers for each pipe. v2: use port enum to access individual registers Signed-off-by:
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Eugeni Dodonov authored
There is one set of such registers for each pipe (A/B/C/EDP). v2: update to use DDI PORTS enum v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Eugeni Dodonov authored
There are 5 DDI ports on Haswell. Port A is always enabled, and is the one connected to eDP, and Port E is the one that can be connected to the PCH using FDI protocol. Ports B, C, D and E can be used for digital outputs. Signed-off-by:
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Eugeni Dodonov authored
This defines the registers used by different power wells. Reviewed-by:
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Eugeni Dodonov authored
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Eugeni Dodonov authored
This adds product definitions for desktop, mobile and server boards. v2: split into a separate patch, add .has_pch_split feature. Signed-off-by:
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Eugeni Dodonov authored
The macro is becoming too complex and with VLV upon us it can lead to confusion. So transforming this into a feature check instead. Signed-off-by:
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- 28 Mar, 2012 18 commits
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Jesse Barnes authored
Haven't seen this yet, but it doesn't hurt. Signed-off-by:
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Jesse Barnes authored
ValleyView has a new interrupt architecture; best to put it in a new set of functions. Also make sure the ring mask functions handle ValleyView. FIXME: fix flipping; need to enable interrupts and call prepare/finish Signed-off-by:
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Jesse Barnes authored
Signed-off-by:
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Jesse Barnes authored
ValleyView handles force wake differently than previous chipsets, so add a couple of new functions for it. But leave it disabled by default until we test it (need a chip with the Punit enabled first). Signed-off-by:
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Jesse Barnes authored
... and bind it right to the PCI id. Note that there are still a few things to fix here: - we need to move the tlb flush to a better place in drm/i915. - we need to check snoop support on vlv and implement it. Signed-off-by:
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Jesse Barnes authored
We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the register for doing so is above the range we normally map. Map the whole register space to make sure we can get it. v2: only map the larger space on gen7+ (Daniel) Signed-off-by:
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Shobhit Kumar authored
HDMI register offsets are different in Valleyview. Add support for the same. v2: drop superfluous comments in HDMI init (Daniel) Signed-off-by:
Beeresh G <beeresh.g@intel.com> Signed-off-by:
Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by:
Vijay Purushothaman <vijay.a.purushothaman@intel.com> Reviewed-by:
Jesse Barnes <jesse.barnes@intel.com> Signed-off-by:
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Gajanan Bhat authored
This patch adds support for programming drain latency registers of Pondicherry memory arbiter of Valleyview. v2: clarify function names (Daniel) fix summary typo (Daniel) v3: add parens (Ben) make drain function return bool (Ben) Acked-by:Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by:
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Jesse Barnes authored
Set required clock gating and chicken bits on VLV. v2: set PIXEL_SUBSPAN_COLLECT_OPT_DISABLE too (Ben) move function below ivb version to pretend to be consistent (Ben) Reviewed-by: -
Jesse Barnes authored
ValleyView puts some display related registers like the PLL controls and dividers behind the DPIO bus. Add simple indirect register access routines to get to those registers. v2: move new wait_for macro to intel_drv.h (Ben) fix DPIO_PKT double write (Ben) add debugfs file Reviewed-by: -
Jesse Barnes authored
Add register definitions for the new VLV PLL bits. v2: remove unused bits & regs (Ben) Acked-by:
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Jesse Barnes authored
Add support for ValleyView watermark handling. v2: remove unused reg & bit definitions (Ben) Acked-by:
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Jesse Barnes authored
For use by the rest of the ValleyView code. v2: fix desktop variant to not set is_mobile (Ben) Acked-by:
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Daniel Vetter authored
Makes it more readable and maintainable. ValleyView will add its own PLL update function in a later patch. v2: split LVDS bits out of this patch (Daniel) v3: fix dropped DP dithering hunk (Daniel) Acked-by:
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Daniel Vetter authored
Just to make things clearer and reduce the size of this monstrosity. v2: make sure 8xx PLL update function calls update_lvds too (Daniel) Signed-off-by:
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Chris Wilson authored
Fixes a regression from 9e984bc1 (drm/i915: Don't do MTRR setup if PAT is enabled) where we left the MTRR as 0 and so tried to free a MTRR we did not own during unload. Reported-and-tested-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
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Daniel Kurtz authored
This memory is always allocated, and it is always a fixed size, so just allocate it along with the rest of the driver state. Signed-off-by:
Daniel Kurtz <djkurtz@chromium.org> Reviewed-by:
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Daniel Kurtz authored
There is no GMBUS "disabled" port 0, nor "reserved" port 7. For the other 6 ports there is a fixed 1:1 mapping between pin pairs and gmbus ports, which means every real gmbus port has a gpio pin. Given these realizations, clean up gmbus initialization. Tested on Sandybridge (gen 6, PCH == CougarPoint) hardware. Signed-off-by:
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