1. 03 Feb, 2020 2 commits
  2. 31 Jan, 2020 7 commits
    • Stephen Boyd's avatar
      Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom',... · db865ee4
      Stephen Boyd authored
      Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next
      
       - Support for Xilinx Versal platform clks
       - Display clk controller on qcom sc7180
       - Video clk controller on qcom sc7180
       - Graphics clk controller on qcom sc7180
       - CPU PLLs for qcom msm8916
       - Fixes for clk controllers on qcom msm8998 SoCs
       - Move qcom msm8974 gfx3d clk to RPM control
       - Display port clk support on qcom sdm845 SoCs
       - Global clk controller on qcom ipq6018
       - Adjust composite clk to new way of describing clk parents
       - Add a driver for BCLK of Freescale SAI cores
      
      * clk-imx: (32 commits)
        clk: imx: Add support for i.MX8MP clock driver
        dt-bindings: imx: Add clock binding doc for i.MX8MP
        clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
        clk: imx: imx8mq: Switch to clk_hw based API
        clk: imx: imx8mm: Switch to clk_hw based API
        clk: imx: imx8mn: Switch to clk_hw based API
        clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
        clk: imx: gate3: Switch to clk_hw based API
        clk: imx: add hw API imx_clk_hw_mux2_flags
        clk: imx: add imx_unregister_hw_clocks
        clk: imx: clk-composite-8m: Switch to clk_hw based API
        clk: imx: clk-pll14xx: Switch to clk_hw based API
        clk: imx7up: Rename the clks to hws
        clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
        clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
        clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
        clk: imx: Rename sccg and frac pll register to suggest clk_hw
        clk: imx: imx7ulp composite: Rename to show is clk_hw based
        clk: imx: pllv2: Switch to clk_hw based API
        clk: imx: pllv1: Switch to clk_hw based API
        ...
      
      * clk-ti:
        clk: ti: clkctrl: Fix hidden dependency to node name
        clk: ti: add clkctrl data dra7 sgx
        clk: ti: omap5: Add missing AESS clock
        clk: ti: dra7: fix parent for gmac_clkctrl
        clk: ti: dra7: add vpe clkctrl data
        clk: ti: dra7: add cam clkctrl data
        dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
      
      * clk-xilinx:
        clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
        clk: zynqmp: Fix divider calculation
        clk: zynqmp: Add support for get max divider
        clk: zynqmp: Warn user if clock user are more than allowed
        clk: zynqmp: Extend driver for versal
        dt-bindings: clock: Add bindings for versal clock driver
      
      * clk-nvidia:
        clk: tegra20/30: Explicitly set parent clock for Video Decoder
        clk: tegra20/30: Don't pre-initialize displays parent clock
        clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
        clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
        clk: tegra: Mark fuse clock as critical
      
      * clk-qcom: (35 commits)
        clk: qcom: rpmh: Sort OF match table
        dt-bindings: fix warnings in validation of qcom,gcc.yaml
        dt-binding: fix compilation error of the example in qcom,gcc.yaml
        clk: qcom: Add ipq6018 Global Clock Controller support
        clk: qcom: Add DT bindings for ipq6018 gcc clock controller
        clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks
        clk: qcom: rpmh: Add IPA clock for SC7180
        clk: qcom: rpmh: skip undefined clocks when registering
        clk: qcom: Add video clock controller driver for SC7180
        dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
        dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
        clk: qcom: Add graphics clock controller driver for SC7180
        dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings
        dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
        clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent
        clk: qcom: Add display clock controller driver for SC7180
        dt-bindings: clock: Introduce QCOM sc7180 display clock bindings
        dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings
        clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration
        clk: qcom: alpha-pll: Remove useless read from set rate
        ...
      
      * clk-freescale:
        clk: fsl-sai: new driver
        dt-bindings: clock: document the fsl-sai driver
        clk: composite: add _register_composite_pdata() variants
      
      * clk-qoriq:
        clk: qoriq: add ls1088a hwaccel clocks support
        clk: ls1028a: Add clock driver for Display output interface
        dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
      db865ee4
    • Stephen Boyd's avatar
      Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas',... · 6e7a9f0c
      Stephen Boyd authored
      Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlogic' and 'clk-allwinner' into clk-next
      
       - Support dangerous debugfs actions on clks with dead code
       - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs
      
      * clk-debugfs-danger:
        clk: Add support for setting clk_rate via debugfs
      
      * clk-basic-hw:
        clk: divider: Add support for specifying parents via DT/pointers
        clk: gate: Add support for specifying parents via DT/pointers
        clk: mux: Add support for specifying parents via DT/pointers
        clk: asm9260: Use parent accuracy in fixed rate clk
        clk: fixed-rate: Document that accuracy isn't a rate
        clk: fixed-rate: Add clk flags for parent accuracy
        clk: fixed-rate: Add support for specifying parents via DT/pointers
        clk: fixed-rate: Document accuracy member
        clk: fixed-rate: Move to_clk_fixed_rate() to C file
        clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()
        clk: fixed-rate: Convert to clk_hw based APIs
        clk: gpio: Use DT way of specifying parents
      
      * clk-renesas:
        clk: renesas: Prepare for split of R-Car H3 config symbol
        dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo
        clk: renesas: r7s9210: Add SPIBSC clock
        clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
        clk: renesas: Remove use of ARCH_R8A7796
        clk: renesas: rcar-gen2: Change multipliers and dividers to u8
      
      * clk-amlogic:
        clk: clarify that clk_set_rate() does updates from top to bottom
        clk: meson: meson8b: make the CCF use the glitch-free mali mux
        clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
        clk: meson: g12a: fix missing uart2 in regmap table
        clk: meson: meson8b: use of_clk_hw_register to register the clocks
        clk: meson: meson8b: don't register the XTAL clock when provided via OF
        clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
        clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
        clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
        dt-bindings: clock: meson8b: add the clock inputs
        dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
      
      * clk-allwinner:
        clk: sunxi: a23/a33: Export the MIPI PLL
        clk: sunxi: a31: Export the MIPI PLL
        clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
        clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
        clk: sunxi-ng: r40: Export MBUS clock
        clk: sunxi: use of_device_get_match_data
      6e7a9f0c
    • Stephen Boyd's avatar
      Merge branches 'clk-uniphier', 'clk-warn-critical', 'clk-ux500', 'clk-kconfig'... · 36bf7a5b
      Stephen Boyd authored
      Merge branches 'clk-uniphier', 'clk-warn-critical', 'clk-ux500', 'clk-kconfig' and 'clk-at91' into clk-next
      
       - Warn about critical clks that fail to enable or prepare
       - Detect more PRMCU variants in ux500 driver
      
      * clk-uniphier:
        clk: uniphier: Add SCSSI clock gate for each channel
      
      * clk-warn-critical:
        clk: Warn about critical clks that fail to enable
        clk: Don't try to enable critical clocks if prepare failed
        clk: tegra: Fix double-free in tegra_clk_init()
        clk: samsung: exynos5420: Keep top G3D clocks enabled
        clk: qcom: Avoid SMMU/cx gdsc corner cases
        clk: qcom: gcc-sc7180: Fix setting flag for votable GDSCs
        clk: Move clk_core_reparent_orphans() under CONFIG_OF
        clk: at91: fix possible deadlock
        clk: walk orphan list on clock provider registration
        clk: imx: pll14xx: fix clk_pll14xx_wait_lock
        clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_table
        clk: imx: clk-composite-8m: add lock to gate/mux
      
      * clk-ux500:
        clk: ux500: Fix up the SGA clock for some variants
      
      * clk-kconfig:
        clk: Fix Kconfig indentation
      
      * clk-at91:
        clk: at91: sam9x60: fix programmable clock prescaler
        clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
      36bf7a5b
    • Stephen Boyd's avatar
      Merge branches 'clk-init-allocation', 'clk-unused' and 'clk-register-dt-node-better' into clk-next · 28db9a8c
      Stephen Boyd authored
       - Let clk_ops::init() return an error code
       - Add a clk_ops::terminate() callback to undo clk_ops::init()
      
      * clk-init-allocation:
        clk: add terminate callback to clk_ops
        clk: let init callback return an error code
        clk: actually call the clock init before any other callback of the clock
      
      * clk-unused:
        clk: bm1800: Remove set but not used variable 'fref'
      
      * clk-register-dt-node-better:
        clk: Use parent node pointer during registration if necessary
      28db9a8c
    • Yangbo Lu's avatar
      clk: qoriq: add ls1088a hwaccel clocks support · a932872f
      Yangbo Lu authored
      This patch is to add hwaccel clocks information for ls1088a.
      Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
      Link: https://lkml.kernel.org/r/20191216100111.17122-1-yangbo.lu@nxp.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      a932872f
    • Wen He's avatar
      clk: ls1028a: Add clock driver for Display output interface · d37010a3
      Wen He authored
      Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
      as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
      integer division and range of the display output pixel clock's 27-594MHz.
      Signed-off-by: default avatarWen He <wen.he_1@nxp.com>
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Link: https://lkml.kernel.org/r/20191213083402.35678-2-wen.he_1@nxp.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      d37010a3
    • Wen He's avatar
      dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings · 87a5ffb3
      Wen He authored
      LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
      output interface. Add a YAML schema for this.
      Signed-off-by: default avatarWen He <wen.he_1@nxp.com>
      Signed-off-by: default avatarMichael Walle <michael@walle.cc>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Link: https://lkml.kernel.org/r/20191213083402.35678-1-wen.he_1@nxp.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      87a5ffb3
  3. 28 Jan, 2020 6 commits
  4. 27 Jan, 2020 1 commit
  5. 23 Jan, 2020 6 commits
  6. 22 Jan, 2020 3 commits
    • Stephen Boyd's avatar
      Merge tag 'ti-clk-for-5.6' of... · 660b94e0
      Stephen Boyd authored
      Merge tag 'ti-clk-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti
      
      Pull TI clk driver updates from Tero Kristo:
      
       - cam, vpe and sgx clock support for dra7
       - fix gmac main clock for dra7
       - aess clock support for omap5
       - move dra7-atl clock header to correct location
       - fix hidden node name dependency on clkctrl clocks
      
      * tag 'ti-clk-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
        clk: ti: clkctrl: Fix hidden dependency to node name
        clk: ti: add clkctrl data dra7 sgx
        clk: ti: omap5: Add missing AESS clock
        clk: ti: dra7: fix parent for gmac_clkctrl
        clk: ti: dra7: add vpe clkctrl data
        clk: ti: dra7: add cam clkctrl data
        dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
      660b94e0
    • Stephen Boyd's avatar
      Merge tag 'imx-clk-5.6' of... · 498e1652
      Stephen Boyd authored
      Merge tag 'imx-clk-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
      
      Pull i.MX clk driver updates from Shawn Guo:
      
       - A series from Abel Vesa to do some trivial cleanups which will be
         helpful for i.MX clock driver switching to clk_hw based API
       - A series from Anson Huang to add i.MX8MP clock driver support
       - Disable non-functional divider between pll4_audio_div and
         pll4_post_div on imx6q
       - Fix watchdog2 clock name typo in imx7ulp clock driver
       - A couple of patches from Leonard Crestez to set CLK_GET_RATE_NOCACHE
         flag for DRAM related clocks on i.MX8M SoCs
       - Suppress bind attrs for i.MX8M clock driver to avoid the possibility
         of reloading the driver at runtime
       - Add a big comment in imx8qxp-lpcg driver to tell why
         devm_platform_ioremap_resource() shouldn't be used for the driver
       - A correction on i.MX8MN usb1_ctrl parent clock setting
       - A couple of trivial cleanup on clk-divider-gate driver
       - A series from Peng Fan to convert i.MX8M clock drivers to clk_hw
         based API
      
      * tag 'imx-clk-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (32 commits)
        clk: imx: Add support for i.MX8MP clock driver
        dt-bindings: imx: Add clock binding doc for i.MX8MP
        clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
        clk: imx: imx8mq: Switch to clk_hw based API
        clk: imx: imx8mm: Switch to clk_hw based API
        clk: imx: imx8mn: Switch to clk_hw based API
        clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
        clk: imx: gate3: Switch to clk_hw based API
        clk: imx: add hw API imx_clk_hw_mux2_flags
        clk: imx: add imx_unregister_hw_clocks
        clk: imx: clk-composite-8m: Switch to clk_hw based API
        clk: imx: clk-pll14xx: Switch to clk_hw based API
        clk: imx7up: Rename the clks to hws
        clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
        clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
        clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
        clk: imx: Rename sccg and frac pll register to suggest clk_hw
        clk: imx: imx7ulp composite: Rename to show is clk_hw based
        clk: imx: pllv2: Switch to clk_hw based API
        clk: imx: pllv1: Switch to clk_hw based API
        ...
      498e1652
    • Stephen Boyd's avatar
      Merge tag 'sunxi-clk-for-5.6' of... · fa9ae305
      Stephen Boyd authored
      Merge tag 'sunxi-clk-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
      
      Pull Allwinner clk driver updates from Maxime Ripard:
      
      Our usual set of patches for sunxi, with a bunch of them required to
      enable the MBUS controller, and two patches to enable cpufreq on the
      A64.
      
      * tag 'sunxi-clk-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
        clk: sunxi: a23/a33: Export the MIPI PLL
        clk: sunxi: a31: Export the MIPI PLL
        clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
        clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
        clk: sunxi-ng: r40: Export MBUS clock
        clk: sunxi: use of_device_get_match_data
      fa9ae305
  7. 20 Jan, 2020 7 commits
  8. 17 Jan, 2020 1 commit
    • Stephen Boyd's avatar
      Merge tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic · 31ef0917
      Stephen Boyd authored
      Pull Amlogic clk driver updates from Jerome Brunet:
      
       - Add meson8b DDR clock controller
       - Add input clocks to meson8b controllers
       - Fix meson8b mali clock update using the glitch free mux
       - Fix pll driver division by zero init
      
      * tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson:
        clk: clarify that clk_set_rate() does updates from top to bottom
        clk: meson: meson8b: make the CCF use the glitch-free mali mux
        clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
        clk: meson: g12a: fix missing uart2 in regmap table
        clk: meson: meson8b: use of_clk_hw_register to register the clocks
        clk: meson: meson8b: don't register the XTAL clock when provided via OF
        clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
        clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
        clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
        dt-bindings: clock: meson8b: add the clock inputs
        dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
      31ef0917
  9. 12 Jan, 2020 3 commits
  10. 10 Jan, 2020 4 commits