- 14 Dec, 2018 11 commits
-
-
Stephen Boyd authored
Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next * clk-renesas: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock clk: renesas: Mark rza2_cpg_clk_register static clk: renesas: r7s9210: Add USB clocks clk: renesas: r8a77970: Add RPC clocks clk: renesas: r7s9210: Add SDHI clocks * clk-allwinner: clk: sunxi-ng: a64: Allow parent change for VE clock clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock * clk-tegra: clk: tegra: Return the exact clock rate from clk_round_rate clk: tegra30: Use Tegra CPU powergate helper function soc/tegra: pmc: Drop SMP dependency from CPU APIs clk: tegra: Fix maximum audio sync clock for Tegra124/210 clk: tegra: get rid of duplicate defines clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC clk: tegra20: Turn EMC clock gate into divider * clk-meson: (25 commits) clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: Mark some things static clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon ... * clk-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
-
Stephen Boyd authored
Merge branches 'clk-managed-registration', 'clk-spdx', 'clk-remove-basic' and 'clk-ops-const' into clk-next - Make devm_of_clk_add_hw_provider() use parent dt node if necessary - Various SPDX taggings - Mark clk_ops const when possible * clk-managed-registration: clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock clk: apcs-msm8916: simplify probe cleanup by using devm clk: clk-twl6040: Free of_provider at remove clk: rk808: use managed version of of_provider registration clk: clk-hi655x: Free of_provider at remove clk: of-provider: look at parent if registered device has no provider info clk: Add kerneldoc to managed of-provider interfaces * clk-spdx: clk: Tag basic clk types with SPDX clk: Tag clk core files with SPDX clk: bcm2835: Switch to SPDX identifier * clk-remove-basic: clk: Loongson1: Remove usage of CLK_IS_BASIC clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC clk: versatile: sp810: Remove usage of CLK_IS_BASIC clk: hisilicon: Remove usage of CLK_IS_BASIC clk: h8300: Remove usage of CLK_IS_BASIC clk: axm5516: Remove usage of CLK_IS_BASIC clk: st: Remove usage of CLK_IS_BASIC clk: renesas: Remove usage of CLK_IS_BASIC * clk-ops-const: clk: s2mps11: constify clk_ops structure clk: pxa: constify clk_ops structures clk: pistachio: constify clk_ops structures clk: palmas: constify clk_ops structure clk: max77686: constify clk_ops structure
-
Robert Yang authored
The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API. Signed-off-by:
Robert Yang <decatf@gmail.com> Reviewed-by:
Dmitry Osipenko <digetx@gmail.com> Tested-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
-
Jon Hunter authored
Rather than using the tegra_powergate_is_powered() function for determining if a CPU is powered, use the tegra_pmc_cpu_is_powered() instead which was created to get the CPU power status. Internally tegra_pmc_cpu_is_powered() calls tegra_powergate_is_powered() and so is equivalent. The Tegra30 clock driver is the only public user of tegra_powergate_is_powered() and so by updating the Tegra30 clock driver to use tegra_pmc_cpu_is_powered(), we can then make tegra_powergate_is_powered() a non-public function. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
-
Jon Hunter authored
When CONFIG_SMP is disabled, the tegra clk driver now fails to build: drivers/clk/tegra/clk-tegra30.c: In function ‘tegra30_cpu_rail_off_ready’: drivers/clk/tegra/clk-tegra30.c:1151:2: error: implicit declaration of function ‘tegra_pmc_cpu_is_powered’ [-Werror=implicit-function-declaration] cpu_pwr_status = tegra_pmc_cpu_is_powered(1) || ^ Fix the above error by removing the CONFIG_SMP ifdef around the declaration around the PMC CPU APIs because although these are not needed for non-SMP configurations, there is no harm in including these for non-SMP builds either. Fixes: 61866523ed6e ("clk: tegra30: Use Tegra CPU powergate helper function") Reported-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
-
Jon Hunter authored
The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by:
-
Marcel Ziswiler authored
Get rid of 3 duplicate defines. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by:
-
Stephen Boyd authored
- Qualcomm SDM845 audio subsystem clks * clk-qcom-sdm845-lpass: clk: qcom: Add lpass clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM LPASS clock bindings dt-bindings: clock: Update GCC bindings for protected-clocks
-
Stephen Boyd authored
Merge branches 'clk-qcom-kconfig', 'clk-qcom-gpucc', 'clk-qcom-qcs404-rpm', 'clk-qcom-spi' and 'clk-qcom-videocc-binding' into clk-next - Qualcomm SDM845 GPU clock controllers - Qualcomm QCS404 RPM clk support * clk-qcom-kconfig: clk: qcom: Move to menuconfig and reduce lines * clk-qcom-gpucc: dt-bindings: clock: qcom: Fix the xo parent in gpucc example clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6 clk: qcom: Add a dummy enable function for GX gdsc clk: qcom: gdsc: Don't override existing gdsc pd functions clk: qcom: Add graphics clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Graphics clock bindings * clk-qcom-qcs404-rpm: clk: qcom: smd: Add support for QCS404 rpm clocks * clk-qcom-spi: clk: qcom: msm8916: Additional clock rates for spi * clk-qcom-videocc-binding: dt-bindings: clock: Require #reset-cells in sdm845-videocc
-
Stephen Boyd authored
Merge branches 'clk-qoriq-t1023', 'clk-protected-binding', 'clk-define-show-macro' and 'clk-static' into clk-next - NXP QorIQ T1023 SoC support - Introduce a 'protected-clocks' binding for firmware protected clks - Shrink code some with DEFINE_SHOW_ATTRIBUTE() * clk-qoriq-t1023: clk: qoriq: add more chips support * clk-protected-binding: clk: qcom: Support 'protected-clocks' property dt-bindings: clk: Introduce 'protected-clocks' property * clk-define-show-macro: clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro clk: nomadik: Change to use DEFINE_SHOW_ATTRIBUTE macro * clk-static: clk: stm32mp1: drop pointless static qualifier in stm32_register_hw_clk()
-
Stephen Boyd authored
- Mediatek MT7629 SoC clk controllers * clk-bcm-module-license: clk: bcm2835: make license text and module license match * clk-boston-leak: clk: boston: unregister clks on failure in clk_boston_setup() clk: boston: fix possible memory leak in clk_boston_setup() * clk-mtk-mt7629: clk: mediatek: fix the PCIe MAC clock parent clk: mediatek: Drop more __init markings for driver probe clk: mediatek: Drop __init from mtk_clk_register_cpumuxes() dt-bindings: arm: mediatek: document clk bindings for MT7629 clk: mediatek: add clock support for MT7629 SoC
-
- 13 Dec, 2018 2 commits
-
-
Stephen Boyd authored
Merge tag 'v4.21-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull rockchip clk driver updates from Heiko Stuebner: - register fixes for rk3188 and rk3328 - one new critical clock for rk3188 and a fixed clock id (double used number) - new clock id for rk3328 * tag 'v4.21-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
-
https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull more meson clk driver updates from Neil Armstrong: - Fix GXL HDMI Pll fractional bits (from first round) - Add the Meson8/Meson8b video clocks - Add clk-input helper and use it for axg-audio clock driver * tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson: clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width
-
- 11 Dec, 2018 3 commits
-
-
Stephen Boyd authored
These are all GPL-2.0 files per the existing license text. Replace the boiler plate with the tag. Signed-off-by: -
Stephen Boyd authored
These are all GPL-2.0 files per the existing license text. Replace the boiler plate with the tag. Signed-off-by: -
Jerome Brunet authored
Rework the axg audio clock controller to use the new clk-input helper function. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
-
- 10 Dec, 2018 11 commits
-
-
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in the clk init structure and then never tested again. Remove it from this driver as it doesn't provide any benefit. Also remove parenthesis nearby that are not needed and include clk.h to fix a sparse warning about static function definition. Signed-off-by: -
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in the clk init structure and then never tested again. Remove it from this drivers as it doesn't provide any benefit. Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
-
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in the clk init structure and then never tested again. Remove it from this driver as it doesn't provide any benefit. Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
-
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Jiancheng Xue <xuejiancheng@hisilicon.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Jianguo Sun <sunjianguo1@huawei.com> Cc: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: -
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Anders Berg <anders.berg@lsi.com> Signed-off-by: -
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Signed-off-by: -
Stephen Boyd authored
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: <linux-renesas-soc@vger.kernel.org> Signed-off-by:
-
Matti Vaittinen authored
ROHM bd71837 and bd71847 contain 32768Hz clock gate. Support the clock using generic clock framework. Note, only bd71837 is tested but bd71847 should be identical what comes to clk parts. Signed-off-by:
Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by:
-
Stephen Boyd authored
We duplicate the 'depends on' in almost every Kconfig here, and it's getting out of hand now that we have tens of options for various SoC drivers here. Let's clean it up a little by making a menuconfig for a submenu and adding an if wrapper around the driver section. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: -
Jernej Skrabec authored
Cedrus driver wants to set VE clock higher than it's possible without changing parent rate. Allow changing parent rate for VE clock, so clock rate can be set freely. Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
-
- 07 Dec, 2018 5 commits
-
-
Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes from Maxime Ripard: - Sigma Delta modulation for the A33 audio clocks - Support for the F1c100s SoC - Rework of the oscillator tree - H6 display engine clocks * tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for CPEX (timer) clocks on various R-Car Gen3 and RZ/G2 SoCs - Add support for SDHI HS400 clocks on early revisions of R-Car H3 and M3-W - Miscellaneous fixes based on the Hardware Manual Errata * tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock
-
Niklas Söderlund authored
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400 needs a quirk to function properly. The reason for the quirk is that there are two settings which produces same divider value for the SDn clock. On the effected boards the one currently selected results in HS400 not working. This change uses the same method as the Gen2 CPG driver and simply ignores the first clock setting as this is the offending one when selecting the settings. Which of the two possible settings is used have no effect for SDR104. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
-
Niklas Söderlund authored
Document the known use cases of the different clock settings. This is useful as different SoC and ES versions use different settings to do the same thing as there is more than one combination to achieve the same SDn clock speed. Signed-off-by:
-
Niklas Söderlund authored
The driver tries to figure out which state a SD clock is in when the clock is registered, instead of setting a known state. This can be problematic for two reasons. 1. If the clock driver can't figure out the state of the clock, registration of the clock fails, and setting of a known state by a clock user is not possible. 2. The state of the clock depends on if and how the bootloader configured it. The driver only checks that the rate is known, not if the clock is stopped or not for example. Fix this by setting a known state and making sure the clock is stopped. Signed-off-by:
-
- 05 Dec, 2018 8 commits
-
-
Ryder Lee authored
The PCIe function doesn't work as the clock tree of MAC layer is wrong. Hence fix the clock table. Fixes: 3b5e7486 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Signed-off-by:
-
Matti Vaittinen authored
use devm variant for of_provider registration. Signed-off-by:
-
Matti Vaittinen authored
use devm variant for of_provider registration so provider is freed at exit. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
-
Matti Vaittinen authored
Simplify clean-up for rk808 by using managed version of of_provider registration. Signed-off-by:
-
Matti Vaittinen authored
use devm variant for of_provider registration so provider is freed at exit. Signed-off-by:
-
Matti Vaittinen authored
It seems to be usual for MFD devices that the created 'clock sub-device' do not have own DT node. The clock provider information is usually in the main device node which is owned by the MFD device. Change the devm variant of clk of-provider registration to check the parent device node if given device has no own node or if the node does not contain the #clock-cells property. In such case use the parent node if it contains the #clock-cells. Signed-off-by:
-
Chen-Yu Tsai authored
All the audio interfaces on Allwinner SoCs need to change their module clocks during operation, to switch between support for 44.1 kHz and 48 kHz family sample rates. The clock rate for the module clocks is governed by their upstream audio PLL. The module clocks themselves only have a gate, and sometimes a divider or mux. Thus any rate changes need to be propagated upstream. Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve this. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
-
Chen-Yu Tsai authored
The audio blocks require specific clock rates. Until now we were using the closest clock rate possible with integer N-M factors. This resulted in audio playback being slightly slower than it should be. The vendor kernel gets around this (for newer SoCs) by using sigma-delta modulation to generate a fractional-N factor. As the PLL hardware is identical in most chips, we can back port the settings from the newer SoC, in this case the H3, onto the A33. Signed-off-by:
-
