Release version 4.3

1. Suppress U7x,U7xb (old RF switch) totally on PCB.
2. Split Pwr_1 Schematic into Pwr_1 and Pwr_2 to fit A4 format.
3. Add C40x and C40xb to split Net between filter F3B38 and F4B4243.

CHANGES.md

+2023-02-06 (v4.3)
+-----------------
+
+ * Suppress U7x,U7xb (old RF switch) totally on PCB.
+ * Split Pwr_1 Schematic into Pwr_1 and Pwr_2 to fit A4 format.
+ * Add C40x and C40xb to split Net between filter F3B38 and F4B4243.
+
 2022-12-01 (v4.2)
 -----------------
 

README.md

@@ -38,6 +38,7 @@ In order to do a full functional product, you will need all those components:
      * `NC Drill`: text file for drilling
      * `Pick Place`: text files for pick and place
      * `Schematic Print`: PDF version of the schematic
+   * `Exported_Ors.Net`: netlist file
  * `MiniPCIexpressCard`: Altium sources files and project files for miniPCIe adaptator PCB
    * `Project Outputs for MiniPciExpressCard`: directory containing all the output of Altium (same orgabisation as above)
  * `tools`: directory containing useful tools

hardOrs/Ors.PrjPcbStructure

@@ -4,5 +4,7 @@ Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=
 Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=root|SchDesignator=root|FileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|SymbolType=Normal|RawFileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=Ors_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=Ors_Supply_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=Ors_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 

hardOrs/Project Outputs for Ors/Design Rule Check - Ors.drc

 Protel Design System Design Rule Check
-PCB File : V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrs\Ors.PcbDoc
-Date     : 14/12/2022
-Time     : 17:33:35
+PCB File : Z:\ors-hardware\hardOrs\Ors.PcbDoc
+Date     : 2/6/2023
+Time     : 4:52:43 PM
 
-Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
-Rule Violations :0
-
-Processing Rule : Room Ors_Pwr_1 (Bounding Region = (220.507mm, 153mm, 318.257mm, 252.5mm) (InComponentClass('Ors_Pwr_1'))
+Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
+Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
 Rule Violations :0
 
-Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
+Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
 Rule Violations :0
 
-Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
+Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR  InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
 Rule Violations :0
 
-Processing Rule : Room b (Bounding Region = (205.744mm, 158.959mm, 251.937mm, 234.499mm) (InComponentClass('b'))
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
+Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
 Rule Violations :0
 
-Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
 Rule Violations :0
 
-Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
+Processing Rule : Un-Routed Net Constraint ( (All) )
 Rule Violations :0
 
-Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
+Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
 Rule Violations :0
 
-Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
+Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
 Rule Violations :0
 
-Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
 Rule Violations :0
 
 Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
 Rule Violations :0
 
-Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
-Rule Violations :0
-
-Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
+Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
 Rule Violations :0
 
-Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
+Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
 Rule Violations :0
 
-Processing Rule : Un-Routed Net Constraint ( (All) )
+Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
 Rule Violations :0
 
-Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
+Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
+Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
+Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR  InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR
-InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
+Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
+Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
+Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
+Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
 Rule Violations :0
 
 
 Violations Detected : 0
-Time Elapsed        : 00:02:04
+Time Elapsed        : 00:01:34
\ No newline at end of file

hardOrs/Project Outputs for Ors/Gerber/Gerber Files.EXTREP

 ------------------------------------------------------------------------------------------
-Gerber File Extension Report For: Gerber Files.GBR   14/12/2022  17:36:38
+Gerber File Extension Report For: Gerber Files.GBR   2/6/2023  4:55:20 PM
 ------------------------------------------------------------------------------------------
 
 

hardOrs/Project Outputs for Ors/Gerber/Gerber Files.RUL

-DRC Rules Export File for PCB: V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrs\Ors.PcbDoc
-RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
-RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
-RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
-RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
-RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
-RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
-RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
-RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
-RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
-RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
-RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
-RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
-RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
+DRC Rules Export File for PCB: Z:\ors-hardware\hardOrs\Ors.PcbDoc
 RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
+RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
+RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
+RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
+RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
+RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
+RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
+RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
+RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
+RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
+RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
+RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
+RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72

hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files.DRR

 ---------------------------------------------------------------------------
-NCDrill File Report For: Ors.PcbDoc   14/12/2022  17:36:51
+NCDrill File Report For: Ors.PcbDoc   2/6/2023  4:55:28 PM
 ---------------------------------------------------------------------------
 
 Layer Pair : TOP to BOTTOM
@@ -8,14 +8,14 @@ ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
 
 Tool         Hole Size           Hole Type     Hole Count Plated       Tool Travel
 ---------------------------------------------------------------------------
-T1        0.2mm (7.874mil)         Round          2492             4572.27 mm (180.01 Inch)
-T2        0.25mm (9.842mil)        Round          1803             4551.89 mm (179.21 Inch)
-T3        0.3mm (11.811mil)        Round          224              991.63 mm (39.04 Inch)
-T4        0.5mm (19.685mil)        Round          34               306.23 mm (12.06 Inch)
+T1        0.2mm (7.874mil)         Round          2457             4581.94 mm (180.39 Inch)
+T2        0.25mm (9.842mil)        Round          1800             4540.97 mm (178.78 Inch)
+T3        0.3mm (11.811mil)        Round          224              931.28 mm (36.66 Inch)
+T4        0.5mm (19.685mil)        Round          34               313.99 mm (12.36 Inch)
 T5        2.6mm (102.362mil)       Round          17               650.39 mm (25.61 Inch)
 T6        3.25mm (127.953mil)      Round          4                35.10 mm (1.38 Inch)
 T7        1mm (39.37mil)           Round          8         NPTH   301.02 mm (11.85 Inch)
 ---------------------------------------------------------------------------
-Totals                                            4582             11408.54 mm (449.16 Inch)
+Totals                                            4544             11354.70 mm (447.04 Inch)
 
 Total Processing Time (hh:mm:ss) : 00:00:01

hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files.LDP

-Layer Pairs Export File for PCB: V:\Work\Projets\RapidSpaceLocal\ors-hardware\hardOrs\Ors.PcbDoc
+Layer Pairs Export File for PCB: Z:\ors-hardware\hardOrs\Ors.PcbDoc
 LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
 LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl