Version from 2020-08-06 (v3.2)

CHANGES.md

+2020-08-06 (v3.2)
+-----------------
+
+ * add the possibility of mounting a temperature compensated oscillator to avoid synchronization by GPS
+ * GPS module has changed to the ublox NEOM8
+ * decoupling capacitors have been added on 1.3V and 2.5V power supplys
+ * FT232HQ decoupling changed by modifying ferrite beads reference
+ * the board shape changes and another mounting hole is added
+
 2019-01-15 (v3.1)
 -----------------
 

LowPwrLTE/LowPwrLTE.OutJob

@@ -22,7 +22,7 @@ VariantName=[No Variations]
 VariantScope=0
 CurrentConfigurationName=
 TargetPrinter=Brother MFC-660CN
-PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=0
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
 OutputMedium1=Print Job
 OutputMedium1_Type=Printer
 OutputMedium1_Printer=Brother MFC-660CN
@@ -43,7 +43,7 @@ OutputMedium7_Printer=PDFCreator
 OutputMedium7_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
 OutputMedium8=Assembly
 OutputMedium8_Type=Publish
-OutputMedium9=New PDF
+OutputMedium9=Print schematis
 OutputMedium9_Type=Publish
 OutputType1=NC Drill
 OutputName1=NC Drill Files
@@ -80,7 +80,7 @@ OutputEnabled2_OutputMedium8=0
 OutputEnabled2_OutputMedium9=0
 OutputDefault2=0
 Configuration2_Name1=OutputConfigurationParameter1
-Configuration2_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16908301~1|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=True|NumberOfDecimals=3|OptimizeChangeLocationCommands=True|OriginPosition=Absolute|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16777220~1,16777221~1,16777222~1,16777223~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908290~1,16908291~1,16908301~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=True|Sorted=False
+Configuration2_Item1=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16908301~1|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=True|NumberOfDecimals=3|OptimizeChangeLocationCommands=True|OriginPosition=Absolute|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16777220~1,16777221~1,16777222~1,16777223~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908290~1,16908291~1,16908301~1,16908319~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=True|Sorted=False
 OutputType3=BOM_PartType
 OutputName3=Bom
 OutputCategory3=Report
@@ -402,7 +402,7 @@ OutputEnabled14_OutputMedium5=0
 OutputEnabled14_OutputMedium6=0
 OutputEnabled14_OutputMedium7=0
 OutputEnabled14_OutputMedium8=0
-OutputEnabled14_OutputMedium9=2
+OutputEnabled14_OutputMedium9=1
 OutputDefault14=0
 PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-2|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
 Configuration14_Name1=OutputConfigurationParameter1
@@ -421,7 +421,7 @@ OutputEnabled15_OutputMedium5=0
 OutputEnabled15_OutputMedium6=0
 OutputEnabled15_OutputMedium7=0
 OutputEnabled15_OutputMedium8=0
-OutputEnabled15_OutputMedium9=1
+OutputEnabled15_OutputMedium9=2
 OutputDefault15=0
 PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-2|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
 Configuration15_Name1=OutputConfigurationParameter1
@@ -478,7 +478,7 @@ FFmpegPixelFormat3=0
 FFmpegQuality3=80
 WmvVideoCodecName3=Windows Media Video V7
 WmvQuality3=60
-OutputFilePath4=V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\Project Outputs for LowPwrLTE\
+OutputFilePath4=V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE_V32_30072020\Project Outputs for LowPwrLTE\
 ReleaseManaged4=1
 OutputBasePath4=Project Outputs for LowPwrLTE
 OutputPathMedia4=
@@ -580,7 +580,7 @@ OpenIPCOutput2=0
 EnableReload2=0
 RelativeOutputPath3=C:\NewProj\UmTRX\UmSEL\UmSELv2\Project Outputs\UmTRXv2_RxSel.wmv
 OpenOutputs3=1
-RelativeOutputPath4=V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\Project Outputs for LowPwrLTE\
+RelativeOutputPath4=V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE_V32_30072020\Project Outputs for LowPwrLTE\
 OpenOutputs4=0
 AddToProject4=0
 TimestampFolder4=0

LowPwrLTE/Project Outputs for LowPwrLTE/Design Rule Check - LowPwrLTE.drc

 Protel Design System Design Rule Check
 PCB File : V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
-Date     : 15/01/2019
-Time     : 10:53:20
+Date     : 29/07/2020
+Time     : 17:43:27
 
 Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
 Rule Violations :0
@@ -54,9 +54,6 @@ Rule Violations :0
 Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.22mm) (InPolyGon),(All)
-Rule Violations :0
-
 Processing Rule : Un-Routed Net Constraint ( (All) )
 Rule Violations :0
 
@@ -66,10 +63,10 @@ Rule Violations :0
 Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
+Processing Rule : Clearance Constraint (Gap=0.25mm) (IsVia AND InNet('+12VMA')),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet')),(All)
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet') OR InNamedPolygon('L6_NoNet2')),(All)
 Rule Violations :0
 
 Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
@@ -78,6 +75,15 @@ Rule Violations :0
 Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR  InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')),(All)
 Rule Violations :0
 
+Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
+Rule Violations :0
+
 
 Violations Detected : 0
-Time Elapsed        : 00:00:17
+Time Elapsed        : 00:01:10
\ No newline at end of file

LowPwrLTE/Project Outputs for LowPwrLTE/Gerber/Gerber Files.EXTREP

 ------------------------------------------------------------------------------------------
-Gerber File Extension Report For: Gerber Files.GBR   15/01/2019  10:54:29
+Gerber File Extension Report For: Gerber Files.GBR   06/08/2020  14:14:33
 ------------------------------------------------------------------------------------------
 
 
@@ -23,6 +23,6 @@ Layer Extension     Layer Description
 .GM1                Mechanical 1                            
 .GM2                Mechanical 2                            
 .GM3                Mechanical 3                            
-.GM5                BLINDAGE                                
 .GM13               DIMENSION                               
+.GM31               PCBEDGE_V4                              
 ------------------------------------------------------------------------------------------

LowPwrLTE/Project Outputs for LowPwrLTE/Gerber/Gerber Files.RUL

-DRC Rules Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
-RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
-RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
-RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
-RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
-RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
-RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
-RuleKind=Clearance|RuleName=PolyGon Pour Clearance|Scope=Board|Minimum=8.66
-RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
-RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
-RuleKind=Clearance|RuleName=Clearance-Via|Scope=Board|Minimum=4.72
-RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
-RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
+DRC Rules Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE_V32_30072020\LowPwrLTE.PcbDoc
+RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
+RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
+RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
 RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
+RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
+RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
+RuleKind=Clearance|RuleName=Clearance-Via-12V|Scope=Board|Minimum=9.84
+RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
+RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
+RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
+RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
+RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
+RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
+RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files.DRR

 ---------------------------------------------------------------------------
-NCDrill File Report For: LowPwrLTE.PcbDoc   15/01/2019  10:54:37
+NCDrill File Report For: LowPwrLTE.PcbDoc   06/08/2020  14:14:41
 ---------------------------------------------------------------------------
 
 Layer Pair : TOP to BOTTOM
@@ -8,15 +8,15 @@ ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
 
 Tool         Hole Size           Hole Type     Hole Count Plated       Tool Travel
 ---------------------------------------------------------------------------
-T1        0.2mm (7.874mil)         Round          2305             4866.67 mm (191.60 Inch)
-T2        0.25mm (9.842mil)        Round          1712             3589.83 mm (141.33 Inch)
-T3        0.3mm (11.811mil)        Round          246              1178.40 mm (46.39 Inch)
-T4        0.5mm (19.685mil)        Round          34               298.49 mm (11.75 Inch)
+T1        0.2mm (7.874mil)         Round          2378             5229.02 mm (205.87 Inch)
+T2        0.25mm (9.842mil)        Round          1775             3841.07 mm (151.22 Inch)
+T3        0.3mm (11.811mil)        Round          247              1148.86 mm (45.23 Inch)
+T4        0.5mm (19.685mil)        Round          34               301.81 mm (11.88 Inch)
 T5        1mm (39.37mil)           Round          2                13.70 mm (0.54 Inch)
-T6        2.6mm (102.362mil)       Round          16               609.54 mm (24.00 Inch)
-T7        3.25mm (127.953mil)      Round          4                34.71 mm (1.37 Inch)
+T6        2.6mm (102.362mil)       Round          17               645.59 mm (25.42 Inch)
+T7        3.25mm (127.953mil)      Round          2                12.70 mm (0.50 Inch)
 T8        1mm (39.37mil)           Round          8         NPTH   310.10 mm (12.21 Inch)
 ---------------------------------------------------------------------------
-Totals                                            4327             10901.44 mm (429.19 Inch)
+Totals                                            4463             11502.85 mm (452.87 Inch)
 
-Total Processing Time (hh:mm:ss) : 00:00:01
+Total Processing Time (hh:mm:ss) : 00:00:02

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files.LDP

-Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
+Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE_V32_30072020\LowPwrLTE.PcbDoc
 LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
 LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl

LowPwrLTE/Project Outputs for LowPwrLTE/Status Report.Txt

-Output: PickPlacceLowPwrLTE-Filter
-Type  : Pick Place
-From  : Variant [LowPwrLTE-Filter] of PCB Document [LowPwrLTE.PcbDoc]
-   Generated File[Pick Place for LowPwrLTE(LowPwrLTE-Filter).txt]
+Output: NC Drill Files
+Type  : NC Drill
+From  : PCB Document [LowPwrLTE.PcbDoc]
+   Generated File[NC Drill Files-Plated.TXT]
+   Generated File[NC Drill Files-NonPlated.TXT]
+   Generated File[NC Drill Files.LDP]
+   Generated File[NC Drill Files.DRR]
 
 
-Files Generated   : 1
+Files Generated   : 4
 Documents Printed : 0
 
-Finished Output Generation At 10:57:33 On 15/01/2019
+Finished Output Generation At 14:14:43 On 06/08/2020

README.md

@@ -16,8 +16,10 @@ The sources are under "CERN Open Hardware Licence Version 2 - Weakly Reciprocal"
      * `Assembly`: the PDF showing the places of the components (top and bottom)
      * `BOM`: the BOM (in ODS format) for each version of the board
      * `Gerber`: Gerber files for all the layers
+     * `MecaSoleBottomCase`: SolidWorks files for the sole case (the aluminium case is adjusted to the PCB)
      * `NC Drill`: text file for drilling
      * `Pick Place`: text files for pick and place
+     * `Pictures`: 3D preview of the PCB
      * `Schematic Print`: PDF version of the schematic
 
 ## FAQ