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Commit cdde2332 authored by Yuanxiang PAN's avatar Yuanxiang PAN Committed by Thomas Gambier
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Regerate OrsTypeC v4.5 based on TypeA after Accton production modification

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hardOrsTypeC/Design Rule Check - OrsTypeC.drc deleted 100644 → 0
View file @ 0849cee2
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
Date : 04/05/2023
Time : 11:33:00
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:02:18
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hardOrsTypeC/Design Rule Check - OrsTypeC.html deleted 100644 → 0
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hardOrsTypeC/Exported Ors.Net deleted 100644 → 0
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hardOrsTypeC/ORS_TypeC_8Layers.OutJob
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hardOrsTypeC/OrsTypeC.PrjPcb
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hardOrsTypeC/Project Outputs for OrsTypeC/Design Rule Check - OrsTypeC.drc deleted 100644 → 0
View file @ 0849cee2
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
Date : 04/05/2023
Time : 11:40:04
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:02:18
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hardOrsTypeC/Project Outputs for OrsTypeC/Gerber/Gerber Files-macro.APR_LIB
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hardOrsTypeC/Project Outputs for OrsTypeC/Gerber/Gerber Files.EXTREP
View file @ cdde2332
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 04/05/2023 11:59:09
Gerber File Extension Report For: Gerber Files.GBR 7/25/2023 4:56:43 PM
------------------------------------------------------------------------------------------
......
hardOrsTypeC/Project Outputs for OrsTypeC/Gerber/Gerber Files.RUL
View file @ cdde2332
DRC Rules Export File for PCB: V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
DRC Rules Export File for PCB: Z:\hardOrsTypeC\OrsTypeC.PcbDoc
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
hardOrsTypeC/Project Outputs for OrsTypeC/NC Drill/NC Drill Files.DRR
View file @ cdde2332
---------------------------------------------------------------------------
NCDrill File Report For: OrsTypeC.PcbDoc 04/05/2023 11:59:23
NCDrill File Report For: OrsTypeC.PcbDoc 7/25/2023 4:56:55 PM
---------------------------------------------------------------------------
Layer Pair : TOP to BOTTOM
......@@ -8,14 +8,14 @@ ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.2mm (7.874mil) Round 2464 4600.70 mm (181.13 Inch)
T2 0.25mm (9.842mil) Round 1798 4540.06 mm (178.74 Inch)
T3 0.3mm (11.811mil) Round 224 929.30 mm (36.59 Inch)
T4 0.5mm (19.685mil) Round 34 313.99 mm (12.36 Inch)
T1 0.2mm (7.874mil) Round 2477 4624.30 mm (182.06 Inch)
T2 0.25mm (9.842mil) Round 1796 4581.54 mm (180.38 Inch)
T3 0.3mm (11.811mil) Round 224 991.63 mm (39.04 Inch)
T4 0.5mm (19.685mil) Round 34 303.82 mm (11.96 Inch)
T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch)
T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch)
T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch)
---------------------------------------------------------------------------
Totals 4549 11370.57 mm (447.66 Inch)
Totals 4560 11487.80 mm (452.28 Inch)
Total Processing Time (hh:mm:ss) : 00:00:02
Total Processing Time (hh:mm:ss) : 00:00:01
hardOrsTypeC/Project Outputs for OrsTypeC/NC Drill/NC Drill Files.LDP
View file @ cdde2332
Layer Pairs Export File for PCB: V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
Layer Pairs Export File for PCB: Z:\hardOrsTypeC\OrsTypeC.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
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