Version from 2022-07-21 (v4.1)

CHANGES.md

+2022-07-21 (v4.1)
+-----------------
+
+WARNING: this version has a bug in Band38, DO NOT USE.
+
+The target for this version was to improve the output power.
+
+ * remove FDD support (only supports TDD now)
+ * for each channel, use 4 amplifiers from Gpowertek (24dBm) instead of 2 from
+   Skyworks (27dBm) because Skyworks amplifier were not available anymore. This
+   keeps the output power of approximately 30dBm per channel.
+ * for each channel, the output power filter is removed and replaced by two saw
+   filters, one at the input of the RF amplifiers and the second at the input
+   of the LNA Rx amplifier. This removes the power lost in the filter.
+ * the output switch is replaced with a lower insertion loss switch. Nevertheless,
+   we keep the original switch as an option to increase the isolation between the Tx and Rx channels.
+ * input voltage range is now 24V-55V (instead of 12V-55V)
+
 2020-12-22 (v3.4)
 -----------------
 

LowPwrLTE/LowPwrLTE.Annotation

-Version V3_1
-*Added LED connector
-*Buried rx Path

LowPwrLTE/LowPwrLTE.PrjPcbStructure

-Record=TopLevelDocument|FileName=LwrPwrLteTop.SchDoc
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator= |SchDesignator= |FileName=LowPwrLTE0.SchDoc|SymbolType=Normal|RawFileName=LowPwrLTE0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator= |SchDesignator= |FileName=CtrlProg.SchDoc|SymbolType=Normal|RawFileName=CtrlProg.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator=root|SchDesignator=root|FileName=PCIERadio0.SchDoc; PCIERadio1.SchDoc; PCIERadio2.SchDoc; PCIERadio3.SchDoc; PCIERadio4.SchDoc; PCIERadio5.SchDoc; PCIERadio6.SchDoc; PCIERadio7.SchDoc; PCIERadio8.SchDoc; PCIERadio9.SchDoc;|SymbolType=Normal|RawFileName=PCIERadio0.SchDoc; PCIERadio1.SchDoc; PCIERadio2.SchDoc; PCIERadio3.SchDoc; PCIERadio4.SchDoc; PCIERadio5.SchDoc; PCIERadio6.SchDoc; PCIERadio7.SchDoc; PCIERadio8.SchDoc; PCIERadio9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=RxTxPwr_0.SchDoc|SymbolType=Normal|RawFileName=RxTxPwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=LowPwrLTE1.SchDoc|SymbolType=Normal|RawFileName=LowPwrLTE1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=RxTxPwr_0.SchDoc|Designator= |SchDesignator= |FileName=RxTxPwr_1.SchDoc|SymbolType=Normal|RawFileName=RxTxPwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|Record=SheetSymbol|SourceDocument=RxTxPwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=RxTxPwr_1.SchDoc|SymbolType=Normal|RawFileName=RxTxPwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 

LowPwrLTE/Project Outputs for LowPwrLTE/Status Report.Txt

-Output: NC Drill Files
-Type  : NC Drill
-From  : PCB Document [LowPwrLTE.PcbDoc]
-   Generated File[NC Drill Files-Plated.TXT]
-   Generated File[NC Drill Files-NonPlated.TXT]
-   Generated File[NC Drill Files.LDP]
-   Generated File[NC Drill Files.DRR]
-
-
-Files Generated   : 4
-Documents Printed : 0
-
-Finished Output Generation At 09:37:13 On 22/12/2020

hardOrs/Ors.PrjPcbStructure

+Record=TopLevelDocument|FileName=Ors_Top.SchDoc
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator= |SchDesignator= |FileName=Ors_Supply_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator= |SchDesignator= |FileName=Ors_Prog.SchDoc|SymbolType=Normal|RawFileName=Ors_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=root|SchDesignator=root|FileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|SymbolType=Normal|RawFileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=Ors_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=Ors_Supply_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 

hardOrs/Project Outputs for Ors/BOM/macroLibreOffice.bas

+sub FormatBomRapidSpace
+rem ----------------------------------------------------------------------
+rem define variables
+dim document   as object
+dim dispatcher as object
+rem ----------------------------------------------------------------------
+rem get access to the document
+document   = ThisComponent.CurrentController.Frame
+
+dispatcher = createUnoService("com.sun.star.frame.DispatchHelper")
+
+rem ajuste la largeur de la  colonne x au contenu des cellules en 1/10mm: 
+ThisComponent.Sheets(0).Columns(0).Width = 10000 rem Designator list
+ThisComponent.Sheets(0).Columns(1).Width = 3700 rem FootPrint
+ThisComponent.Sheets(0).Columns(2).Width = 4500 rem Manufacturer
+ThisComponent.Sheets(0).Columns(3).Width = 5000 rem Type
+ThisComponent.Sheets(0).Columns(4).Width = 3800 rem Value
+ThisComponent.Sheets(0).Columns(5).Width = 1800 rem Qte
+ThisComponent.Sheets(0).Columns(6).Width = 7000 rem Infos 
+
+rem ----------------------------------------------------------------------
+dispatcher.executeDispatch(document, ".uno:SelectAll", "", 0, Array())
+
+rem ----------------------------------------------------------------------
+dim args2(2) as new com.sun.star.beans.PropertyValue
+args2(0).Name = "FontHeight.Height"
+args2(0).Value = 10
+args2(1).Name = "FontHeight.Prop"
+args2(1).Value = 100
+args2(2).Name = "FontHeight.Diff"
+args2(2).Value = 0
+
+dispatcher.executeDispatch(document, ".uno:FontHeight", "", 0, args2())
+
+rem ----------------------------------------------------------------------
+dim args3(0) as new com.sun.star.beans.PropertyValue
+args3(0).Name = "WrapText"
+args3(0).Value = true
+
+dispatcher.executeDispatch(document, ".uno:WrapText", "", 0, args3())
+
+
+rem ---Figer les Volets----------------------------------------------------------
+dim args1(0) as new com.sun.star.beans.PropertyValue
+args1(0).Name = "ToPoint"
+args1(0).Value = "$B$2"
+dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args1())
+dispatcher.executeDispatch(document, ".uno:FreezePanes", "", 0, Array())
+
+
+
+
+rem ----------------------------------------------------------------------
+dim args6(0) as new com.sun.star.beans.PropertyValue
+args6(0).Name = "ToPoint"
+args6(0).Value = "$A$2"
+
+dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args6())
+
+rem ----------------------------------------------------------------------
+dim args5(0) as new com.sun.star.beans.PropertyValue
+Dim oCurrentSelection As Variant
+Dim oRows As Variant, oCols As Variant
+args5(0).Name = "Sel"
+args5(0).Value = true
+
+dispatcher.executeDispatch(document, ".uno:GoToEndOfData", "", 0, args5())
+oCurrentSelection = ThisComponent.getCurrentSelection()
+oRows = oCurrentSelection.getRows()
+oCols = oCurrentSelection.getColumns()
+
+   Dim oDocument As Object, oSheet As Object, oCell As Object
+   Dim l As Integer, pair As Integer, nbrCol As Integer,nbrRow As Integer
+   Dim strLayer As String, index As Integer, nbOccurences As Integer, oCell2 As Object 
+   oDocument = ThisComponent
+   oSheet=oDocument.Sheets.getByName ("Feuille1" )
+   pair = 0
+   nbrCol = oCols.getCount()
+   nbrRow =  oRows.getCount()
+
+rem ----diplays  Top or Bottom----------------------------------------  
+   osheet = ThisComponent.CurrentController.ActiveSheet
+   For l = 1 To nbrRow 
+   	 oCell2 = osheet.getCellByPosition(7, l)	
+   	 strLayer =  oCell2.getString()
+	 oCell2.setString("")
+	 
+	 index = InStr(strLayer, "Top")
+   	 if index > 0 then
+   	 	oCell2 = osheet.getCellByPosition(7, l)
+     	oCell2.setString("T")
+     endif  
+     
+    	index = InStr(strLayer, "Bottom")
+   	 if index > 0 then
+   	 	oCell2 = osheet.getCellByPosition(7, l)
+  	  	oCell2.setString(oCell2.getString() +"B")
+     endif
+
+
+   Next l  
+    
+   For l = 1 To nbrRow
+ 	 oCell = oSheet.getCellrangeByPosition(0,l,nbrCol-1,l)
+   		if pair = 0 then 
+ 	 		oCell.CellBackColor = RGB(245,245,245)
+ 	 		pair = 1
+ 	 	else
+			oCell.CellBackColor = RGB(250,240,230) 
+			pair = 0
+		endif		 			
+   Next l
+   
+oCell = oSheet.getCellrangeByPosition(0,0,nbrCol-1,nbrRow)  
+oCell.VERTJUSTIFY=com.sun.star.table.CellVertJustify.CENTER
+oCell.HORIJUSTIFY=com.sun.star.table.CellHoriJustify.LEFT
+
+rem Mise en form des enttes
+oCell = oSheet.getCellrangeByPosition(0,0,nbrCol-1,0)  
+oCell.CharWeight = com.sun.star.awt.FontWeight.BOLD
+oCell.HORIJUSTIFY=com.sun.star.table.CellHoriJustify.CENTER
+rem semble faire un unselect
+
+dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args5())   
+
+end sub
\ No newline at end of file

LowPwrLTE/Project Outputs for LowPwrLTE/Design Rule Check - LowPwrLTE.drc → hardOrs/Project Outputs for Ors/Design Rule Check - Ors.drc

 Protel Design System Design Rule Check
-PCB File : V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
-Date     : 22/12/2020
-Time     : 09:35:19
+PCB File : V:\Work\Projets\RapidSpaceLocal\hard\hardOrs\Ors.PcbDoc
+Date     : 21/07/2022
+Time     : 12:22:47
 
 Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
 Rule Violations :0
 
-Processing Rule : Room RxTxPwr_1 (Bounding Region = (230.75mm, 153mm, 331.75mm, 252.5mm) (InComponentClass('RxTxPwr_1'))
+Processing Rule : Room Ors_Pwr_1 (Bounding Region = (220.507mm, 153mm, 318.257mm, 252.5mm) (InComponentClass('Ors_Pwr_1'))
 Rule Violations :0
 
 Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
@@ -18,7 +18,7 @@ Rule Violations :0
 Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
 Rule Violations :0
 
-Processing Rule : Room b (Bounding Region = (205.75mm, 158mm, 269.75mm, 226mm) (InComponentClass('b'))
+Processing Rule : Room b (Bounding Region = (205.744mm, 158.959mm, 251.937mm, 234.499mm) (InComponentClass('b'))
 Rule Violations :0
 
 Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
@@ -63,10 +63,7 @@ Rule Violations :0
 Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
 Rule Violations :0
 
-Processing Rule : Clearance Constraint (Gap=0.25mm) (IsVia AND InNet('+12VMA')),(All)
-Rule Violations :0
-
-Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet') OR InNamedPolygon('L6_NoNet2')),(All)
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
 Rule Violations :0
 
 Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
@@ -86,4 +83,4 @@ Rule Violations :0
 
 
 Violations Detected : 0
-Time Elapsed        : 00:01:12
+Time Elapsed        : 00:02:04
\ No newline at end of file

LowPwrLTE/Project Outputs for LowPwrLTE/Gerber/Gerber Files.EXTREP → hardOrs/Project Outputs for Ors/Gerber/Gerber Files.EXTREP

 ------------------------------------------------------------------------------------------
-Gerber File Extension Report For: Gerber Files.GBR   22/12/2020  09:37:03
+Gerber File Extension Report For: Gerber Files.GBR   21/07/2022  14:02:47
 ------------------------------------------------------------------------------------------
 
 
@@ -23,6 +23,6 @@ Layer Extension     Layer Description
 .GM1                Mechanical 1                            
 .GM2                Mechanical 2                            
 .GM3                Mechanical 3                            
+.GM7                SOLE_EDGE-V4                            
 .GM13               DIMENSION                               
-.GM31               PCBEDGE_V4                              
 ------------------------------------------------------------------------------------------

LowPwrLTE/Project Outputs for LowPwrLTE/Gerber/Gerber Files.RUL → hardOrs/Project Outputs for Ors/Gerber/Gerber Files.RUL

-DRC Rules Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
+DRC Rules Export File for PCB: V:\Work\Projets\RapidSpaceLocal\hard\hardOrs\Ors.PcbDoc
 RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
 RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
 RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
@@ -7,7 +7,6 @@ RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.
 RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
 RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
 RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
-RuleKind=Clearance|RuleName=Clearance-Via-12V|Scope=Board|Minimum=9.84
 RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
 RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
 RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files-NonPlated.TXT → hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files-NonPlated.TXT

@@ -3,15 +3,15 @@ M48
 ;FILE_FORMAT=4:3
 METRIC,TZ
 ;TYPE=NON_PLATED
-T8F00S00C1.000
+T7F00S00C1.000
 %
-T08
-X322892Y183074
-Y187774
+T07
+X325250Y204650
+Y209350
 X242150Y269900
-X325255Y261805
-Y257105
-X325250Y249850
-Y245150
+X325255Y255805
+Y251105
+X325250Y243850
+Y239150
 X242150Y279900
 M30

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files.DRR → hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files.DRR

 ---------------------------------------------------------------------------
-NCDrill File Report For: LowPwrLTE.PcbDoc   22/12/2020  09:37:12
+NCDrill File Report For: Ors.PcbDoc   21/07/2022  14:03:00
 ---------------------------------------------------------------------------
 
 Layer Pair : TOP to BOTTOM
@@ -8,15 +8,14 @@ ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
 
 Tool         Hole Size           Hole Type     Hole Count Plated       Tool Travel
 ---------------------------------------------------------------------------
-T1        0.2mm (7.874mil)         Round          2378             5179.29 mm (203.91 Inch)
-T2        0.25mm (9.842mil)        Round          1775             3899.70 mm (153.53 Inch)
-T3        0.3mm (11.811mil)        Round          247              1180.17 mm (46.46 Inch)
-T4        0.5mm (19.685mil)        Round          34               298.49 mm (11.75 Inch)
-T5        1mm (39.37mil)           Round          2                13.70 mm (0.54 Inch)
-T6        2.6mm (102.362mil)       Round          17               645.59 mm (25.42 Inch)
-T7        3.25mm (127.953mil)      Round          2                12.70 mm (0.50 Inch)
-T8        1mm (39.37mil)           Round          8         NPTH   310.10 mm (12.21 Inch)
+T1        0.2mm (7.874mil)         Round          2492             4573.52 mm (180.06 Inch)
+T2        0.25mm (9.842mil)        Round          1803             4551.46 mm (179.19 Inch)
+T3        0.3mm (11.811mil)        Round          224              991.63 mm (39.04 Inch)
+T4        0.5mm (19.685mil)        Round          34               306.23 mm (12.06 Inch)
+T5        2.6mm (102.362mil)       Round          17               650.39 mm (25.61 Inch)
+T6        3.25mm (127.953mil)      Round          4                35.10 mm (1.38 Inch)
+T7        1mm (39.37mil)           Round          8         NPTH   301.02 mm (11.85 Inch)
 ---------------------------------------------------------------------------
-Totals                                            4463             11539.74 mm (454.32 Inch)
+Totals                                            4582             11409.36 mm (449.19 Inch)
 
-Total Processing Time (hh:mm:ss) : 00:00:01
+Total Processing Time (hh:mm:ss) : 00:00:02