Version from 2019-01-15 (v3.1)

CHANGES.md

+2019-01-15 (v3.1)
+-----------------
+
+First version of SDR PCB containing the following features:
+ * based on Amarisoft SDR board
+ * supports up to 40MHz bandwidth
+ * USB connection to access FPGA JTAG
+ * TDD/FDD support
+ * supports all bands for which Skyworks/Qorvo ampli are available
+
+This PCB was designed by Jean-Marc Ouvrard and Jean-Samuel Najnudel.

LowPwrLTE/LowPwrLTE.Annotation

+Version V3_1
+*Added LED connector
+*Buried rx Path

LowPwrLTE/LowPwrLTE.PrjPcbStructure

+Record=TopLevelDocument|FileName=LwrPwrLteTop.SchDoc
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator= |SchDesignator= |FileName=LowPwrLTE0.SchDoc|SymbolType=Normal|RawFileName=LowPwrLTE0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator= |SchDesignator= |FileName=CtrlProg.SchDoc|SymbolType=Normal|RawFileName=CtrlProg.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator=root|SchDesignator=root|FileName=PCIERadio0.SchDoc; PCIERadio1.SchDoc; PCIERadio2.SchDoc; PCIERadio3.SchDoc; PCIERadio4.SchDoc; PCIERadio5.SchDoc; PCIERadio6.SchDoc; PCIERadio7.SchDoc; PCIERadio8.SchDoc; PCIERadio9.SchDoc;|SymbolType=Normal|RawFileName=PCIERadio0.SchDoc; PCIERadio1.SchDoc; PCIERadio2.SchDoc; PCIERadio3.SchDoc; PCIERadio4.SchDoc; PCIERadio5.SchDoc; PCIERadio6.SchDoc; PCIERadio7.SchDoc; PCIERadio8.SchDoc; PCIERadio9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=RxTxPwr_0.SchDoc|SymbolType=Normal|RawFileName=RxTxPwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=LwrPwrLteTop.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=LowPwrLTE1.SchDoc|SymbolType=Normal|RawFileName=LowPwrLTE1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=RxTxPwr_0.SchDoc|Designator= |SchDesignator= |FileName=RxTxPwr_1.SchDoc|SymbolType=Normal|RawFileName=RxTxPwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=RxTxPwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=RxTxPwr_1.SchDoc|SymbolType=Normal|RawFileName=RxTxPwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 

LowPwrLTE/Project Outputs for LowPwrLTE/Design Rule Check - LowPwrLTE.drc

+Protel Design System Design Rule Check
+PCB File : V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
+Date     : 15/01/2019
+Time     : 10:53:20
+
+Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
+Rule Violations :0
+
+Processing Rule : Room RxTxPwr_1 (Bounding Region = (230.75mm, 153mm, 331.75mm, 252.5mm) (InComponentClass('RxTxPwr_1'))
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
+Rule Violations :0
+
+Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
+Rule Violations :0
+
+Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
+Rule Violations :0
+
+Processing Rule : Room b (Bounding Region = (205.75mm, 158mm, 269.75mm, 226mm) (InComponentClass('b'))
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
+Rule Violations :0
+
+Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
+Rule Violations :0
+
+Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.22mm) (InPolyGon),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NotNet') OR InNamedPolygon('L6_NotNet') OR InNamedPolygon('L4_NotNet') OR InNamedPolygon('L7_NotNet')OR InNamedPolygon('L3_NotNet')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR  InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')),(All)
+Rule Violations :0
+
+
+Violations Detected : 0
+Time Elapsed        : 00:00:17
\ No newline at end of file

LowPwrLTE/Project Outputs for LowPwrLTE/Gerber/Gerber Files.EXTREP

+------------------------------------------------------------------------------------------
+Gerber File Extension Report For: Gerber Files.GBR   15/01/2019  10:54:29
+------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------
+Layer Extension     Layer Description                      
+------------------------------------------------------------------------------------------
+.GTL                TOP                                     
+.G1                 L2                                      
+.G2                 L3                                      
+.G3                 L4                                      
+.G4                 L5                                      
+.G5                 L6                                      
+.G6                 L7                                      
+.GBL                BOTTOM                                  
+.GTO                Top Overlay                             
+.GTP                Top Paste                               
+.GTS                Top Solder                              
+.GBS                Bottom Solder                           
+.GBP                Bottom Paste                            
+.GBO                Bottom Overlay                          
+.GM1                Mechanical 1                            
+.GM2                Mechanical 2                            
+.GM3                Mechanical 3                            
+.GM5                BLINDAGE                                
+.GM13               DIMENSION                               
+------------------------------------------------------------------------------------------

LowPwrLTE/Project Outputs for LowPwrLTE/Gerber/Gerber Files.RUL

+DRC Rules Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
+RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
+RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
+RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
+RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
+RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=PolyGon Pour Clearance|Scope=Board|Minimum=8.66
+RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
+RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
+RuleKind=Clearance|RuleName=Clearance-Via|Scope=Board|Minimum=4.72
+RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
+RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
+RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files-NonPlated.TXT

+M48
+;Layer_Color=9474304
+;FILE_FORMAT=4:3
+METRIC,TZ
+;TYPE=NON_PLATED
+T8F00S00C1.000
+%
+T08
+X322892Y183074
+Y187774
+X242150Y269900
+X325255Y261805
+Y257105
+X325250Y249850
+Y245150
+X242150Y279900
+M30

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files.DRR

+---------------------------------------------------------------------------
+NCDrill File Report For: LowPwrLTE.PcbDoc   15/01/2019  10:54:37
+---------------------------------------------------------------------------
+
+Layer Pair : TOP to BOTTOM
+ASCII Plated RoundHoles File : NC Drill Files-Plated.TXT
+ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
+
+Tool         Hole Size           Hole Type     Hole Count Plated       Tool Travel
+---------------------------------------------------------------------------
+T1        0.2mm (7.874mil)         Round          2305             4866.67 mm (191.60 Inch)
+T2        0.25mm (9.842mil)        Round          1712             3589.83 mm (141.33 Inch)
+T3        0.3mm (11.811mil)        Round          246              1178.40 mm (46.39 Inch)
+T4        0.5mm (19.685mil)        Round          34               298.49 mm (11.75 Inch)
+T5        1mm (39.37mil)           Round          2                13.70 mm (0.54 Inch)
+T6        2.6mm (102.362mil)       Round          16               609.54 mm (24.00 Inch)
+T7        3.25mm (127.953mil)      Round          4                34.71 mm (1.37 Inch)
+T8        1mm (39.37mil)           Round          8         NPTH   310.10 mm (12.21 Inch)
+---------------------------------------------------------------------------
+Totals                                            4327             10901.44 mm (429.19 Inch)
+
+Total Processing Time (hh:mm:ss) : 00:00:01

LowPwrLTE/Project Outputs for LowPwrLTE/NC Drill/NC Drill Files.LDP

+Layer Pairs Export File for PCB: V:\Work\Projets\BjtPartners\LowPwrLteWork\Hard\LowPwrLTE\LowPwrLTE.PcbDoc
+LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
+LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl

LowPwrLTE/Project Outputs for LowPwrLTE/Status Report.Txt

+Output: PickPlacceLowPwrLTE-Filter
+Type  : Pick Place
+From  : Variant [LowPwrLTE-Filter] of PCB Document [LowPwrLTE.PcbDoc]
+   Generated File[Pick Place for LowPwrLTE(LowPwrLTE-Filter).txt]
+
+
+Files Generated   : 1
+Documents Printed : 0
+
+Finished Output Generation At 10:57:33 On 15/01/2019

README.md

 # ORS hardware
 
 This is the repository containing the sources for the low power radio PCB used inside the ORS.
+
+
+## Ownership
+
+All the sources belong to *Libre Endowment Fund* (*Fond de dotation du libre* in French), see https://www.fdl-lef.org/
+
+The sources are under "CERN Open Hardware Licence Version 2 - Weakly Reciprocal" license (https://ohwr.org/cern_ohl_w_v2.txt), see [LICENSE](LICENSE).
+
+## Files
+
+ * `LowPwrLTE`: directory containing the Altium sources files and project files
+   * `Project Outputs for LowPwrLTE`: directory containing all the output of Altium
+     * `Assembly`: the PDF showing the places of the components (top and bottom)
+     * `BOM`: the BOM (in ODS format) for each version of the board
+     * `Gerber`: Gerber files for all the layers
+     * `NC Drill`: text file for drilling
+     * `Pick Place`: text files for pick and place
+     * `Schematic Print`: PDF version of the schematic
+
+## FAQ
+
+ * *Why do you use Altium (proprietary software) for Open Hardware project?*
+
+The project is using Altium to design the PCB because at the beginning of the project (2016) the existing open source PCB designer were not able to handle 8 layers PCB with some constraints on impedance. The goal is to move the project to KiCad EDA (https://www.kicad.org/)