r8169_main.c 140 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
 *
 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
 * Copyright (c) a lot of people too. Please respect their work.
 *
 * See MAINTAINERS file for support contact information.
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 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/if_vlan.h>
#include <linux/in.h>
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#include <linux/io.h>
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#include <linux/ip.h>
#include <linux/tcp.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/bitfield.h>
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#include <linux/prefetch.h>
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#include <linux/ipv6.h>
#include <net/ip6_checksum.h>
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#include "r8169.h"
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#include "r8169_firmware.h"

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#define MODULENAME "r8169"

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#define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"
#define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"
#define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"
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#define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"
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#define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"
#define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
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#define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
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#define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"
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#define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"
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#define FIRMWARE_8411_2		"rtl_nic/rtl8411-2.fw"
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#define FIRMWARE_8106E_1	"rtl_nic/rtl8106e-1.fw"
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#define FIRMWARE_8106E_2	"rtl_nic/rtl8106e-2.fw"
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#define FIRMWARE_8168G_2	"rtl_nic/rtl8168g-2.fw"
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#define FIRMWARE_8168G_3	"rtl_nic/rtl8168g-3.fw"
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#define FIRMWARE_8168H_1	"rtl_nic/rtl8168h-1.fw"
#define FIRMWARE_8168H_2	"rtl_nic/rtl8168h-2.fw"
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#define FIRMWARE_8168FP_3	"rtl_nic/rtl8168fp-3.fw"
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#define FIRMWARE_8107E_1	"rtl_nic/rtl8107e-1.fw"
#define FIRMWARE_8107E_2	"rtl_nic/rtl8107e-2.fw"
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#define FIRMWARE_8125A_3	"rtl_nic/rtl8125a-3.fw"
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#define FIRMWARE_8125B_2	"rtl_nic/rtl8125b-2.fw"
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/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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#define	MC_FILTER_LIMIT	32
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#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */
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#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
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#define R8169_RX_BUF_SIZE	(SZ_16K - 1)
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#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
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#define NUM_RX_DESC	256U	/* Number of Rx descriptor registers */
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#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

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#define OCP_STD_PHY_BASE	0xa400

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#define RTL_CFG_NO_GBIT	1

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/* write/read MMIO register */
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#define RTL_W8(tp, reg, val8)	writeb((val8), tp->mmio_addr + (reg))
#define RTL_W16(tp, reg, val16)	writew((val16), tp->mmio_addr + (reg))
#define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))
#define RTL_R8(tp, reg)		readb(tp->mmio_addr + (reg))
#define RTL_R16(tp, reg)		readw(tp->mmio_addr + (reg))
#define RTL_R32(tp, reg)		readl(tp->mmio_addr + (reg))
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#define JUMBO_4K	(4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
#define JUMBO_6K	(6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
#define JUMBO_7K	(7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
#define JUMBO_9K	(9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
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static const struct {
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	const char *name;
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	const char *fw_name;
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} rtl_chip_infos[] = {
	/* PCI devices. */
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	[RTL_GIGA_MAC_VER_02] = {"RTL8169s"				},
	[RTL_GIGA_MAC_VER_03] = {"RTL8110s"				},
	[RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"			},
	[RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"			},
	[RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"			},
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	/* PCI-E devices. */
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	[RTL_GIGA_MAC_VER_07] = {"RTL8102e"				},
	[RTL_GIGA_MAC_VER_08] = {"RTL8102e"				},
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	[RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"			},
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	[RTL_GIGA_MAC_VER_10] = {"RTL8101e"				},
	[RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"			},
	[RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"			},
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	[RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"			},
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	[RTL_GIGA_MAC_VER_14] = {"RTL8401"				},
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	[RTL_GIGA_MAC_VER_16] = {"RTL8101e"				},
	[RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"			},
	[RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"			},
	[RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"			},
	[RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"			},
	[RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"			},
	[RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"			},
	[RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"			},
	[RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"			},
	[RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",	FIRMWARE_8168D_1},
	[RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",	FIRMWARE_8168D_2},
	[RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"			},
	[RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"			},
	[RTL_GIGA_MAC_VER_29] = {"RTL8105e",		FIRMWARE_8105E_1},
	[RTL_GIGA_MAC_VER_30] = {"RTL8105e",		FIRMWARE_8105E_1},
	[RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"			},
	[RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",	FIRMWARE_8168E_1},
	[RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",	FIRMWARE_8168E_2},
	[RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",	FIRMWARE_8168E_3},
	[RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",	FIRMWARE_8168F_1},
	[RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",	FIRMWARE_8168F_2},
	[RTL_GIGA_MAC_VER_37] = {"RTL8402",		FIRMWARE_8402_1 },
	[RTL_GIGA_MAC_VER_38] = {"RTL8411",		FIRMWARE_8411_1 },
	[RTL_GIGA_MAC_VER_39] = {"RTL8106e",		FIRMWARE_8106E_1},
	[RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",	FIRMWARE_8168G_2},
	[RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"			},
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	[RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",	FIRMWARE_8168G_3},
	[RTL_GIGA_MAC_VER_43] = {"RTL8106eus",		FIRMWARE_8106E_2},
	[RTL_GIGA_MAC_VER_44] = {"RTL8411b",		FIRMWARE_8411_2 },
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	[RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",	FIRMWARE_8168H_1},
	[RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",	FIRMWARE_8168H_2},
	[RTL_GIGA_MAC_VER_47] = {"RTL8107e",		FIRMWARE_8107E_1},
	[RTL_GIGA_MAC_VER_48] = {"RTL8107e",		FIRMWARE_8107E_2},
	[RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"			},
	[RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"			},
	[RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"			},
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	[RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
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	[RTL_GIGA_MAC_VER_60] = {"RTL8125A"				},
	[RTL_GIGA_MAC_VER_61] = {"RTL8125A",		FIRMWARE_8125A_3},
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	/* reserve 62 for CFG_METHOD_4 in the vendor driver */
	[RTL_GIGA_MAC_VER_63] = {"RTL8125B",		FIRMWARE_8125B_2},
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};

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static const struct pci_device_id rtl8169_pci_tbl[] = {
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	{ PCI_VDEVICE(REALTEK,	0x2502) },
	{ PCI_VDEVICE(REALTEK,	0x2600) },
	{ PCI_VDEVICE(REALTEK,	0x8129) },
	{ PCI_VDEVICE(REALTEK,	0x8136), RTL_CFG_NO_GBIT },
	{ PCI_VDEVICE(REALTEK,	0x8161) },
	{ PCI_VDEVICE(REALTEK,	0x8167) },
	{ PCI_VDEVICE(REALTEK,	0x8168) },
	{ PCI_VDEVICE(NCUBE,	0x8168) },
	{ PCI_VDEVICE(REALTEK,	0x8169) },
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	{ PCI_VENDOR_ID_DLINK,	0x4300,
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		PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
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	{ PCI_VDEVICE(DLINK,	0x4300) },
	{ PCI_VDEVICE(DLINK,	0x4302) },
	{ PCI_VDEVICE(AT,	0xc107) },
	{ PCI_VDEVICE(USR,	0x0116) },
	{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
	{ 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
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	{ PCI_VDEVICE(REALTEK,	0x8125) },
	{ PCI_VDEVICE(REALTEK,	0x3000) },
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	{}
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};

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

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enum rtl_registers {
	MAC0		= 0,	/* Ethernet hardware address. */
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	MAC4		= 4,
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	MAR0		= 8,	/* Multicast filter. */
	CounterAddrLow		= 0x10,
	CounterAddrHigh		= 0x14,
	TxDescStartAddrLow	= 0x20,
	TxDescStartAddrHigh	= 0x24,
	TxHDescStartAddrLow	= 0x28,
	TxHDescStartAddrHigh	= 0x2c,
	FLASH		= 0x30,
	ERSR		= 0x36,
	ChipCmd		= 0x37,
	TxPoll		= 0x38,
	IntrMask	= 0x3c,
	IntrStatus	= 0x3e,
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	TxConfig	= 0x40,
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#define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */
#define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */
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	RxConfig	= 0x44,
#define	RX128_INT_EN			(1 << 15)	/* 8111c and later */
#define	RX_MULTI_EN			(1 << 14)	/* 8111c only */
#define	RXCFG_FIFO_SHIFT		13
					/* No threshold before first PCI xfer */
#define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)
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#define	RX_EARLY_OFF			(1 << 11)
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#define	RXCFG_DMA_SHIFT			8
					/* Unlimited maximum PCI burst. */
#define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)
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	Cfg9346		= 0x50,
	Config0		= 0x51,
	Config1		= 0x52,
	Config2		= 0x53,
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#define PME_SIGNAL			(1 << 5)	/* 8168c and later */

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	Config3		= 0x54,
	Config4		= 0x55,
	Config5		= 0x56,
	PHYAR		= 0x60,
	PHYstatus	= 0x6c,
	RxMaxSize	= 0xda,
	CPlusCmd	= 0xe0,
	IntrMitigate	= 0xe2,
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#define RTL_COALESCE_TX_USECS	GENMASK(15, 12)
#define RTL_COALESCE_TX_FRAMES	GENMASK(11, 8)
#define RTL_COALESCE_RX_USECS	GENMASK(7, 4)
#define RTL_COALESCE_RX_FRAMES	GENMASK(3, 0)

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#define RTL_COALESCE_T_MAX	0x0fU
#define RTL_COALESCE_FRAME_MAX	(RTL_COALESCE_T_MAX * 4)
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	RxDescAddrLow	= 0xe4,
	RxDescAddrHigh	= 0xe8,
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	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */

#define NoEarlyTx	0x3f	/* Max value : no early transmit. */

	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */

#define TxPacketMax	(8064 >> 7)
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#define EarlySize	0x27
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	FuncEvent	= 0xf0,
	FuncEventMask	= 0xf4,
	FuncPresetState	= 0xf8,
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	IBCR0           = 0xf8,
	IBCR2           = 0xf9,
	IBIMR0          = 0xfa,
	IBISR0          = 0xfb,
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	FuncForceEvent	= 0xfc,
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};

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enum rtl8168_8101_registers {
	CSIDR			= 0x64,
	CSIAR			= 0x68,
#define	CSIAR_FLAG			0x80000000
#define	CSIAR_WRITE_CMD			0x80000000
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#define	CSIAR_BYTE_ENABLE		0x0000f000
#define	CSIAR_ADDR_MASK			0x00000fff
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	PMCH			= 0x6f,
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	EPHYAR			= 0x80,
#define	EPHYAR_FLAG			0x80000000
#define	EPHYAR_WRITE_CMD		0x80000000
#define	EPHYAR_REG_MASK			0x1f
#define	EPHYAR_REG_SHIFT		16
#define	EPHYAR_DATA_MASK		0xffff
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	DLLPR			= 0xd0,
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#define	PFM_EN				(1 << 6)
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#define	TX_10M_PS_EN			(1 << 7)
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	DBG_REG			= 0xd1,
#define	FIX_NAK_1			(1 << 4)
#define	FIX_NAK_2			(1 << 3)
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	TWSI			= 0xd2,
	MCU			= 0xd3,
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#define	NOW_IS_OOB			(1 << 7)
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#define	TX_EMPTY			(1 << 5)
#define	RX_EMPTY			(1 << 4)
#define	RXTX_EMPTY			(TX_EMPTY | RX_EMPTY)
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#define	EN_NDP				(1 << 3)
#define	EN_OOB_RESET			(1 << 2)
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#define	LINK_LIST_RDY			(1 << 1)
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	EFUSEAR			= 0xdc,
#define	EFUSEAR_FLAG			0x80000000
#define	EFUSEAR_WRITE_CMD		0x80000000
#define	EFUSEAR_READ_CMD		0x00000000
#define	EFUSEAR_REG_MASK		0x03ff
#define	EFUSEAR_REG_SHIFT		8
#define	EFUSEAR_DATA_MASK		0xff
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	MISC_1			= 0xf2,
#define	PFM_D3COLD_EN			(1 << 6)
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};

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enum rtl8168_registers {
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	LED_FREQ		= 0x1a,
	EEE_LED			= 0x1b,
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	ERIDR			= 0x70,
	ERIAR			= 0x74,
#define ERIAR_FLAG			0x80000000
#define ERIAR_WRITE_CMD			0x80000000
#define ERIAR_READ_CMD			0x00000000
#define ERIAR_ADDR_BYTE_ALIGN		4
#define ERIAR_TYPE_SHIFT		16
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#define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)
#define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)
#define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)
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#define ERIAR_OOB			(0x02 << ERIAR_TYPE_SHIFT)
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#define ERIAR_MASK_SHIFT		12
#define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)
#define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0100			(0x4 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0101			(0x5 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)
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	EPHY_RXER_NUM		= 0x7c,
	OCPDR			= 0xb0,	/* OCP GPHY access */
#define OCPDR_WRITE_CMD			0x80000000
#define OCPDR_READ_CMD			0x00000000
#define OCPDR_REG_MASK			0x7f
#define OCPDR_GPHY_REG_SHIFT		16
#define OCPDR_DATA_MASK			0xffff
	OCPAR			= 0xb4,
#define OCPAR_FLAG			0x80000000
#define OCPAR_GPHY_WRITE_CMD		0x8000f060
#define OCPAR_GPHY_READ_CMD		0x0000f060
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	GPHY_OCP		= 0xb8,
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	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */
	MISC			= 0xf0,	/* 8168e only. */
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#define TXPLA_RST			(1 << 29)
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#define DISABLE_LAN_EN			(1 << 23) /* Enable GPIO pin */
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#define PWM_EN				(1 << 22)
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#define RXDV_GATED_EN			(1 << 19)
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#define EARLY_TALLY_EN			(1 << 16)
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};

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enum rtl8125_registers {
	IntrMask_8125		= 0x38,
	IntrStatus_8125		= 0x3c,
	TxPoll_8125		= 0x90,
	MAC0_BKP		= 0x19e0,
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	EEE_TXIDLE_TIMER_8125	= 0x6048,
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};

#define RX_VLAN_INNER_8125	BIT(22)
#define RX_VLAN_OUTER_8125	BIT(23)
#define RX_VLAN_8125		(RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)

#define RX_FETCH_DFLT_8125	(8 << 27)

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enum rtl_register_content {
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	/* InterruptStatusBits */
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	SYSErr		= 0x8000,
	PCSTimeout	= 0x4000,
	SWInt		= 0x0100,
	TxDescUnavail	= 0x0080,
	RxFIFOOver	= 0x0040,
	LinkChg		= 0x0020,
	RxOverflow	= 0x0010,
	TxErr		= 0x0008,
	TxOK		= 0x0004,
	RxErr		= 0x0002,
	RxOK		= 0x0001,
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	/* RxStatusDesc */
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	RxRWT	= (1 << 22),
	RxRES	= (1 << 21),
	RxRUNT	= (1 << 20),
	RxCRC	= (1 << 19),
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	/* ChipCmdBits */
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	StopReq		= 0x80,
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	CmdReset	= 0x10,
	CmdRxEnb	= 0x08,
	CmdTxEnb	= 0x04,
	RxBufEmpty	= 0x01,
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	/* TXPoll register p.5 */
	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
	FSWInt		= 0x01,		/* Forced software interrupt */

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	/* Cfg9346Bits */
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	Cfg9346_Lock	= 0x00,
	Cfg9346_Unlock	= 0xc0,
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	/* rx_mode_bits */
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	AcceptErr	= 0x20,
	AcceptRunt	= 0x10,
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#define RX_CONFIG_ACCEPT_ERR_MASK	0x30
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	AcceptBroadcast	= 0x08,
	AcceptMulticast	= 0x04,
	AcceptMyPhys	= 0x02,
	AcceptAllPhys	= 0x01,
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#define RX_CONFIG_ACCEPT_OK_MASK	0x0f
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#define RX_CONFIG_ACCEPT_MASK		0x3f
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	/* TxConfigBits */
	TxInterFrameGapShift = 24,
	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

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	/* Config1 register p.24 */
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	LEDS1		= (1 << 7),
	LEDS0		= (1 << 6),
	Speed_down	= (1 << 4),
	MEMMAP		= (1 << 3),
	IOMAP		= (1 << 2),
	VPD		= (1 << 1),
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	PMEnable	= (1 << 0),	/* Power Management Enable */

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	/* Config2 register p. 25 */
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	ClkReqEn	= (1 << 7),	/* Clock Request Enable */
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	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */
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	PCI_Clock_66MHz = 0x01,
	PCI_Clock_33MHz = 0x00,

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	/* Config3 register p.25 */
	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
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	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */
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	Rdy_to_L23	= (1 << 1),	/* L23 Enable */
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	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
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	/* Config4 register */
	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */

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	/* Config5 register p.27 */
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	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
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	Spi_en		= (1 << 3),
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	LanWake		= (1 << 1),	/* LanWake enable/disable */
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	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
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	ASPM_en		= (1 << 0),	/* ASPM enable */
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	/* CPlusCmd p.31 */
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	EnableBist	= (1 << 15),	// 8168 8101
	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
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	EnAnaPLL	= (1 << 14),	// 8169
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	Normal_mode	= (1 << 13),	// unused
	Force_half_dup	= (1 << 12),	// 8168 8101
	Force_rxflow_en	= (1 << 11),	// 8168 8101
	Force_txflow_en	= (1 << 10),	// 8168 8101
	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
	ASF		= (1 << 8),	// 8168 8101
	PktCntrDisable	= (1 << 7),	// 8168 8101
	Mac_dbgo_sel	= 0x001c,	// 8168
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	RxVlan		= (1 << 6),
	RxChkSum	= (1 << 5),
	PCIDAC		= (1 << 4),
	PCIMulRW	= (1 << 3),
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#define INTT_MASK	GENMASK(1, 0)
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#define CPCMD_MASK	(Normal_mode | RxVlan | RxChkSum | INTT_MASK)
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	/* rtl8169_PHYstatus */
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	TBI_Enable	= 0x80,
	TxFlowCtrl	= 0x40,
	RxFlowCtrl	= 0x20,
	_1000bpsF	= 0x10,
	_100bps		= 0x08,
	_10bps		= 0x04,
	LinkStatus	= 0x02,
	FullDup		= 0x01,
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	/* ResetCounterCommand */
	CounterReset	= 0x1,

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	/* DumpCounterCommand */
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	CounterDump	= 0x8,
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	/* magic enable v2 */
	MagicPacket_v2	= (1 << 16),	/* Wake up when receives a Magic Packet */
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};

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enum rtl_desc_bit {
	/* First doubleword. */
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	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
	RingEnd		= (1 << 30), /* End of descriptor ring */
	FirstFrag	= (1 << 29), /* First segment of a packet */
	LastFrag	= (1 << 28), /* Final segment of a packet */
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};

/* Generic case. */
enum rtl_tx_desc_bit {
	/* First doubleword. */
	TD_LSO		= (1 << 27),		/* Large Send Offload */
#define TD_MSS_MAX			0x07ffu	/* MSS value */
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	/* Second doubleword. */
	TxVlanTag	= (1 << 17),		/* Add VLAN tag */
};

/* 8169, 8168b and 810x except 8102e. */
enum rtl_tx_desc_bit_0 {
	/* First doubleword. */
#define TD0_MSS_SHIFT			16	/* MSS position (11 bits) */
	TD0_TCP_CS	= (1 << 16),		/* Calculate TCP/IP checksum */
	TD0_UDP_CS	= (1 << 17),		/* Calculate UDP/IP checksum */
	TD0_IP_CS	= (1 << 18),		/* Calculate IP checksum */
};

/* 8102e, 8168c and beyond. */
enum rtl_tx_desc_bit_1 {
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	/* First doubleword. */
	TD1_GTSENV4	= (1 << 26),		/* Giant Send for IPv4 */
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	TD1_GTSENV6	= (1 << 25),		/* Giant Send for IPv6 */
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#define GTTCPHO_SHIFT			18
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#define GTTCPHO_MAX			0x7f
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	/* Second doubleword. */
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#define TCPHO_SHIFT			18
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#define TCPHO_MAX			0x3ff
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#define TD1_MSS_SHIFT			18	/* MSS position (11 bits) */
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	TD1_IPv6_CS	= (1 << 28),		/* Calculate IPv6 checksum */
	TD1_IPv4_CS	= (1 << 29),		/* Calculate IPv4 checksum */
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	TD1_TCP_CS	= (1 << 30),		/* Calculate TCP/IP checksum */
	TD1_UDP_CS	= (1 << 31),		/* Calculate UDP/IP checksum */
};
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enum rtl_rx_desc_bit {
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	/* Rx private */
	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
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	PID0		= (1 << 17), /* Protocol ID bit 0/2 */
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#define RxProtoUDP	(PID1)
#define RxProtoTCP	(PID0)
#define RxProtoIP	(PID1 | PID0)
#define RxProtoMask	RxProtoIP

	IPFail		= (1 << 16), /* IP checksum failed */
	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
	RxVlanTag	= (1 << 16), /* VLAN tag available */
};

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#define RTL_GSO_MAX_SIZE_V1	32000
#define RTL_GSO_MAX_SEGS_V1	24
#define RTL_GSO_MAX_SIZE_V2	64000
#define RTL_GSO_MAX_SEGS_V2	64

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struct TxDesc {
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	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct RxDesc {
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	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct ring_info {
	struct sk_buff	*skb;
	u32		len;
};

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struct rtl8169_counters {
	__le64	tx_packets;
	__le64	rx_packets;
	__le64	tx_errors;
	__le32	rx_errors;
	__le16	rx_missed;
	__le16	align_errors;
	__le32	tx_one_collision;
	__le32	tx_multi_collision;
	__le64	rx_unicast;
	__le64	rx_broadcast;
	__le32	rx_multicast;
	__le16	tx_aborted;
	__le16	tx_underun;
};

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struct rtl8169_tc_offsets {
	bool	inited;
	__le64	tx_errors;
	__le32	tx_multi_collision;
	__le16	tx_aborted;
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	__le16	rx_missed;
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};

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enum rtl_flag {
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	RTL_FLAG_TASK_ENABLED = 0,
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	RTL_FLAG_TASK_RESET_PENDING,
	RTL_FLAG_MAX
};

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struct rtl8169_stats {
	u64			packets;
	u64			bytes;
	struct u64_stats_sync	syncp;
};

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struct rtl8169_private {
	void __iomem *mmio_addr;	/* memory map physical address */
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	struct pci_dev *pci_dev;
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	struct net_device *dev;
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	struct phy_device *phydev;
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	struct napi_struct napi;
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	enum mac_version mac_version;
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	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
	u32 dirty_tx;
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	struct rtl8169_stats rx_stats;
	struct rtl8169_stats tx_stats;
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	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
	dma_addr_t TxPhyAddr;
	dma_addr_t RxPhyAddr;
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	struct page *Rx_databuff[NUM_RX_DESC];	/* Rx data buffers */
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	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
	u16 cp_cmd;
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	u32 irq_mask;
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	struct clk *clk;
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	struct {
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		DECLARE_BITMAP(flags, RTL_FLAG_MAX);
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		struct work_struct work;
	} wk;

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	unsigned supports_gmii:1;
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	unsigned aspm_manageable:1;
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	dma_addr_t counters_phys_addr;
	struct rtl8169_counters *counters;
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	struct rtl8169_tc_offsets tc_offset;
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	u32 saved_wolopts;
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	int eee_adv;
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	const char *fw_name;
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	struct rtl_fw *rtl_fw;
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	u32 ocp_base;
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};

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typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);

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MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
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MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
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MODULE_SOFTDEP("pre: realtek");
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MODULE_LICENSE("GPL");
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MODULE_FIRMWARE(FIRMWARE_8168D_1);
MODULE_FIRMWARE(FIRMWARE_8168D_2);
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MODULE_FIRMWARE(FIRMWARE_8168E_1);
MODULE_FIRMWARE(FIRMWARE_8168E_2);
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MODULE_FIRMWARE(FIRMWARE_8168E_3);
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MODULE_FIRMWARE(FIRMWARE_8105E_1);
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MODULE_FIRMWARE(FIRMWARE_8168F_1);
MODULE_FIRMWARE(FIRMWARE_8168F_2);
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MODULE_FIRMWARE(FIRMWARE_8402_1);
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MODULE_FIRMWARE(FIRMWARE_8411_1);
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MODULE_FIRMWARE(FIRMWARE_8411_2);
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MODULE_FIRMWARE(FIRMWARE_8106E_1);
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MODULE_FIRMWARE(FIRMWARE_8106E_2);
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MODULE_FIRMWARE(FIRMWARE_8168G_2);
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MODULE_FIRMWARE(FIRMWARE_8168G_3);
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MODULE_FIRMWARE(FIRMWARE_8168H_1);
MODULE_FIRMWARE(FIRMWARE_8168H_2);
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MODULE_FIRMWARE(FIRMWARE_8168FP_3);
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MODULE_FIRMWARE(FIRMWARE_8107E_1);
MODULE_FIRMWARE(FIRMWARE_8107E_2);
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MODULE_FIRMWARE(FIRMWARE_8125A_3);
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MODULE_FIRMWARE(FIRMWARE_8125B_2);
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static inline struct device *tp_to_dev(struct rtl8169_private *tp)
{
	return &tp->pci_dev->dev;
}

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static void rtl_lock_config_regs(struct rtl8169_private *tp)
{
	RTL_W8(tp, Cfg9346, Cfg9346_Lock);
}

static void rtl_unlock_config_regs(struct rtl8169_private *tp)
{
	RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
}

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static void rtl_pci_commit(struct rtl8169_private *tp)
{
	/* Read an arbitrary register to commit a preceding PCI write */
	RTL_R8(tp, ChipCmd);
}

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static bool rtl_is_8125(struct rtl8169_private *tp)
{
	return tp->mac_version >= RTL_GIGA_MAC_VER_60;
}

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static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
{
	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
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	       tp->mac_version != RTL_GIGA_MAC_VER_39 &&
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	       tp->mac_version <= RTL_GIGA_MAC_VER_52;
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}

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static bool rtl_supports_eee(struct rtl8169_private *tp)
{
	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
	       tp->mac_version != RTL_GIGA_MAC_VER_37 &&
	       tp->mac_version != RTL_GIGA_MAC_VER_39;
}

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static void rtl_get_priv_stats(struct rtl8169_stats *stats,
			       u64 *pkts, u64 *bytes)
{
	unsigned int start;

	do {
		start = u64_stats_fetch_begin_irq(&stats->syncp);
		*pkts = stats->packets;
		*bytes = stats->bytes;
	} while (u64_stats_fetch_retry_irq(&stats->syncp, start));
}

static void rtl_inc_priv_stats(struct rtl8169_stats *stats,
			       u64 pkts, u64 bytes)
{
	u64_stats_update_begin(&stats->syncp);
	stats->packets += pkts;
	stats->bytes += bytes;
	u64_stats_update_end(&stats->syncp);
}

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static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
{
	int i;

	for (i = 0; i < ETH_ALEN; i++)
		mac[i] = RTL_R8(tp, reg + i);
}

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struct rtl_cond {
	bool (*check)(struct rtl8169_private *);
	const char *msg;
};

static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
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			  unsigned long usecs, int n, bool high)
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{
	int i;

	for (i = 0; i < n; i++) {
		if (c->check(tp) == high)
			return true;
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		fsleep(usecs);
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	}
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	if (net_ratelimit())
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		netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
			   c->msg, !high, n, usecs);
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	return false;
}

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static bool rtl_loop_wait_high(struct rtl8169_private *tp,
			       const struct rtl_cond *c,
			       unsigned long d, int n)
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{
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	return rtl_loop_wait(tp, c, d, n, true);
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}

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static bool rtl_loop_wait_low(struct rtl8169_private *tp,
			      const struct rtl_cond *c,
			      unsigned long d, int n)
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{
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	return rtl_loop_wait(tp, c, d, n, false);
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}

#define DECLARE_RTL_COND(name)				\
static bool name ## _check(struct rtl8169_private *);	\
							\
static const struct rtl_cond name = {			\
	.check	= name ## _check,			\
	.msg	= #name					\
};							\
							\
static bool name ## _check(struct rtl8169_private *tp)

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static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
{
	if (reg & 0xffff0001) {
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		if (net_ratelimit())
			netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
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		return true;
	}
	return false;
}

DECLARE_RTL_COND(rtl_ocp_gphy_cond)
{
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	return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
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}

static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
	if (rtl_ocp_reg_failure(tp, reg))
		return;

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	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
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	rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
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}

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static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
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{
	if (rtl_ocp_reg_failure(tp, reg))
		return 0;

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	RTL_W32(tp, GPHY_OCP, reg << 15);
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	return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
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		(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
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}

static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
	if (rtl_ocp_reg_failure(tp, reg))
		return;

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	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
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}

static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
{
	if (rtl_ocp_reg_failure(tp, reg))
		return 0;

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	RTL_W32(tp, OCPDR, reg << 15);
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	return RTL_R32(tp, OCPDR);
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}

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static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
				 u16 set)
{
	u16 data = r8168_mac_ocp_read(tp, reg);

	r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
}

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static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
{
	if (reg == 0x1f) {
		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
		return;
	}

	if (tp->ocp_base != OCP_STD_PHY_BASE)
		reg -= 0x10;

	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
}

static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
{
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	if (reg == 0x1f)
		return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;

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	if (tp->ocp_base != OCP_STD_PHY_BASE)
		reg -= 0x10;

	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
}

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static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
{
	if (reg == 0x1f) {
		tp->ocp_base = value << 4;
		return;
	}

	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
}

static int mac_mcu_read(struct rtl8169_private *tp, int reg)
{
	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
}

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DECLARE_RTL_COND(rtl_phyar_cond)
{
881
	return RTL_R32(tp, PHYAR) & 0x80000000;
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}

884
static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
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{
886
	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
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887

888
	rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
889
	/*
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	 * According to hardware specs a 20us delay is required after write
	 * complete indication, but before sending next command.
892
	 */
893
	udelay(20);
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}

896
static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
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{
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	int value;
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	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
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902
	value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
903
		RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
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	/*
	 * According to hardware specs a 20us delay is required after read
	 * complete indication, but before sending next command.
	 */
	udelay(20);

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	return value;
}

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DECLARE_RTL_COND(rtl_ocpar_cond)
{
916
	return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
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}

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static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
920
{
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	RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
	RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
	RTL_W32(tp, EPHY_RXER_NUM, 0);
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925
	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
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}

928
static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
929
{
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	r8168dp_1_mdio_access(tp, reg,
			      OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
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}

934
static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
935
{
936
	r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
937 938

	mdelay(1);
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	RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
	RTL_W32(tp, EPHY_RXER_NUM, 0);
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942
	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
943
		RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
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}

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#define R8168DP_1_MDIO_ACCESS_BIT	0x00020000

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static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
949
{
950
	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
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}

953
static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
954
{
955
	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
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}

958
static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
959
{
960
	r8168dp_2_mdio_start(tp);
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962
	r8169_mdio_write(tp, reg, value);
963

964
	r8168dp_2_mdio_stop(tp);
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}

967
static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
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{
	int value;

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	/* Work around issue with chip reporting wrong PHY ID */
	if (reg == MII_PHYSID2)
		return 0xc912;

975
	r8168dp_2_mdio_start(tp);
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977
	value = r8169_mdio_read(tp, reg);
978

979
	r8168dp_2_mdio_stop(tp);
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	return value;
}

984
static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
985
{
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	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
		r8168dp_1_mdio_write(tp, location, val);
		break;
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		r8168dp_2_mdio_write(tp, location, val);
		break;
994
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
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		r8168g_mdio_write(tp, location, val);
		break;
	default:
		r8169_mdio_write(tp, location, val);
		break;
	}
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}

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static int rtl_readphy(struct rtl8169_private *tp, int location)
{
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	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
		return r8168dp_1_mdio_read(tp, location);
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		return r8168dp_2_mdio_read(tp, location);
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	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
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		return r8168g_mdio_read(tp, location);
	default:
		return r8169_mdio_read(tp, location);
	}
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}

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DECLARE_RTL_COND(rtl_ephyar_cond)
{
1020
	return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
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}

1023
static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1024
{
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	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
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		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

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	rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1029 1030

	udelay(10);
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}

1033
static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1034
{
1035
	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1036

1037
	return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
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		RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
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}

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static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
{
	/* based on RTL8168FP_OOBMAC_BASE in vendor driver */
	if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
		*cmd |= 0x7f0 << 18;
}

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DECLARE_RTL_COND(rtl_eriar_cond)
{
1050
	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
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}

1053 1054
static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
			   u32 val, int type)
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{
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	u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;

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1058
	BUG_ON((addr & 3) || (mask == 0));
1059
	RTL_W32(tp, ERIDR, val);
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	r8168fp_adjust_ocp_cmd(tp, &cmd, type);
	RTL_W32(tp, ERIAR, cmd);
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1063
	rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
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}

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static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
			  u32 val)
{
	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
}

static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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{
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	u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;

	r8168fp_adjust_ocp_cmd(tp, &cmd, type);
	RTL_W32(tp, ERIAR, cmd);
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1078

1079
	return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1080
		RTL_R32(tp, ERIDR) : ~0;
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}

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static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
{
	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
}

1088
static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
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{
1090
	u32 val = rtl_eri_read(tp, addr);
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1092
	rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
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}

1095
static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1096
{
1097
	rtl_w0w1_eri(tp, addr, p, 0);
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}

1100
static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1101
{
1102
	rtl_w0w1_eri(tp, addr, 0, m);
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}

1105
static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1106
{
1107
	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1108
	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
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		RTL_R32(tp, OCPDR) : ~0;
1110 1111
}

1112
static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1113
{
1114
	return _rtl_eri_read(tp, reg, ERIAR_OOB);
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}

static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
			      u32 data)
{
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	RTL_W32(tp, OCPDR, data);
	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1122
	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
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}

static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
			      u32 data)
{
1128 1129
	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
		       data, ERIAR_OOB);
1130 1131
}

1132
static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1133
{
1134
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1135

1136
	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
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}

#define OOB_CMD_RESET		0x00
#define OOB_CMD_DRIVER_START	0x05
#define OOB_CMD_DRIVER_STOP	0x06

static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
{
	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
}

1148
DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1149 1150 1151 1152 1153
{
	u16 reg;

	reg = rtl8168_get_ocp_reg(tp);

1154
	return r8168dp_ocp_read(tp, reg) & 0x00000800;
1155 1156
}

1157
DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1158
{
1159
	return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
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}

DECLARE_RTL_COND(rtl_ocp_tx_cond)
{
1164
	return RTL_R8(tp, IBISR0) & 0x20;
1165
}
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1167 1168
static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
{
1169
	RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1170
	rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
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	RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
	RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
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}

1175 1176
static void rtl8168dp_driver_start(struct rtl8169_private *tp)
{
1177
	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1178
	rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
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}

1181
static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1182
{
1183
	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1184
	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1185
	rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
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}

static void rtl8168_driver_start(struct rtl8169_private *tp)
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl8168dp_driver_start(tp);
		break;
1196
	case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
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		rtl8168ep_driver_start(tp);
		break;
	default:
		BUG();
		break;
	}
}
1204

1205 1206
static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
{
1207
	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1208
	rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
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}

1211 1212
static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
{
1213
	rtl8168ep_stop_cmac(tp);
1214
	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1215
	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1216
	rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
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}

static void rtl8168_driver_stop(struct rtl8169_private *tp)
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl8168dp_driver_stop(tp);
		break;
1227
	case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
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		rtl8168ep_driver_stop(tp);
		break;
	default:
		BUG();
		break;
	}
}

1236
static bool r8168dp_check_dash(struct rtl8169_private *tp)
1237 1238 1239
{
	u16 reg = rtl8168_get_ocp_reg(tp);

1240
	return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
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}

1243
static bool r8168ep_check_dash(struct rtl8169_private *tp)
1244
{
1245
	return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
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}

1248
static bool r8168_check_dash(struct rtl8169_private *tp)
1249 1250 1251 1252 1253 1254
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		return r8168dp_check_dash(tp);
1255
	case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1256 1257
		return r8168ep_check_dash(tp);
	default:
1258
		return false;
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	}
}

1262 1263
static void rtl_reset_packet_filter(struct rtl8169_private *tp)
{
1264 1265
	rtl_eri_clear_bits(tp, 0xdc, BIT(0));
	rtl_eri_set_bits(tp, 0xdc, BIT(0));
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}

1268 1269
DECLARE_RTL_COND(rtl_efusear_cond)
{
1270
	return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1271 1272
}

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u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1274
{
1275
	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1276

1277
	return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
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		RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
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}

1281 1282
static u32 rtl_get_events(struct rtl8169_private *tp)
{
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	if (rtl_is_8125(tp))
		return RTL_R32(tp, IntrStatus_8125);
	else
		return RTL_R16(tp, IntrStatus);
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}

static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
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{
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	if (rtl_is_8125(tp))
		RTL_W32(tp, IntrStatus_8125, bits);
	else
		RTL_W16(tp, IntrStatus, bits);
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}

static void rtl_irq_disable(struct rtl8169_private *tp)
{
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	if (rtl_is_8125(tp))
		RTL_W32(tp, IntrMask_8125, 0);
	else
		RTL_W16(tp, IntrMask, 0);
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}

1305
static void rtl_irq_enable(struct rtl8169_private *tp)
1306
{
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	if (rtl_is_8125(tp))
		RTL_W32(tp, IntrMask_8125, tp->irq_mask);
	else
		RTL_W16(tp, IntrMask, tp->irq_mask);
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}

1313
static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
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{
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	rtl_irq_disable(tp);
1316
	rtl_ack_events(tp, 0xffffffff);
1317
	rtl_pci_commit(tp);
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}

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static void rtl_link_chg_patch(struct rtl8169_private *tp)
{
1322
	struct phy_device *phydev = tp->phydev;
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1323

1324 1325
	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_38) {
1326
		if (phydev->speed == SPEED_1000) {
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			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
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		} else if (phydev->speed == SPEED_100) {
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			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
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		} else {
1333 1334
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
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1335
		}
1336
		rtl_reset_packet_filter(tp);
1337 1338
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_36) {
1339
		if (phydev->speed == SPEED_1000) {
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			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1342
		} else {
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			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
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		}
1346
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
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		if (phydev->speed == SPEED_10) {
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			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
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		} else {
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			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
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		}
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	}
}

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#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)

static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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{
	struct rtl8169_private *tp = netdev_priv(dev);
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	wol->supported = WAKE_ANY;
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	wol->wolopts = tp->saved_wolopts;
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}

static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
{
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	static const struct {
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		u32 opt;
		u16 reg;
		u8  mask;
	} cfg[] = {
		{ WAKE_PHY,   Config3, LinkUp },
		{ WAKE_UCAST, Config5, UWF },
		{ WAKE_BCAST, Config5, BWF },
		{ WAKE_MCAST, Config5, MWF },
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		{ WAKE_ANY,   Config5, LanWake },
		{ WAKE_MAGIC, Config3, MagicPacket }
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	};
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	unsigned int i, tmp = ARRAY_SIZE(cfg);
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	u8 options;
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	rtl_unlock_config_regs(tp);
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	if (rtl_is_8168evl_up(tp)) {
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		tmp--;
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		if (wolopts & WAKE_MAGIC)
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			rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
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		else
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			rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
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	} else if (rtl_is_8125(tp)) {
		tmp--;
		if (wolopts & WAKE_MAGIC)
			r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
		else
			r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
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	}

	for (i = 0; i < tmp; i++) {
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		options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
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		if (wolopts & cfg[i].opt)
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			options |= cfg[i].mask;
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		RTL_W8(tp, cfg[i].reg, options);
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	}

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	switch (tp->mac_version) {
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	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
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		options = RTL_R8(tp, Config1) & ~PMEnable;
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		if (wolopts)
			options |= PMEnable;
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		RTL_W8(tp, Config1, options);
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		break;
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	case RTL_GIGA_MAC_VER_34:
	case RTL_GIGA_MAC_VER_37:
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	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
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		options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
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		if (wolopts)
			options |= PME_SIGNAL;
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		RTL_W8(tp, Config2, options);
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		break;
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	default:
		break;
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	}

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	rtl_lock_config_regs(tp);
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	device_set_wakeup_enable(tp_to_dev(tp), wolopts);
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	tp->dev->wol_enabled = wolopts ? 1 : 0;
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}

static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct rtl8169_private *tp = netdev_priv(dev);
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	if (wol->wolopts & ~WAKE_ANY)
		return -EINVAL;

	tp->saved_wolopts = wol->wolopts;
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	__rtl8169_set_wol(tp, tp->saved_wolopts);
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	return 0;
}

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static void rtl8169_get_drvinfo(struct net_device *dev,
				struct ethtool_drvinfo *info)
{
	struct rtl8169_private *tp = netdev_priv(dev);
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	struct rtl_fw *rtl_fw = tp->rtl_fw;
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	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
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	BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
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	if (rtl_fw)
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		strlcpy(info->fw_version, rtl_fw->version,
			sizeof(info->fw_version));
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}

static int rtl8169_get_regs_len(struct net_device *dev)
{
	return R8169_REGS_SIZE;
}

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static netdev_features_t rtl8169_fix_features(struct net_device *dev,
	netdev_features_t features)
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{
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	struct rtl8169_private *tp = netdev_priv(dev);

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	if (dev->mtu > TD_MSS_MAX)
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		features &= ~NETIF_F_ALL_TSO;
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	if (dev->mtu > ETH_DATA_LEN &&
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	    tp->mac_version > RTL_GIGA_MAC_VER_06)
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		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
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	return features;
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}

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static void rtl_set_rx_config_features(struct rtl8169_private *tp,
				       netdev_features_t features)
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{
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	u32 rx_config = RTL_R32(tp, RxConfig);
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1483
	if (features & NETIF_F_RXALL)
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		rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
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	else
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		rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
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	if (rtl_is_8125(tp)) {
		if (features & NETIF_F_HW_VLAN_CTAG_RX)
			rx_config |= RX_VLAN_8125;
		else
			rx_config &= ~RX_VLAN_8125;
	}

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	RTL_W32(tp, RxConfig, rx_config);
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}

static int rtl8169_set_features(struct net_device *dev,
				netdev_features_t features)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_set_rx_config_features(tp, features);
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	if (features & NETIF_F_RXCSUM)
		tp->cp_cmd |= RxChkSum;
	else
		tp->cp_cmd &= ~RxChkSum;
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	if (!rtl_is_8125(tp)) {
		if (features & NETIF_F_HW_VLAN_CTAG_RX)
			tp->cp_cmd |= RxVlan;
		else
			tp->cp_cmd &= ~RxVlan;
	}
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	RTL_W16(tp, CPlusCmd, tp->cp_cmd);
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	rtl_pci_commit(tp);
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	return 0;
}

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static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
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{
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	return (skb_vlan_tag_present(skb)) ?
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		TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
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}

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static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
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{
	u32 opts2 = le32_to_cpu(desc->opts2);

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	if (opts2 & RxVlanTag)
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		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
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}

static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			     void *p)
{
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	struct rtl8169_private *tp = netdev_priv(dev);
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	u32 __iomem *data = tp->mmio_addr;
	u32 *dw = p;
	int i;
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	for (i = 0; i < R8169_REGS_SIZE; i += 4)
		memcpy_fromio(dw++, data++, 4);
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}

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static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
	"tx_packets",
	"rx_packets",
	"tx_errors",
	"rx_errors",
	"rx_missed",
	"align_errors",
	"tx_single_collisions",
	"tx_multi_collisions",
	"unicast",
	"broadcast",
	"multicast",
	"tx_aborted",
	"tx_underrun",
};

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static int rtl8169_get_sset_count(struct net_device *dev, int sset)
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{
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	switch (sset) {
	case ETH_SS_STATS:
		return ARRAY_SIZE(rtl8169_gstrings);
	default:
		return -EOPNOTSUPP;
	}
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}

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DECLARE_RTL_COND(rtl_counters_cond)
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{
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	return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
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}

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static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1581
{
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	dma_addr_t paddr = tp->counters_phys_addr;
	u32 cmd;
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	RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
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	rtl_pci_commit(tp);
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	cmd = (u64)paddr & DMA_BIT_MASK(32);
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	RTL_W32(tp, CounterAddrLow, cmd);
	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
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	rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
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}

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static void rtl8169_reset_counters(struct rtl8169_private *tp)
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{
	/*
	 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
	 * tally counters.
	 */
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	if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
		rtl8169_do_counters(tp, CounterReset);
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}

1604
static void rtl8169_update_counters(struct rtl8169_private *tp)
1605
{
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	u8 val = RTL_R8(tp, ChipCmd);

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	/*
	 * Some chips are unable to dump tally counters when the receiver
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	 * is disabled. If 0xff chip may be in a PCI power-save state.
1611
	 */
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	if (val & CmdRxEnb && val != 0xff)
		rtl8169_do_counters(tp, CounterDump);
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}

1616
static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1617
{
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	struct rtl8169_counters *counters = tp->counters;
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	/*
	 * rtl8169_init_counter_offsets is called from rtl_open.  On chip
	 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
	 * reset by a power cycle, while the counter values collected by the
	 * driver are reset at every driver unload/load cycle.
	 *
	 * To make sure the HW values returned by @get_stats64 match the SW
	 * values, we collect the initial values at first open(*) and use them
	 * as offsets to normalize the values returned by @get_stats64.
	 *
	 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
	 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
	 * set at open time by rtl_hw_start.
	 */

	if (tp->tc_offset.inited)
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		return;
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	rtl8169_reset_counters(tp);
	rtl8169_update_counters(tp);
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	tp->tc_offset.tx_errors = counters->tx_errors;
	tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
	tp->tc_offset.tx_aborted = counters->tx_aborted;
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	tp->tc_offset.rx_missed = counters->rx_missed;
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	tp->tc_offset.inited = true;
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}

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static void rtl8169_get_ethtool_stats(struct net_device *dev,
				      struct ethtool_stats *stats, u64 *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);
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	struct rtl8169_counters *counters;
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1654 1655
	counters = tp->counters;
	rtl8169_update_counters(tp);
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	data[0] = le64_to_cpu(counters->tx_packets);
	data[1] = le64_to_cpu(counters->rx_packets);
	data[2] = le64_to_cpu(counters->tx_errors);
	data[3] = le32_to_cpu(counters->rx_errors);
	data[4] = le16_to_cpu(counters->rx_missed);
	data[5] = le16_to_cpu(counters->align_errors);
	data[6] = le32_to_cpu(counters->tx_one_collision);
	data[7] = le32_to_cpu(counters->tx_multi_collision);
	data[8] = le64_to_cpu(counters->rx_unicast);
	data[9] = le64_to_cpu(counters->rx_broadcast);
	data[10] = le32_to_cpu(counters->rx_multicast);
	data[11] = le16_to_cpu(counters->tx_aborted);
	data[12] = le16_to_cpu(counters->tx_underun);
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}

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static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_STATS:
		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
		break;
	}
}

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/*
 * Interrupt coalescing
 *
 * > 1 - the availability of the IntrMitigate (0xe2) register through the
 * >     8169, 8168 and 810x line of chipsets
 *
 * 8169, 8168, and 8136(810x) serial chipsets support it.
 *
 * > 2 - the Tx timer unit at gigabit speed
 *
 * The unit of the timer depends on both the speed and the setting of CPlusCmd
 * (0xe0) bit 1 and bit 0.
 *
 * For 8169
 * bit[1:0] \ speed        1000M           100M            10M
 * 0 0                     320ns           2.56us          40.96us
 * 0 1                     2.56us          20.48us         327.7us
 * 1 0                     5.12us          40.96us         655.4us
 * 1 1                     10.24us         81.92us         1.31ms
 *
 * For the other
 * bit[1:0] \ speed        1000M           100M            10M
 * 0 0                     5us             2.56us          40.96us
 * 0 1                     40us            20.48us         327.7us
 * 1 0                     80us            40.96us         655.4us
 * 1 1                     160us           81.92us         1.31ms
 */

/* rx/tx scale factors for all CPlusCmd[0:1] cases */
struct rtl_coalesce_info {
	u32 speed;
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	u32 scale_nsecs[4];
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};

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/* produce array with base delay *1, *8, *8*2, *8*2*2 */
#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }

1718
static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1719
	{ SPEED_1000,	COALESCE_DELAY(320) },
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	{ SPEED_100,	COALESCE_DELAY(2560) },
	{ SPEED_10,	COALESCE_DELAY(40960) },
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	{ 0 },
};

static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1726
	{ SPEED_1000,	COALESCE_DELAY(5000) },
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	{ SPEED_100,	COALESCE_DELAY(2560) },
	{ SPEED_10,	COALESCE_DELAY(40960) },
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	{ 0 },
};
1731
#undef COALESCE_DELAY
1732 1733

/* get rx/tx scale vector corresponding to current speed */
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static const struct rtl_coalesce_info *
rtl_coalesce_info(struct rtl8169_private *tp)
1736 1737 1738
{
	const struct rtl_coalesce_info *ci;

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	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		ci = rtl_coalesce_info_8169;
	else
		ci = rtl_coalesce_info_8168_8136;
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1744 1745 1746 1747
	/* if speed is unknown assume highest one */
	if (tp->phydev->speed == SPEED_UNKNOWN)
		return ci;

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	for (; ci->speed; ci++) {
		if (tp->phydev->speed == ci->speed)
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			return ci;
	}

	return ERR_PTR(-ELNRNG);
}

static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	const struct rtl_coalesce_info *ci;
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	u32 scale, c_us, c_fr;
	u16 intrmit;
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	if (rtl_is_8125(tp))
		return -EOPNOTSUPP;

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	memset(ec, 0, sizeof(*ec));

	/* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
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	ci = rtl_coalesce_info(tp);
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	if (IS_ERR(ci))
		return PTR_ERR(ci);

1773
	scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
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	intrmit = RTL_R16(tp, IntrMitigate);
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	c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
	ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
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	c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
	/* ethtool_coalesce states usecs and max_frames must not both be 0 */
	ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;

	c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
	ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);

	c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
	ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
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	return 0;
}

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/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
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				     u16 *cp01)
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{
	const struct rtl_coalesce_info *ci;
	u16 i;

1800
	ci = rtl_coalesce_info(tp);
1801
	if (IS_ERR(ci))
1802
		return PTR_ERR(ci);
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	for (i = 0; i < 4; i++) {
1805
		if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1806
			*cp01 = i;
1807
			return ci->scale_nsecs[i];
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		}
	}

1811
	return -ERANGE;
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}

static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
{
	struct rtl8169_private *tp = netdev_priv(dev);
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	u32 tx_fr = ec->tx_max_coalesced_frames;
	u32 rx_fr = ec->rx_max_coalesced_frames;
	u32 coal_usec_max, units;
1820
	u16 w = 0, cp01 = 0;
1821
	int scale;
1822

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	if (rtl_is_8125(tp))
		return -EOPNOTSUPP;

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	if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
		return -ERANGE;

1829 1830
	coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
	scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
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	if (scale < 0)
		return scale;
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	/* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
	 * not only when usecs=0 because of e.g. the following scenario:
	 *
	 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
	 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
	 * - then user does `ethtool -C eth0 rx-usecs 100`
	 *
	 * Since ethtool sends to kernel whole ethtool_coalesce settings,
	 * if we want to ignore rx_frames then it has to be set to 0.
	 */
	if (rx_fr == 1)
		rx_fr = 0;
	if (tx_fr == 1)
		tx_fr = 0;
1848

1849 1850 1851 1852 1853
	/* HW requires time limit to be set if frame limit is set */
	if ((tx_fr && !ec->tx_coalesce_usecs) ||
	    (rx_fr && !ec->rx_coalesce_usecs))
		return -EINVAL;

1854 1855
	w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
	w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1856

1857 1858 1859 1860
	units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
	w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
	units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
	w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1861

1862
	RTL_W16(tp, IntrMitigate, w);
1863

1864 1865 1866 1867 1868 1869 1870 1871 1872
	/* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
	if (rtl_is_8168evl_up(tp)) {
		if (!rx_fr && !tx_fr)
			/* disable packet counter */
			tp->cp_cmd |= PktCntrDisable;
		else
			tp->cp_cmd &= ~PktCntrDisable;
	}

1873
	tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1874
	RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1875
	rtl_pci_commit(tp);
1876 1877 1878 1879

	return 0;
}

1880 1881 1882 1883
static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1884 1885 1886
	if (!rtl_supports_eee(tp))
		return -EOPNOTSUPP;

1887
	return phy_ethtool_get_eee(tp->phydev, data);
1888 1889 1890 1891 1892
}

static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1893 1894 1895 1896
	int ret;

	if (!rtl_supports_eee(tp))
		return -EOPNOTSUPP;
1897

1898
	ret = phy_ethtool_set_eee(tp->phydev, data);
1899 1900 1901 1902

	if (!ret)
		tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
					   MDIO_AN_EEE_ADV);
1903
	return ret;
1904 1905
}

1906
static const struct ethtool_ops rtl8169_ethtool_ops = {
1907 1908
	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
				     ETHTOOL_COALESCE_MAX_FRAMES,
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1909 1910 1911
	.get_drvinfo		= rtl8169_get_drvinfo,
	.get_regs_len		= rtl8169_get_regs_len,
	.get_link		= ethtool_op_get_link,
1912 1913
	.get_coalesce		= rtl_get_coalesce,
	.set_coalesce		= rtl_set_coalesce,
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1914
	.get_regs		= rtl8169_get_regs,
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1915 1916
	.get_wol		= rtl8169_get_wol,
	.set_wol		= rtl8169_set_wol,
1917
	.get_strings		= rtl8169_get_strings,
1918
	.get_sset_count		= rtl8169_get_sset_count,
1919
	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
1920
	.get_ts_info		= ethtool_op_get_ts_info,
1921
	.nway_reset		= phy_ethtool_nway_reset,
1922 1923
	.get_eee		= rtl8169_get_eee,
	.set_eee		= rtl8169_set_eee,
1924 1925
	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
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1926 1927
};

1928 1929
static void rtl_enable_eee(struct rtl8169_private *tp)
{
1930
	struct phy_device *phydev = tp->phydev;
1931 1932 1933 1934 1935 1936 1937
	int adv;

	/* respect EEE advertisement the user may have set */
	if (tp->eee_adv >= 0)
		adv = tp->eee_adv;
	else
		adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1938

1939 1940
	if (adv >= 0)
		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1941 1942
}

1943
static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
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1944
{
1945 1946 1947 1948 1949
	/*
	 * The driver currently handles the 8168Bf and the 8168Be identically
	 * but they can be identified more specifically through the test below
	 * if needed:
	 *
1950
	 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
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1951 1952 1953
	 *
	 * Same thing for the 8101Eb and the 8101Ec:
	 *
1954
	 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1955
	 */
1956
	static const struct rtl_mac_info {
1957 1958
		u16 mask;
		u16 val;
1959
		enum mac_version ver;
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1960
	} mac_info[] = {
1961 1962 1963 1964
		/* 8125B family. */
		{ 0x7cf, 0x641,	RTL_GIGA_MAC_VER_63 },

		/* 8125A family. */
1965 1966 1967
		{ 0x7cf, 0x608,	RTL_GIGA_MAC_VER_60 },
		{ 0x7c8, 0x608,	RTL_GIGA_MAC_VER_61 },

1968 1969 1970
		/* RTL8117 */
		{ 0x7cf, 0x54a,	RTL_GIGA_MAC_VER_52 },

1971
		/* 8168EP family. */
1972 1973 1974
		{ 0x7cf, 0x502,	RTL_GIGA_MAC_VER_51 },
		{ 0x7cf, 0x501,	RTL_GIGA_MAC_VER_50 },
		{ 0x7cf, 0x500,	RTL_GIGA_MAC_VER_49 },
1975

1976
		/* 8168H family. */
1977 1978
		{ 0x7cf, 0x541,	RTL_GIGA_MAC_VER_46 },
		{ 0x7cf, 0x540,	RTL_GIGA_MAC_VER_45 },
1979

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1980
		/* 8168G family. */
1981 1982 1983 1984
		{ 0x7cf, 0x5c8,	RTL_GIGA_MAC_VER_44 },
		{ 0x7cf, 0x509,	RTL_GIGA_MAC_VER_42 },
		{ 0x7cf, 0x4c1,	RTL_GIGA_MAC_VER_41 },
		{ 0x7cf, 0x4c0,	RTL_GIGA_MAC_VER_40 },
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1985

1986
		/* 8168F family. */
1987 1988 1989
		{ 0x7c8, 0x488,	RTL_GIGA_MAC_VER_38 },
		{ 0x7cf, 0x481,	RTL_GIGA_MAC_VER_36 },
		{ 0x7cf, 0x480,	RTL_GIGA_MAC_VER_35 },
1990

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1991
		/* 8168E family. */
1992 1993 1994
		{ 0x7c8, 0x2c8,	RTL_GIGA_MAC_VER_34 },
		{ 0x7cf, 0x2c1,	RTL_GIGA_MAC_VER_32 },
		{ 0x7c8, 0x2c0,	RTL_GIGA_MAC_VER_33 },
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1995

1996
		/* 8168D family. */
1997 1998
		{ 0x7cf, 0x281,	RTL_GIGA_MAC_VER_25 },
		{ 0x7c8, 0x280,	RTL_GIGA_MAC_VER_26 },
1999

2000
		/* 8168DP family. */
2001 2002 2003
		{ 0x7cf, 0x288,	RTL_GIGA_MAC_VER_27 },
		{ 0x7cf, 0x28a,	RTL_GIGA_MAC_VER_28 },
		{ 0x7cf, 0x28b,	RTL_GIGA_MAC_VER_31 },
2004

2005
		/* 8168C family. */
2006 2007 2008 2009 2010 2011 2012
		{ 0x7cf, 0x3c9,	RTL_GIGA_MAC_VER_23 },
		{ 0x7cf, 0x3c8,	RTL_GIGA_MAC_VER_18 },
		{ 0x7c8, 0x3c8,	RTL_GIGA_MAC_VER_24 },
		{ 0x7cf, 0x3c0,	RTL_GIGA_MAC_VER_19 },
		{ 0x7cf, 0x3c2,	RTL_GIGA_MAC_VER_20 },
		{ 0x7cf, 0x3c3,	RTL_GIGA_MAC_VER_21 },
		{ 0x7c8, 0x3c0,	RTL_GIGA_MAC_VER_22 },
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2013 2014

		/* 8168B family. */
2015 2016 2017
		{ 0x7cf, 0x380,	RTL_GIGA_MAC_VER_12 },
		{ 0x7c8, 0x380,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c8, 0x300,	RTL_GIGA_MAC_VER_11 },
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2018 2019

		/* 8101 family. */
2020 2021 2022 2023 2024 2025 2026 2027 2028
		{ 0x7c8, 0x448,	RTL_GIGA_MAC_VER_39 },
		{ 0x7c8, 0x440,	RTL_GIGA_MAC_VER_37 },
		{ 0x7cf, 0x409,	RTL_GIGA_MAC_VER_29 },
		{ 0x7c8, 0x408,	RTL_GIGA_MAC_VER_30 },
		{ 0x7cf, 0x349,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf, 0x249,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf, 0x348,	RTL_GIGA_MAC_VER_07 },
		{ 0x7cf, 0x248,	RTL_GIGA_MAC_VER_07 },
		{ 0x7cf, 0x340,	RTL_GIGA_MAC_VER_13 },
2029
		{ 0x7cf, 0x240,	RTL_GIGA_MAC_VER_14 },
2030 2031 2032 2033 2034
		{ 0x7cf, 0x343,	RTL_GIGA_MAC_VER_10 },
		{ 0x7cf, 0x342,	RTL_GIGA_MAC_VER_16 },
		{ 0x7c8, 0x348,	RTL_GIGA_MAC_VER_09 },
		{ 0x7c8, 0x248,	RTL_GIGA_MAC_VER_09 },
		{ 0x7c8, 0x340,	RTL_GIGA_MAC_VER_16 },
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2035
		/* FIXME: where did these entries come from ? -- FR */
2036 2037
		{ 0xfc8, 0x388,	RTL_GIGA_MAC_VER_13 },
		{ 0xfc8, 0x308,	RTL_GIGA_MAC_VER_13 },
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2038 2039

		/* 8110 family. */
2040 2041 2042 2043 2044
		{ 0xfc8, 0x980,	RTL_GIGA_MAC_VER_06 },
		{ 0xfc8, 0x180,	RTL_GIGA_MAC_VER_05 },
		{ 0xfc8, 0x100,	RTL_GIGA_MAC_VER_04 },
		{ 0xfc8, 0x040,	RTL_GIGA_MAC_VER_03 },
		{ 0xfc8, 0x008,	RTL_GIGA_MAC_VER_02 },
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2045

2046
		/* Catch-all */
2047
		{ 0x000, 0x000,	RTL_GIGA_MAC_NONE   }
2048 2049
	};
	const struct rtl_mac_info *p = mac_info;
2050
	enum mac_version ver;
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2051

2052
	while ((xid & p->mask) != p->val)
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2053
		p++;
2054 2055 2056 2057 2058 2059 2060 2061 2062
	ver = p->ver;

	if (ver != RTL_GIGA_MAC_NONE && !gmii) {
		if (ver == RTL_GIGA_MAC_VER_42)
			ver = RTL_GIGA_MAC_VER_43;
		else if (ver == RTL_GIGA_MAC_VER_45)
			ver = RTL_GIGA_MAC_VER_47;
		else if (ver == RTL_GIGA_MAC_VER_46)
			ver = RTL_GIGA_MAC_VER_48;
2063
	}
2064 2065

	return ver;
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2066 2067
}

2068 2069
static void rtl_release_firmware(struct rtl8169_private *tp)
{
2070
	if (tp->rtl_fw) {
2071
		rtl_fw_release_firmware(tp->rtl_fw);
2072
		kfree(tp->rtl_fw);
2073
		tp->rtl_fw = NULL;
2074
	}
2075 2076
}

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2077
void r8169_apply_firmware(struct rtl8169_private *tp)
2078
{
2079 2080
	int val;

2081
	/* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2082
	if (tp->rtl_fw) {
2083
		rtl_fw_write_firmware(tp, tp->rtl_fw);
2084 2085
		/* At least one firmware doesn't reset tp->ocp_base. */
		tp->ocp_base = OCP_STD_PHY_BASE;
2086 2087 2088 2089 2090

		/* PHY soft reset may still be in progress */
		phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
				      !(val & BMCR_RESET),
				      50000, 600000, true);
2091
	}
2092 2093
}

2094 2095
static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
{
2096 2097 2098 2099
	/* Adjust EEE LED frequency */
	if (tp->mac_version != RTL_GIGA_MAC_VER_38)
		RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);

2100
	rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2101 2102
}

2103
static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2104 2105 2106 2107 2108
{
	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
	r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
}

2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
{
	RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
}

static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
{
	rtl8125_set_eee_txidle_timer(tp);
	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
}

2120 2121 2122 2123 2124 2125 2126 2127
static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
{
	const u16 w[] = {
		addr[0] | (addr[1] << 8),
		addr[2] | (addr[3] << 8),
		addr[4] | (addr[5] << 8)
	};

2128 2129 2130 2131
	rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
	rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
	rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
	rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2132 2133
}

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2134
u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
{
	u16 data1, data2, ioffset;

	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
	data1 = r8168_mac_ocp_read(tp, 0xdd02);
	data2 = r8168_mac_ocp_read(tp, 0xdd00);

	ioffset = (data2 >> 1) & 0x7ff8;
	ioffset |= data2 & 0x0007;
	if (data1 & BIT(7))
		ioffset |= BIT(15);

	return ioffset;
}

2150 2151
static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
{
2152 2153
	set_bit(flag, tp->wk.flags);
	schedule_work(&tp->wk.work);
2154 2155
}

2156
static void rtl8169_init_phy(struct rtl8169_private *tp)
2157
{
2158
	r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2159

2160
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2161 2162
		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2163
		/* set undocumented MAC Reg C+CR Offset 0x82h */
2164
		RTL_W8(tp, 0x82, 0x01);
2165
	}
2166

2167 2168 2169 2170 2171
	if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
	    tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
	    tp->pci_dev->subsystem_device == 0xe000)
		phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);

2172
	/* We may have called phy_speed_down before */
2173
	phy_speed_up(tp->phydev);
2174

2175 2176 2177
	if (rtl_supports_eee(tp))
		rtl_enable_eee(tp);

2178
	genphy_soft_reset(tp->phydev);
2179 2180
}

2181 2182
static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
{
2183
	rtl_unlock_config_regs(tp);
2184

2185
	RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2186
	rtl_pci_commit(tp);
2187

2188
	RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2189
	rtl_pci_commit(tp);
2190

2191 2192
	if (tp->mac_version == RTL_GIGA_MAC_VER_34)
		rtl_rar_exgmac_set(tp, addr);
2193

2194
	rtl_lock_config_regs(tp);
2195 2196 2197 2198 2199
}

static int rtl_set_mac_address(struct net_device *dev, void *p)
{
	struct rtl8169_private *tp = netdev_priv(dev);
2200
	int ret;
2201

2202 2203 2204
	ret = eth_mac_addr(dev, p);
	if (ret)
		return ret;
2205

2206
	rtl_rar_set(tp, dev->dev_addr);
2207 2208 2209 2210

	return 0;
}

2211 2212 2213
static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
{
	switch (tp->mac_version) {
2214 2215
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
2216 2217 2218 2219 2220
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
2221
	case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
2222
		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2223 2224 2225 2226 2227 2228 2229
			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
		break;
	default:
		break;
	}
}

2230
static void rtl_pll_power_down(struct rtl8169_private *tp)
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2231
{
2232
	if (r8168_check_dash(tp))
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2233 2234
		return;

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2235 2236
	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_33)
2237
		rtl_ephy_write(tp, 0x19, 0xff64);
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2238

2239 2240 2241
	if (device_may_wakeup(tp_to_dev(tp))) {
		phy_speed_down(tp->phydev, false);
		rtl_wol_suspend_quirk(tp);
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2242
		return;
2243
	}
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2244 2245

	switch (tp->mac_version) {
2246
	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2247 2248 2249
	case RTL_GIGA_MAC_VER_37:
	case RTL_GIGA_MAC_VER_39:
	case RTL_GIGA_MAC_VER_43:
2250
	case RTL_GIGA_MAC_VER_44:
2251 2252
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
2253 2254
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
2255
	case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2256
		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
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2257
		break;
2258 2259
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
2260
	case RTL_GIGA_MAC_VER_49:
2261
		rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2262
		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2263
		break;
2264 2265
	default:
		break;
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2266 2267 2268
	}
}

2269
static void rtl_pll_power_up(struct rtl8169_private *tp)
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2270 2271
{
	switch (tp->mac_version) {
2272
	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2273 2274 2275
	case RTL_GIGA_MAC_VER_37:
	case RTL_GIGA_MAC_VER_39:
	case RTL_GIGA_MAC_VER_43:
2276
		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
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2277
		break;
2278
	case RTL_GIGA_MAC_VER_44:
2279 2280
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
2281 2282
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
2283
	case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2284
		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2285
		break;
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	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
2288
	case RTL_GIGA_MAC_VER_49:
2289
		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2290
		rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2291
		break;
2292 2293
	default:
		break;
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	}

2296
	phy_resume(tp->phydev);
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}

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static void rtl_init_rxcfg(struct rtl8169_private *tp)
{
	switch (tp->mac_version) {
2302
	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2303
	case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2304
		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2305
		break;
2306
	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2307 2308
	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
	case RTL_GIGA_MAC_VER_38:
2309
		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2310
		break;
2311
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2312
		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2313
		break;
2314
	case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2315
		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2316
		break;
2317
	default:
2318
		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2319 2320 2321 2322
		break;
	}
}

2323 2324
static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
{
2325
	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2326 2327
}

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static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
{
2330 2331
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
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}

static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
{
2336 2337
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
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}

static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
{
2342
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
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}

static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
{
2347
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
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}

static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
{
2352 2353 2354
	RTL_W8(tp, MaxTxPacketSize, 0x3f);
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
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}

static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
{
2359 2360 2361
	RTL_W8(tp, MaxTxPacketSize, 0x0c);
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
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}

static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
{
2366
	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
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}

static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
{
2371
	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
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2372 2373
}

2374
static void rtl_jumbo_config(struct rtl8169_private *tp)
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2375
{
2376
	bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
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2377

2378 2379 2380 2381
	rtl_unlock_config_regs(tp);
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
2382 2383 2384 2385 2386 2387
		if (jumbo) {
			pcie_set_readrq(tp->pci_dev, 512);
			r8168b_1_hw_jumbo_enable(tp);
		} else {
			r8168b_1_hw_jumbo_disable(tp);
		}
2388 2389
		break;
	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2390 2391 2392 2393 2394 2395
		if (jumbo) {
			pcie_set_readrq(tp->pci_dev, 512);
			r8168c_hw_jumbo_enable(tp);
		} else {
			r8168c_hw_jumbo_disable(tp);
		}
2396 2397
		break;
	case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2398 2399 2400 2401
		if (jumbo)
			r8168dp_hw_jumbo_enable(tp);
		else
			r8168dp_hw_jumbo_disable(tp);
2402
		break;
2403
	case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2404 2405 2406 2407 2408 2409
		if (jumbo) {
			pcie_set_readrq(tp->pci_dev, 512);
			r8168e_hw_jumbo_enable(tp);
		} else {
			r8168e_hw_jumbo_disable(tp);
		}
2410
		break;
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2411 2412 2413
	default:
		break;
	}
2414
	rtl_lock_config_regs(tp);
2415

2416
	if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2417
		pcie_set_readrq(tp->pci_dev, 4096);
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2418 2419
}

2420 2421
DECLARE_RTL_COND(rtl_chipcmd_cond)
{
2422
	return RTL_R8(tp, ChipCmd) & CmdReset;
2423 2424
}

2425 2426
static void rtl_hw_reset(struct rtl8169_private *tp)
{
2427
	RTL_W8(tp, ChipCmd, CmdReset);
2428

2429
	rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2430 2431
}

2432
static void rtl_request_firmware(struct rtl8169_private *tp)
2433
{
2434
	struct rtl_fw *rtl_fw;
2435

2436 2437 2438
	/* firmware loaded already or no firmware available */
	if (tp->rtl_fw || !tp->fw_name)
		return;
2439

2440
	rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2441
	if (!rtl_fw)
2442
		return;
2443

2444 2445 2446 2447
	rtl_fw->phy_write = rtl_writephy;
	rtl_fw->phy_read = rtl_readphy;
	rtl_fw->mac_mcu_write = mac_mcu_write;
	rtl_fw->mac_mcu_read = mac_mcu_read;
2448 2449
	rtl_fw->fw_name = tp->fw_name;
	rtl_fw->dev = tp_to_dev(tp);
2450

2451 2452 2453 2454
	if (rtl_fw_request_firmware(rtl_fw))
		kfree(rtl_fw);
	else
		tp->rtl_fw = rtl_fw;
2455 2456
}

2457 2458
static void rtl_rx_close(struct rtl8169_private *tp)
{
2459
	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2460 2461
}

2462 2463
DECLARE_RTL_COND(rtl_npq_cond)
{
2464
	return RTL_R8(tp, TxPoll) & NPQ;
2465 2466 2467 2468
}

DECLARE_RTL_COND(rtl_txcfg_empty_cond)
{
2469
	return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2470 2471
}

2472 2473 2474 2475 2476
DECLARE_RTL_COND(rtl_rxtx_empty_cond)
{
	return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
}

2477 2478 2479 2480 2481 2482
DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
{
	/* IntrMitigate has new functionality on RTL8125 */
	return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
}

2483 2484 2485 2486 2487 2488 2489 2490 2491 2492
static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
		break;
	case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
		break;
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	case RTL_GIGA_MAC_VER_63:
		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
		break;
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	default:
		break;
	}
}

2503 2504 2505 2506
static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
{
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
	fsleep(2000);
2507
	rtl_wait_txrx_fifo_empty(tp);
2508 2509
}

2510
static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2511
{
2512 2513 2514
	u32 val = TX_DMA_BURST << TxDMAShift |
		  InterFrameGap << TxInterFrameGapShift;

2515
	if (rtl_is_8168evl_up(tp))
2516 2517 2518
		val |= TXCFG_AUTO_FIFO;

	RTL_W32(tp, TxConfig, val);
2519 2520
}

2521
static void rtl_set_rx_max_size(struct rtl8169_private *tp)
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2522
{
2523 2524
	/* Low hurts. Let's disable the filtering. */
	RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2525 2526
}

2527
static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2528 2529 2530 2531 2532 2533
{
	/*
	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
	 * register to be written before TxDescAddrLow to work.
	 * Switching from MMIO to I/O access fixes the issue as well.
	 */
2534 2535 2536 2537
	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2538 2539
}

2540
static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2541
{
2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554
	u32 val;

	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
		val = 0x000fff00;
	else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
		val = 0x00ffff00;
	else
		return;

	if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
		val |= 0xff;

	RTL_W32(tp, 0x7c, val);
2555 2556
}

2557 2558
static void rtl_set_rx_mode(struct net_device *dev)
{
2559 2560 2561
	u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
	/* Multicast hash filter */
	u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2562
	struct rtl8169_private *tp = netdev_priv(dev);
2563
	u32 tmp;
2564 2565

	if (dev->flags & IFF_PROMISC) {
2566 2567 2568 2569 2570 2571 2572
		rx_mode |= AcceptAllPhys;
	} else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
		   dev->flags & IFF_ALLMULTI ||
		   tp->mac_version == RTL_GIGA_MAC_VER_35) {
		/* accept all multicasts */
	} else if (netdev_mc_empty(dev)) {
		rx_mode &= ~AcceptMulticast;
2573 2574 2575 2576 2577
	} else {
		struct netdev_hw_addr *ha;

		mc_filter[1] = mc_filter[0] = 0;
		netdev_for_each_mc_addr(ha, dev) {
2578
			u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2579 2580 2581 2582 2583 2584 2585
			mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
		}

		if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
			tmp = mc_filter[0];
			mc_filter[0] = swab32(mc_filter[1]);
			mc_filter[1] = swab32(tmp);
2586 2587 2588
		}
	}

2589 2590
	RTL_W32(tp, MAR0 + 4, mc_filter[1]);
	RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2591

2592
	tmp = RTL_R32(tp, RxConfig);
2593
	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2594 2595
}

2596 2597
DECLARE_RTL_COND(rtl_csiar_cond)
{
2598
	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2599 2600
}

2601
static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2602
{
2603
	u32 func = PCI_FUNC(tp->pci_dev->devfn);
2604

2605 2606
	RTL_W32(tp, CSIDR, value);
	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2607
		CSIAR_BYTE_ENABLE | func << 16);
2608

2609
	rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2610 2611
}

2612
static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2613
{
2614 2615 2616 2617
	u32 func = PCI_FUNC(tp->pci_dev->devfn);

	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
		CSIAR_BYTE_ENABLE);
2618

2619
	return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2620
		RTL_R32(tp, CSIDR) : ~0;
2621 2622
}

2623
static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2624
{
2625 2626
	struct pci_dev *pdev = tp->pci_dev;
	u32 csi;
2627

2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639
	/* According to Realtek the value at config space address 0x070f
	 * controls the L0s/L1 entrance latency. We try standard ECAM access
	 * first and if it fails fall back to CSI.
	 */
	if (pdev->cfg_size > 0x070f &&
	    pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
		return;

	netdev_notice_once(tp->dev,
		"No native access to PCI extended config space, falling back to CSI\n");
	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
	rtl_csi_write(tp, 0x070c, csi | val << 24);
2640 2641
}

2642
static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2643
{
2644
	rtl_csi_access_enable(tp, 0x27);
2645 2646 2647 2648 2649 2650 2651 2652
}

struct ephy_info {
	unsigned int offset;
	u16 mask;
	u16 bits;
};

2653 2654
static void __rtl_ephy_init(struct rtl8169_private *tp,
			    const struct ephy_info *e, int len)
2655 2656 2657 2658
{
	u16 w;

	while (len-- > 0) {
2659 2660
		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
		rtl_ephy_write(tp, e->offset, w);
2661 2662 2663 2664
		e++;
	}
}

2665 2666
#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))

2667
static void rtl_disable_clock_request(struct rtl8169_private *tp)
2668
{
2669
	pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2670
				   PCI_EXP_LNKCTL_CLKREQ_EN);
2671 2672
}

2673
static void rtl_enable_clock_request(struct rtl8169_private *tp)
2674
{
2675
	pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2676
				 PCI_EXP_LNKCTL_CLKREQ_EN);
2677 2678
}

2679
static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
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2680
{
2681 2682
	/* work around an issue when PCI reset occurs during L2/L3 state */
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
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2683 2684
}

2685 2686
static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
{
2687 2688
	/* Don't enable ASPM in the chip if OS can't control ASPM */
	if (enable && tp->aspm_manageable) {
2689
		RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2690
		RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2691 2692 2693 2694
	} else {
		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
		RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
	}
2695 2696

	udelay(10);
2697 2698
}

2699 2700 2701 2702 2703 2704 2705 2706 2707 2708
static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
			      u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
{
	/* Usage of dynamic vs. static FIFO is controlled by bit
	 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
	 */
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
}

2709 2710 2711 2712 2713 2714 2715 2716
static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
					  u8 low, u8 high)
{
	/* FIFO thresholds for pause flow control */
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
}

2717
static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2718
{
2719
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2720 2721
}

2722
static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2723
{
2724
	RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2725

2726
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2727

2728
	rtl_disable_clock_request(tp);
2729 2730
}

2731
static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2732
{
2733
	static const struct ephy_info e_info_8168cp[] = {
2734 2735 2736 2737 2738 2739 2740
		{ 0x01, 0,	0x0001 },
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0042 },
		{ 0x06, 0x0080,	0x0000 },
		{ 0x07, 0,	0x2000 }
	};

2741
	rtl_set_def_aspm_entry_latency(tp);
2742

2743
	rtl_ephy_init(tp, e_info_8168cp);
2744

2745
	__rtl_hw_start_8168cp(tp);
2746 2747
}

2748
static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2749
{
2750
	rtl_set_def_aspm_entry_latency(tp);
2751

2752
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2753 2754
}

2755
static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2756
{
2757
	rtl_set_def_aspm_entry_latency(tp);
2758

2759
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2760 2761

	/* Magic. */
2762
	RTL_W8(tp, DBG_REG, 0x20);
2763 2764
}

2765
static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2766
{
2767
	static const struct ephy_info e_info_8168c_1[] = {
2768 2769 2770 2771 2772
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0002 },
		{ 0x06, 0x0080,	0x0000 }
	};

2773
	rtl_set_def_aspm_entry_latency(tp);
2774

2775
	RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2776

2777
	rtl_ephy_init(tp, e_info_8168c_1);
2778

2779
	__rtl_hw_start_8168cp(tp);
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}

2782
static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2783
{
2784
	static const struct ephy_info e_info_8168c_2[] = {
2785
		{ 0x01, 0,	0x0001 },
2786
		{ 0x03, 0x0400,	0x0020 }
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	};

2789
	rtl_set_def_aspm_entry_latency(tp);
2790

2791
	rtl_ephy_init(tp, e_info_8168c_2);
2792

2793
	__rtl_hw_start_8168cp(tp);
2794 2795
}

2796
static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2797
{
2798
	rtl_hw_start_8168c_2(tp);
2799 2800
}

2801
static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2802
{
2803
	rtl_set_def_aspm_entry_latency(tp);
2804

2805
	__rtl_hw_start_8168cp(tp);
2806 2807
}

2808
static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2809
{
2810
	rtl_set_def_aspm_entry_latency(tp);
2811

2812
	rtl_disable_clock_request(tp);
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}

2815
static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2816 2817
{
	static const struct ephy_info e_info_8168d_4[] = {
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		{ 0x0b, 0x0000,	0x0048 },
		{ 0x19, 0x0020,	0x0050 },
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		{ 0x0c, 0x0100,	0x0020 },
		{ 0x10, 0x0004,	0x0000 },
2822 2823
	};

2824
	rtl_set_def_aspm_entry_latency(tp);
2825

2826
	rtl_ephy_init(tp, e_info_8168d_4);
2827

2828
	rtl_enable_clock_request(tp);
2829 2830
}

2831
static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
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2832
{
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2833
	static const struct ephy_info e_info_8168e_1[] = {
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		{ 0x00, 0x0200,	0x0100 },
		{ 0x00, 0x0000,	0x0004 },
		{ 0x06, 0x0002,	0x0001 },
		{ 0x06, 0x0000,	0x0030 },
		{ 0x07, 0x0000,	0x2000 },
		{ 0x00, 0x0000,	0x0020 },
		{ 0x03, 0x5800,	0x2000 },
		{ 0x03, 0x0000,	0x0001 },
		{ 0x01, 0x0800,	0x1000 },
		{ 0x07, 0x0000,	0x4000 },
		{ 0x1e, 0x0000,	0x2000 },
		{ 0x19, 0xffff,	0xfe6c },
		{ 0x0a, 0x0000,	0x0040 }
	};

2849
	rtl_set_def_aspm_entry_latency(tp);
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2850

2851
	rtl_ephy_init(tp, e_info_8168e_1);
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2852

2853
	rtl_disable_clock_request(tp);
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2854 2855

	/* Reset tx FIFO pointer */
2856 2857
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
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2858

2859
	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
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2860 2861
}

2862
static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
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{
	static const struct ephy_info e_info_8168e_2[] = {
		{ 0x09, 0x0000,	0x0080 },
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		{ 0x19, 0x0000,	0x0224 },
		{ 0x00, 0x0000,	0x0004 },
		{ 0x0c, 0x3df0,	0x0200 },
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2869 2870
	};

2871
	rtl_set_def_aspm_entry_latency(tp);
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2872

2873
	rtl_ephy_init(tp, e_info_8168e_2);
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2874

2875
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2876
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2877
	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
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	rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
	rtl_eri_set_bits(tp, 0x1d0, BIT(1));
	rtl_reset_packet_filter(tp);
	rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2882 2883
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
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2884

2885
	rtl_disable_clock_request(tp);
2886

2887
	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
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2888

2889 2890
	rtl8168_config_eee_mac(tp);

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	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2894 2895

	rtl_hw_aspm_clkreq_enable(tp, true);
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2896 2897
}

2898
static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2899
{
2900
	rtl_set_def_aspm_entry_latency(tp);
2901

2902
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2903
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2904
	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2905
	rtl_reset_packet_filter(tp);
2906
	rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2907
	rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2908 2909
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2910

2911
	rtl_disable_clock_request(tp);
2912

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	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
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	rtl8168_config_eee_mac(tp);
2919 2920
}

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static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x08, 0x0001,	0x0002 },
		{ 0x09, 0x0000,	0x0080 },
2927
		{ 0x19, 0x0000,	0x0224 },
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		{ 0x00, 0x0000,	0x0008 },
2929
		{ 0x0c, 0x3df0,	0x0200 },
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	};

	rtl_hw_start_8168f(tp);

2934
	rtl_ephy_init(tp, e_info_8168f_1);
2935

2936
	rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
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}

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static void rtl_hw_start_8411(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x0f, 0xffff,	0x5200 },
2944
		{ 0x19, 0x0000,	0x0224 },
2945
		{ 0x00, 0x0000,	0x0008 },
2946
		{ 0x0c, 0x3df0,	0x0200 },
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	};

	rtl_hw_start_8168f(tp);
2950
	rtl_pcie_state_l2l3_disable(tp);
2951

2952
	rtl_ephy_init(tp, e_info_8168f_1);
2953

2954
	rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
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}

2957
static void rtl_hw_start_8168g(struct rtl8169_private *tp)
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2958
{
2959
	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2960
	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
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2961

2962
	rtl_set_def_aspm_entry_latency(tp);
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2963

2964
	rtl_reset_packet_filter(tp);
2965
	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
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2966

2967
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
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2968

2969 2970
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2971
	rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
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2972

2973 2974
	rtl8168_config_eee_mac(tp);

2975 2976
	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
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2977

2978
	rtl_pcie_state_l2l3_disable(tp);
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2979 2980
}

2981 2982 2983
static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168g_1[] = {
2984 2985
		{ 0x00, 0x0008,	0x0000 },
		{ 0x0c, 0x3ff0,	0x0820 },
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		{ 0x1e, 0x0000,	0x0001 },
		{ 0x19, 0x8000,	0x0000 }
	};

	rtl_hw_start_8168g(tp);

	/* disable aspm and clock request before access ephy */
2993
	rtl_hw_aspm_clkreq_enable(tp, false);
2994
	rtl_ephy_init(tp, e_info_8168g_1);
2995
	rtl_hw_aspm_clkreq_enable(tp, true);
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}

2998 2999 3000
static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168g_2[] = {
3001 3002 3003 3004 3005 3006 3007 3008 3009
		{ 0x00, 0x0008,	0x0000 },
		{ 0x0c, 0x3ff0,	0x0820 },
		{ 0x19, 0xffff,	0x7c00 },
		{ 0x1e, 0xffff,	0x20eb },
		{ 0x0d, 0xffff,	0x1666 },
		{ 0x00, 0xffff,	0x10a3 },
		{ 0x06, 0xffff,	0xf050 },
		{ 0x04, 0x0000,	0x0010 },
		{ 0x1d, 0x4000,	0x0000 },
3010 3011
	};

3012
	rtl_hw_start_8168g(tp);
3013 3014

	/* disable aspm and clock request before access ephy */
3015
	rtl_hw_aspm_clkreq_enable(tp, false);
3016
	rtl_ephy_init(tp, e_info_8168g_2);
3017 3018
}

3019 3020 3021
static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8411_2[] = {
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		{ 0x00, 0x0008,	0x0000 },
		{ 0x0c, 0x37d0,	0x0820 },
		{ 0x1e, 0x0000,	0x0001 },
		{ 0x19, 0x8021,	0x0000 },
		{ 0x1e, 0x0000,	0x2000 },
		{ 0x0d, 0x0100,	0x0200 },
		{ 0x00, 0x0000,	0x0080 },
		{ 0x06, 0x0000,	0x0010 },
		{ 0x04, 0x0000,	0x0010 },
		{ 0x1d, 0x0000,	0x4000 },
3032 3033
	};

3034
	rtl_hw_start_8168g(tp);
3035 3036

	/* disable aspm and clock request before access ephy */
3037
	rtl_hw_aspm_clkreq_enable(tp, false);
3038
	rtl_ephy_init(tp, e_info_8411_2);
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	/* The following Realtek-provided magic fixes an issue with the RX unit
	 * getting confused after the PHY having been powered-down.
	 */
	r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
	r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
	mdelay(3);
	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);

	r8168_mac_ocp_write(tp, 0xF800, 0xE008);
	r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
	r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
	r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
	r8168_mac_ocp_write(tp, 0xF808, 0xE027);
	r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
	r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
	r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
	r8168_mac_ocp_write(tp, 0xF810, 0xC602);
	r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
	r8168_mac_ocp_write(tp, 0xF814, 0x0000);
	r8168_mac_ocp_write(tp, 0xF816, 0xC502);
	r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
	r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
	r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
	r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
	r8168_mac_ocp_write(tp, 0xF820, 0x080A);
	r8168_mac_ocp_write(tp, 0xF822, 0x6420);
	r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
	r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
	r8168_mac_ocp_write(tp, 0xF828, 0xC516);
	r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
	r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
	r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
	r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
	r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
	r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
	r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
	r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
	r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
	r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
	r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
	r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
	r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
	r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
	r8168_mac_ocp_write(tp, 0xF846, 0xC404);
	r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
	r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
	r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
	r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
	r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
	r8168_mac_ocp_write(tp, 0xF852, 0xE434);
	r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
	r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
	r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
	r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
	r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
	r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
	r8168_mac_ocp_write(tp, 0xF860, 0xF007);
	r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
	r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
	r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
	r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
	r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
	r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
	r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
	r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
	r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
	r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
	r8168_mac_ocp_write(tp, 0xF876, 0xC516);
	r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
	r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
	r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
	r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
	r8168_mac_ocp_write(tp, 0xF880, 0xC512);
	r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
	r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
	r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
	r8168_mac_ocp_write(tp, 0xF888, 0x483F);
	r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
	r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
	r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
	r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
	r8168_mac_ocp_write(tp, 0xF892, 0xC505);
	r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
	r8168_mac_ocp_write(tp, 0xF896, 0xC502);
	r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
	r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
	r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
	r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
	r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
	r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
	r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
	r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
	r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
	r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
	r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
	r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
	r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
	r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
	r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
	r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
	r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
	r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
	r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
	r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
	r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
	r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
	r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
	r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
	r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
	r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
	r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
	r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
	r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
	r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
	r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
	r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
	r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
	r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
	r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);

	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);

	r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
	r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
	r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
	r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
	r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
	r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
	r8168_mac_ocp_write(tp, 0xFC36, 0x012D);

3176
	rtl_hw_aspm_clkreq_enable(tp, true);
3177 3178
}

3179 3180 3181 3182 3183 3184 3185
static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168h_1[] = {
		{ 0x1e, 0x0800,	0x0001 },
		{ 0x1d, 0x0000,	0x0800 },
		{ 0x05, 0xffff,	0x2089 },
		{ 0x06, 0xffff,	0x5881 },
3186
		{ 0x04, 0xffff,	0x854a },
3187 3188
		{ 0x01, 0xffff,	0x068b }
	};
3189
	int rg_saw_cnt;
3190 3191

	/* disable aspm and clock request before access ephy */
3192
	rtl_hw_aspm_clkreq_enable(tp, false);
3193
	rtl_ephy_init(tp, e_info_8168h_1);
3194

3195
	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3196
	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3197

3198
	rtl_set_def_aspm_entry_latency(tp);
3199

3200
	rtl_reset_packet_filter(tp);
3201

3202
	rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3203
	rtl_eri_set_bits(tp, 0xdc, 0x001c);
3204

3205
	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3206

3207
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3208

3209 3210
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3211

3212 3213
	rtl8168_config_eee_mac(tp);

3214 3215
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3216

3217
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3218

3219
	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3220

3221
	rtl_pcie_state_l2l3_disable(tp);
3222

3223
	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3224 3225 3226 3227 3228
	if (rg_saw_cnt > 0) {
		u16 sw_cnt_1ms_ini;

		sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
		sw_cnt_1ms_ini &= 0x0fff;
3229
		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3230 3231
	}

3232 3233 3234 3235
	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
	r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
	r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3236 3237 3238 3239 3240

	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3241 3242

	rtl_hw_aspm_clkreq_enable(tp, true);
3243 3244
}

3245 3246
static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
{
3247 3248
	rtl8168ep_stop_cmac(tp);

3249
	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3250
	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3251

3252
	rtl_set_def_aspm_entry_latency(tp);
3253

3254
	rtl_reset_packet_filter(tp);
3255

3256
	rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3257

3258
	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3259

3260
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3261

3262 3263
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3264

3265 3266
	rtl8168_config_eee_mac(tp);

3267
	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3268

3269
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3270

3271
	rtl_pcie_state_l2l3_disable(tp);
3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284
}

static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168ep_1[] = {
		{ 0x00, 0xffff,	0x10ab },
		{ 0x06, 0xffff,	0xf030 },
		{ 0x08, 0xffff,	0x2006 },
		{ 0x0d, 0xffff,	0x1666 },
		{ 0x0c, 0x3ff0,	0x0000 }
	};

	/* disable aspm and clock request before access ephy */
3285
	rtl_hw_aspm_clkreq_enable(tp, false);
3286
	rtl_ephy_init(tp, e_info_8168ep_1);
3287 3288

	rtl_hw_start_8168ep(tp);
3289 3290

	rtl_hw_aspm_clkreq_enable(tp, true);
3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301
}

static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168ep_2[] = {
		{ 0x00, 0xffff,	0x10a3 },
		{ 0x19, 0xffff,	0xfc00 },
		{ 0x1e, 0xffff,	0x20ea }
	};

	/* disable aspm and clock request before access ephy */
3302
	rtl_hw_aspm_clkreq_enable(tp, false);
3303
	rtl_ephy_init(tp, e_info_8168ep_2);
3304 3305 3306

	rtl_hw_start_8168ep(tp);

3307 3308
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3309 3310

	rtl_hw_aspm_clkreq_enable(tp, true);
3311 3312 3313 3314 3315
}

static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168ep_3[] = {
3316 3317 3318 3319
		{ 0x00, 0x0000,	0x0080 },
		{ 0x0d, 0x0100,	0x0200 },
		{ 0x19, 0x8021,	0x0000 },
		{ 0x1e, 0x0000,	0x2000 },
3320 3321 3322
	};

	/* disable aspm and clock request before access ephy */
3323
	rtl_hw_aspm_clkreq_enable(tp, false);
3324
	rtl_ephy_init(tp, e_info_8168ep_3);
3325 3326 3327

	rtl_hw_start_8168ep(tp);

3328 3329
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3330

3331 3332 3333
	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3334 3335

	rtl_hw_aspm_clkreq_enable(tp, true);
3336 3337
}

3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358
static void rtl_hw_start_8117(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8117[] = {
		{ 0x19, 0x0040,	0x1100 },
		{ 0x59, 0x0040,	0x1100 },
	};
	int rg_saw_cnt;

	rtl8168ep_stop_cmac(tp);

	/* disable aspm and clock request before access ephy */
	rtl_hw_aspm_clkreq_enable(tp, false);
	rtl_ephy_init(tp, e_info_8117);

	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);

	rtl_set_def_aspm_entry_latency(tp);

	rtl_reset_packet_filter(tp);

3359
	rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374

	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);

	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);

	rtl8168_config_eee_mac(tp);

	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);

	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);

3375
	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396

	rtl_pcie_state_l2l3_disable(tp);

	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
	if (rg_saw_cnt > 0) {
		u16 sw_cnt_1ms_ini;

		sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
	}

	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
	r8168_mac_ocp_write(tp, 0xea80, 0x0003);
	r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);

	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);

3397
	/* firmware is for MAC only */
3398
	r8169_apply_firmware(tp);
3399

3400 3401 3402
	rtl_hw_aspm_clkreq_enable(tp, true);
}

3403
static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3404
{
3405
	static const struct ephy_info e_info_8102e_1[] = {
3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416
		{ 0x01,	0, 0x6e65 },
		{ 0x02,	0, 0x091f },
		{ 0x03,	0, 0xc2f9 },
		{ 0x06,	0, 0xafb5 },
		{ 0x07,	0, 0x0e00 },
		{ 0x19,	0, 0xec80 },
		{ 0x01,	0, 0x2e65 },
		{ 0x01,	0, 0x6e65 }
	};
	u8 cfg1;

3417
	rtl_set_def_aspm_entry_latency(tp);
3418

3419
	RTL_W8(tp, DBG_REG, FIX_NAK_1);
3420

3421
	RTL_W8(tp, Config1,
3422
	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3423
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3424

3425
	cfg1 = RTL_R8(tp, Config1);
3426
	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3427
		RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3428

3429
	rtl_ephy_init(tp, e_info_8102e_1);
3430 3431
}

3432
static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3433
{
3434
	rtl_set_def_aspm_entry_latency(tp);
3435

3436 3437
	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3438 3439
}

3440
static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3441
{
3442
	rtl_hw_start_8102e_2(tp);
3443

3444
	rtl_ephy_write(tp, 0x03, 0xc2f9);
3445 3446
}

3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459
static void rtl_hw_start_8401(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8401[] = {
		{ 0x01,	0xffff, 0x6fe5 },
		{ 0x03,	0xffff, 0x0599 },
		{ 0x06,	0xffff, 0xaf25 },
		{ 0x07,	0xffff, 0x8e68 },
	};

	rtl_ephy_init(tp, e_info_8401);
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
}

3460
static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472
{
	static const struct ephy_info e_info_8105e_1[] = {
		{ 0x07,	0, 0x4000 },
		{ 0x19,	0, 0x0200 },
		{ 0x19,	0, 0x0020 },
		{ 0x1e,	0, 0x2000 },
		{ 0x03,	0, 0x0001 },
		{ 0x19,	0, 0x0100 },
		{ 0x19,	0, 0x0004 },
		{ 0x0a,	0, 0x0020 }
	};

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Francois Romieu committed
3473
	/* Force LAN exit from ASPM if Rx/Tx are not idle */
3474
	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3475

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Francois Romieu committed
3476
	/* Disable Early Tally Counter */
3477
	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3478

3479 3480
	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3481

3482
	rtl_ephy_init(tp, e_info_8105e_1);
hayeswang's avatar
hayeswang committed
3483

3484
	rtl_pcie_state_l2l3_disable(tp);
3485 3486
}

3487
static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3488
{
3489
	rtl_hw_start_8105e_1(tp);
3490
	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3491 3492
}

3493 3494 3495 3496 3497 3498 3499
static void rtl_hw_start_8402(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8402[] = {
		{ 0x19,	0xffff, 0xff64 },
		{ 0x1e,	0, 0x4000 }
	};

3500
	rtl_set_def_aspm_entry_latency(tp);
3501 3502

	/* Force LAN exit from ASPM if Rx/Tx are not idle */
3503
	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3504

3505
	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3506

3507
	rtl_ephy_init(tp, e_info_8402);
3508

3509
	rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3510
	rtl_reset_packet_filter(tp);
3511 3512
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3513
	rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
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hayeswang committed
3514

3515 3516 3517
	/* disable EEE */
	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);

3518
	rtl_pcie_state_l2l3_disable(tp);
3519 3520
}

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3521 3522
static void rtl_hw_start_8106(struct rtl8169_private *tp)
{
3523 3524
	rtl_hw_aspm_clkreq_enable(tp, false);

Hayes Wang's avatar
Hayes Wang committed
3525
	/* Force LAN exit from ASPM if Rx/Tx are not idle */
3526
	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
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Hayes Wang committed
3527

3528 3529 3530
	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
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3531

3532 3533
	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);

3534 3535 3536
	/* disable EEE */
	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);

3537
	rtl_pcie_state_l2l3_disable(tp);
3538
	rtl_hw_aspm_clkreq_enable(tp, true);
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Hayes Wang committed
3539 3540
}

3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568
DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
{
	return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
}

static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
{
	rtl_pcie_state_l2l3_disable(tp);

	RTL_W16(tp, 0x382, 0x221b);
	RTL_W8(tp, 0x4500, 0);
	RTL_W16(tp, 0x4800, 0);

	/* disable UPS */
	r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);

	RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);

	r8168_mac_ocp_write(tp, 0xc140, 0xffff);
	r8168_mac_ocp_write(tp, 0xc142, 0xffff);

	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);

	/* disable new tx descriptor format */
	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);

3569 3570 3571 3572 3573 3574 3575 3576 3577 3578
	if (tp->mac_version == RTL_GIGA_MAC_VER_63)
		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
	else
		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);

	if (tp->mac_version == RTL_GIGA_MAC_VER_63)
		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
	else
		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);

3579 3580 3581 3582 3583
	r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
	r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
	r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3584
	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3585
	r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3586
	r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3587 3588
	r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
	r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3589

3590 3591 3592 3593 3594 3595 3596 3597
	r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
	r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
	udelay(1);
	r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
	RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);

	r8168_mac_ocp_write(tp, 0xe098, 0xc302);

3598
	rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3599

3600 3601 3602 3603
	if (tp->mac_version == RTL_GIGA_MAC_VER_63)
		rtl8125b_config_eee_mac(tp);
	else
		rtl8125a_config_eee_mac(tp);
3604

3605 3606 3607 3608
	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
	udelay(10);
}

3609
static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3610
{
3611
	static const struct ephy_info e_info_8125a_1[] = {
3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642
		{ 0x01, 0xffff, 0xa812 },
		{ 0x09, 0xffff, 0x520c },
		{ 0x04, 0xffff, 0xd000 },
		{ 0x0d, 0xffff, 0xf702 },
		{ 0x0a, 0xffff, 0x8653 },
		{ 0x06, 0xffff, 0x001e },
		{ 0x08, 0xffff, 0x3595 },
		{ 0x20, 0xffff, 0x9455 },
		{ 0x21, 0xffff, 0x99ff },
		{ 0x02, 0xffff, 0x6046 },
		{ 0x29, 0xffff, 0xfe00 },
		{ 0x23, 0xffff, 0xab62 },

		{ 0x41, 0xffff, 0xa80c },
		{ 0x49, 0xffff, 0x520c },
		{ 0x44, 0xffff, 0xd000 },
		{ 0x4d, 0xffff, 0xf702 },
		{ 0x4a, 0xffff, 0x8653 },
		{ 0x46, 0xffff, 0x001e },
		{ 0x48, 0xffff, 0x3595 },
		{ 0x60, 0xffff, 0x9455 },
		{ 0x61, 0xffff, 0x99ff },
		{ 0x42, 0xffff, 0x6046 },
		{ 0x69, 0xffff, 0xfe00 },
		{ 0x63, 0xffff, 0xab62 },
	};

	rtl_set_def_aspm_entry_latency(tp);

	/* disable aspm and clock request before access ephy */
	rtl_hw_aspm_clkreq_enable(tp, false);
3643
	rtl_ephy_init(tp, e_info_8125a_1);
3644 3645

	rtl_hw_start_8125_common(tp);
3646
	rtl_hw_aspm_clkreq_enable(tp, true);
3647 3648
}

3649
static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3650
{
3651
	static const struct ephy_info e_info_8125a_2[] = {
3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670
		{ 0x04, 0xffff, 0xd000 },
		{ 0x0a, 0xffff, 0x8653 },
		{ 0x23, 0xffff, 0xab66 },
		{ 0x20, 0xffff, 0x9455 },
		{ 0x21, 0xffff, 0x99ff },
		{ 0x29, 0xffff, 0xfe04 },

		{ 0x44, 0xffff, 0xd000 },
		{ 0x4a, 0xffff, 0x8653 },
		{ 0x63, 0xffff, 0xab66 },
		{ 0x60, 0xffff, 0x9455 },
		{ 0x61, 0xffff, 0x99ff },
		{ 0x69, 0xffff, 0xfe04 },
	};

	rtl_set_def_aspm_entry_latency(tp);

	/* disable aspm and clock request before access ephy */
	rtl_hw_aspm_clkreq_enable(tp, false);
3671
	rtl_ephy_init(tp, e_info_8125a_2);
3672 3673

	rtl_hw_start_8125_common(tp);
3674
	rtl_hw_aspm_clkreq_enable(tp, true);
3675 3676
}

3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696
static void rtl_hw_start_8125b(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8125b[] = {
		{ 0x0b, 0xffff, 0xa908 },
		{ 0x1e, 0xffff, 0x20eb },
		{ 0x4b, 0xffff, 0xa908 },
		{ 0x5e, 0xffff, 0x20eb },
		{ 0x22, 0x0030, 0x0020 },
		{ 0x62, 0x0030, 0x0020 },
	};

	rtl_set_def_aspm_entry_latency(tp);
	rtl_hw_aspm_clkreq_enable(tp, false);

	rtl_ephy_init(tp, e_info_8125b);
	rtl_hw_start_8125_common(tp);

	rtl_hw_aspm_clkreq_enable(tp, true);
}

3697 3698 3699 3700 3701 3702 3703
static void rtl_hw_config(struct rtl8169_private *tp)
{
	static const rtl_generic_fct hw_configs[] = {
		[RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
		[RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
		[RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
		[RTL_GIGA_MAC_VER_10] = NULL,
3704 3705
		[RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
		[RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3706
		[RTL_GIGA_MAC_VER_13] = NULL,
3707
		[RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3708
		[RTL_GIGA_MAC_VER_16] = NULL,
3709
		[RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722
		[RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
		[RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
		[RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
		[RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
		[RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
		[RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
		[RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
		[RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
		[RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
		[RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
		[RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
		[RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
		[RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3723
		[RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743
		[RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
		[RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
		[RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
		[RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
		[RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
		[RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
		[RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
		[RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
		[RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
		[RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
		[RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
		[RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
		[RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
		[RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
		[RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
		[RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
		[RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
		[RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
		[RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
		[RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3744
		[RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3745 3746
		[RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
		[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3747
		[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3748 3749 3750 3751 3752 3753
	};

	if (hw_configs[tp->mac_version])
		hw_configs[tp->mac_version](tp);
}

3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764
static void rtl_hw_start_8125(struct rtl8169_private *tp)
{
	int i;

	/* disable interrupt coalescing */
	for (i = 0xa00; i < 0xb00; i += 4)
		RTL_W32(tp, i, 0);

	rtl_hw_config(tp);
}

3765
static void rtl_hw_start_8168(struct rtl8169_private *tp)
3766
{
3767 3768 3769 3770
	if (rtl_is_8168evl_up(tp))
		RTL_W8(tp, MaxTxPacketSize, EarlySize);
	else
		RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3771

3772
	rtl_hw_config(tp);
3773 3774 3775

	/* disable interrupt coalescing */
	RTL_W16(tp, IntrMitigate, 0x0000);
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}

3778 3779 3780 3781 3782 3783 3784
static void rtl_hw_start_8169(struct rtl8169_private *tp)
{
	RTL_W8(tp, EarlyTxThres, NoEarlyTx);

	tp->cp_cmd |= PCIMulRW;

	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3785 3786
	    tp->mac_version == RTL_GIGA_MAC_VER_03)
		tp->cp_cmd |= EnAnaPLL;
3787 3788 3789

	RTL_W16(tp, CPlusCmd, tp->cp_cmd);

3790
	rtl8169_set_magic_reg(tp);
3791

3792 3793
	/* disable interrupt coalescing */
	RTL_W16(tp, IntrMitigate, 0x0000);
3794 3795 3796 3797 3798 3799 3800 3801 3802 3803
}

static void rtl_hw_start(struct  rtl8169_private *tp)
{
	rtl_unlock_config_regs(tp);

	RTL_W16(tp, CPlusCmd, tp->cp_cmd);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		rtl_hw_start_8169(tp);
3804 3805
	else if (rtl_is_8125(tp))
		rtl_hw_start_8125(tp);
3806 3807 3808 3809 3810 3811 3812
	else
		rtl_hw_start_8168(tp);

	rtl_set_rx_max_size(tp);
	rtl_set_rx_tx_desc_registers(tp);
	rtl_lock_config_regs(tp);

3813
	rtl_jumbo_config(tp);
3814

3815
	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3816 3817
	rtl_pci_commit(tp);

3818 3819 3820
	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
	rtl_init_rxcfg(tp);
	rtl_set_tx_config_registers(tp);
3821
	rtl_set_rx_config_features(tp, tp->dev->features);
3822 3823 3824 3825
	rtl_set_rx_mode(tp->dev);
	rtl_irq_enable(tp);
}

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3826 3827
static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
{
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3828 3829
	struct rtl8169_private *tp = netdev_priv(dev);

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3830
	dev->mtu = new_mtu;
3831
	netdev_update_features(dev);
3832
	rtl_jumbo_config(tp);
3833

3834 3835 3836 3837 3838 3839 3840 3841 3842
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_61:
	case RTL_GIGA_MAC_VER_63:
		rtl8125_set_eee_txidle_timer(tp);
		break;
	default:
		break;
	}

3843
	return 0;
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}

3846
static void rtl8169_mark_to_asic(struct RxDesc *desc)
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{
	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;

3850
	desc->opts2 = 0;
3851 3852
	/* Force memory writes to complete before releasing descriptor */
	dma_wmb();
3853
	WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
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}

3856 3857
static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
					  struct RxDesc *desc)
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3858
{
3859
	struct device *d = tp_to_dev(tp);
3860
	int node = dev_to_node(d);
3861 3862
	dma_addr_t mapping;
	struct page *data;
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3863

3864
	data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3865 3866
	if (!data)
		return NULL;
3867

3868
	mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3869
	if (unlikely(dma_mapping_error(d, mapping))) {
3870
		netdev_err(tp->dev, "Failed to map RX DMA!\n");
3871 3872
		__free_pages(data, get_order(R8169_RX_BUF_SIZE));
		return NULL;
3873
	}
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3875 3876
	desc->addr = cpu_to_le64(mapping);
	rtl8169_mark_to_asic(desc);
3877

3878
	return data;
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}

static void rtl8169_rx_clear(struct rtl8169_private *tp)
{
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	unsigned int i;
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3885 3886 3887 3888 3889 3890
	for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
		dma_unmap_page(tp_to_dev(tp),
			       le64_to_cpu(tp->RxDescArray[i].addr),
			       R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
		__free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
		tp->Rx_databuff[i] = NULL;
3891 3892
		tp->RxDescArray[i].addr = 0;
		tp->RxDescArray[i].opts1 = 0;
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	}
}

3896 3897 3898
static int rtl8169_rx_fill(struct rtl8169_private *tp)
{
	unsigned int i;
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3900
	for (i = 0; i < NUM_RX_DESC; i++) {
3901
		struct page *data;
3902

3903
		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3904
		if (!data) {
3905 3906
			rtl8169_rx_clear(tp);
			return -ENOMEM;
3907 3908
		}
		tp->Rx_databuff[i] = data;
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	}

3911 3912
	/* mark as last descriptor in the ring */
	tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3913

3914
	return 0;
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}

3917
static int rtl8169_init_ring(struct rtl8169_private *tp)
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{
	rtl8169_init_ring_indexes(tp);

3921 3922
	memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
	memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
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3923

3924
	return rtl8169_rx_fill(tp);
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}

3927
static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
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{
3929 3930
	struct ring_info *tx_skb = tp->tx_skb + entry;
	struct TxDesc *desc = tp->TxDescArray + entry;
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3932 3933
	dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
			 DMA_TO_DEVICE);
3934 3935
	memset(desc, 0, sizeof(*desc));
	memset(tx_skb, 0, sizeof(*tx_skb));
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}

3938 3939
static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
				   unsigned int n)
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{
	unsigned int i;

3943 3944
	for (i = 0; i < n; i++) {
		unsigned int entry = (start + i) % NUM_TX_DESC;
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		struct ring_info *tx_skb = tp->tx_skb + entry;
		unsigned int len = tx_skb->len;

		if (len) {
			struct sk_buff *skb = tx_skb->skb;

3951
			rtl8169_unmap_tx_skb(tp, entry);
3952
			if (skb)
3953
				dev_consume_skb_any(skb);
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		}
	}
3956 3957 3958 3959 3960
}

static void rtl8169_tx_clear(struct rtl8169_private *tp)
{
	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3961
	netdev_reset_queue(tp->dev);
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}

3964
static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3965
{
3966 3967
	napi_disable(&tp->napi);

3968
	/* Give a racing hard_start_xmit a few cycles to complete. */
3969
	synchronize_net();
3970 3971 3972 3973 3974 3975

	/* Disable interrupts */
	rtl8169_irq_mask_and_ack(tp);

	rtl_rx_close(tp);

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	if (going_down && tp->dev->wol_enabled)
		goto no_reset;

3979 3980 3981 3982 3983 3984 3985 3986 3987 3988
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
		break;
	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
		break;
3989
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3990 3991 3992 3993 3994 3995 3996 3997 3998 3999
		rtl_enable_rxdvgate(tp);
		fsleep(2000);
		break;
	default:
		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
		fsleep(100);
		break;
	}

	rtl_hw_reset(tp);
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no_reset:
4001 4002 4003 4004
	rtl8169_tx_clear(tp);
	rtl8169_init_ring_indexes(tp);
}

4005
static void rtl_reset_work(struct rtl8169_private *tp)
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{
4007
	int i;
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4009
	netif_stop_queue(tp->dev);
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4011
	rtl8169_cleanup(tp, false);
4012

4013
	for (i = 0; i < NUM_RX_DESC; i++)
4014
		rtl8169_mark_to_asic(tp->RxDescArray + i);
4015

4016
	napi_enable(&tp->napi);
4017
	rtl_hw_start(tp);
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}

4020
static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
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{
4022 4023 4024
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
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}

4027 4028
static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
			  void *addr, unsigned int entry, bool desc_own)
4029
{
4030 4031 4032 4033 4034 4035 4036 4037 4038 4039
	struct TxDesc *txd = tp->TxDescArray + entry;
	struct device *d = tp_to_dev(tp);
	dma_addr_t mapping;
	u32 opts1;
	int ret;

	mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
	ret = dma_mapping_error(d, mapping);
	if (unlikely(ret)) {
		if (net_ratelimit())
4040
			netdev_err(tp->dev, "Failed to map TX data!\n");
4041 4042 4043 4044 4045
		return ret;
	}

	txd->addr = cpu_to_le64(mapping);
	txd->opts2 = cpu_to_le32(opts[1]);
4046

4047
	opts1 = opts[0] | len;
4048
	if (entry == NUM_TX_DESC - 1)
4049 4050 4051 4052
		opts1 |= RingEnd;
	if (desc_own)
		opts1 |= DescOwn;
	txd->opts1 = cpu_to_le32(opts1);
4053

4054 4055 4056
	tp->tx_skb[entry].len = len;

	return 0;
4057 4058
}

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4059
static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4060
			      const u32 *opts, unsigned int entry)
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{
	struct skb_shared_info *info = skb_shinfo(skb);
4063
	unsigned int cur_frag;
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4064 4065

	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4066
		const skb_frag_t *frag = info->frags + cur_frag;
4067 4068
		void *addr = skb_frag_address(frag);
		u32 len = skb_frag_size(frag);
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4069 4070 4071

		entry = (entry + 1) % NUM_TX_DESC;

4072
		if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4073
			goto err_out;
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4074 4075
	}

4076
	return 0;
4077 4078 4079 4080

err_out:
	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
	return -EIO;
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4081 4082
}

4083
static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp)
4084
{
4085 4086 4087 4088 4089 4090 4091 4092 4093
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_34:
	case RTL_GIGA_MAC_VER_60:
	case RTL_GIGA_MAC_VER_61:
	case RTL_GIGA_MAC_VER_63:
		return true;
	default:
		return false;
	}
4094 4095
}

4096
static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
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4097
{
4098 4099
	u32 mss = skb_shinfo(skb)->gso_size;

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4100 4101
	if (mss) {
		opts[0] |= TD_LSO;
4102
		opts[0] |= mss << TD0_MSS_SHIFT;
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4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
		const struct iphdr *ip = ip_hdr(skb);

		if (ip->protocol == IPPROTO_TCP)
			opts[0] |= TD0_IP_CS | TD0_TCP_CS;
		else if (ip->protocol == IPPROTO_UDP)
			opts[0] |= TD0_IP_CS | TD0_UDP_CS;
		else
			WARN_ON_ONCE(1);
	}
}

static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
				struct sk_buff *skb, u32 *opts)
{
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4118
	u32 transport_offset = (u32)skb_transport_offset(skb);
4119 4120
	struct skb_shared_info *shinfo = skb_shinfo(skb);
	u32 mss = shinfo->gso_size;
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4121 4122

	if (mss) {
4123
		if (shinfo->gso_type & SKB_GSO_TCPV4) {
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4124
			opts[0] |= TD1_GTSENV4;
4125
		} else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4126
			if (skb_cow_head(skb, 0))
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4127 4128
				return false;

4129
			tcp_v6_gso_csum_prep(skb);
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4130
			opts[0] |= TD1_GTSENV6;
4131
		} else {
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4132 4133 4134
			WARN_ON_ONCE(1);
		}

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4135
		opts[0] |= transport_offset << GTTCPHO_SHIFT;
4136
		opts[1] |= mss << TD1_MSS_SHIFT;
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4137
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
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4138
		u8 ip_protocol;
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4139

4140
		switch (vlan_get_protocol(skb)) {
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4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159
		case htons(ETH_P_IP):
			opts[1] |= TD1_IPv4_CS;
			ip_protocol = ip_hdr(skb)->protocol;
			break;

		case htons(ETH_P_IPV6):
			opts[1] |= TD1_IPv6_CS;
			ip_protocol = ipv6_hdr(skb)->nexthdr;
			break;

		default:
			ip_protocol = IPPROTO_RAW;
			break;
		}

		if (ip_protocol == IPPROTO_TCP)
			opts[1] |= TD1_TCP_CS;
		else if (ip_protocol == IPPROTO_UDP)
			opts[1] |= TD1_UDP_CS;
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4160 4161
		else
			WARN_ON_ONCE(1);
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4162 4163

		opts[1] |= transport_offset << TCPHO_SHIFT;
4164
	} else {
4165
		if (unlikely(skb->len < ETH_ZLEN && rtl_test_hw_pad_bug(tp)))
4166
			return !eth_skb_pad(skb);
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4167
	}
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4168

4169
	return true;
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4170 4171
}

4172 4173 4174 4175 4176 4177 4178 4179 4180
static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
			       unsigned int nr_frags)
{
	unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;

	/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
	return slots_avail > nr_frags;
}

4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192
/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
	case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
		return false;
	default:
		return true;
	}
}

4193 4194 4195 4196 4197 4198 4199 4200
static void rtl8169_doorbell(struct rtl8169_private *tp)
{
	if (rtl_is_8125(tp))
		RTL_W16(tp, TxPoll_8125, BIT(0));
	else
		RTL_W8(tp, TxPoll, NPQ);
}

4201 4202
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev)
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4203
{
4204
	unsigned int frags = skb_shinfo(skb)->nr_frags;
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4205
	struct rtl8169_private *tp = netdev_priv(dev);
4206
	unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4207 4208 4209 4210 4211
	struct TxDesc *txd_first, *txd_last;
	bool stop_queue, door_bell;
	u32 opts[2];

	txd_first = tp->TxDescArray + entry;
4212

4213
	if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4214 4215
		if (net_ratelimit())
			netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4216
		goto err_stop_0;
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4217 4218
	}

4219
	if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4220 4221
		goto err_stop_0;

4222
	opts[1] = rtl8169_tx_vlan_tag(skb);
4223
	opts[0] = 0;
4224

4225
	if (!rtl_chip_supports_csum_v2(tp))
4226
		rtl8169_tso_csum_v1(skb, opts);
4227
	else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4228 4229
		goto err_dma_0;

4230 4231 4232
	if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
				    entry, false)))
		goto err_dma_0;
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4233

4234 4235
	if (frags) {
		if (rtl8169_xmit_frags(tp, skb, opts, entry))
4236
			goto err_dma_1;
4237
		entry = (entry + frags) % NUM_TX_DESC;
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4238 4239
	}

4240 4241 4242
	txd_last = tp->TxDescArray + entry;
	txd_last->opts1 |= cpu_to_le32(LastFrag);
	tp->tx_skb[entry].skb = skb;
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4243

4244 4245
	skb_tx_timestamp(skb);

4246 4247
	/* Force memory writes to complete before releasing descriptor */
	dma_wmb();
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4248

4249 4250
	door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());

4251
	txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
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4252

4253 4254
	/* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
	smp_wmb();
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4255

4256 4257
	tp->cur_tx += frags + 1;

4258 4259
	stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
	if (unlikely(stop_queue)) {
4260 4261 4262 4263 4264
		/* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
		 * not miss a ring update when it notices a stopped queue.
		 */
		smp_wmb();
		netif_stop_queue(dev);
4265
		door_bell = true;
4266 4267 4268
	}

	if (door_bell)
4269
		rtl8169_doorbell(tp);
4270 4271

	if (unlikely(stop_queue)) {
4272 4273 4274 4275 4276 4277 4278
		/* Sync with rtl_tx:
		 * - publish queue status and cur_tx ring index (write barrier)
		 * - refresh dirty_tx ring index (read barrier).
		 * May the current thread have a pessimistic view of the ring
		 * status and forget to wake up queue, a racing rtl_tx thread
		 * can't.
		 */
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4279
		smp_mb();
4280
		if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4281
			netif_start_queue(dev);
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4282 4283
	}

4284
	return NETDEV_TX_OK;
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4285

4286
err_dma_1:
4287
	rtl8169_unmap_tx_skb(tp, entry);
4288
err_dma_0:
4289
	dev_kfree_skb_any(skb);
4290 4291 4292 4293
	dev->stats.tx_dropped++;
	return NETDEV_TX_OK;

err_stop_0:
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4294
	netif_stop_queue(dev);
4295
	dev->stats.tx_dropped++;
4296
	return NETDEV_TX_BUSY;
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4297 4298
}

4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329
static unsigned int rtl_last_frag_len(struct sk_buff *skb)
{
	struct skb_shared_info *info = skb_shinfo(skb);
	unsigned int nr_frags = info->nr_frags;

	if (!nr_frags)
		return UINT_MAX;

	return skb_frag_size(info->frags + nr_frags - 1);
}

/* Workaround for hw issues with TSO on RTL8168evl */
static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
					    netdev_features_t features)
{
	/* IPv4 header has options field */
	if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
	    ip_hdrlen(skb) > sizeof(struct iphdr))
		features &= ~NETIF_F_ALL_TSO;

	/* IPv4 TCP header has options field */
	else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
		 tcp_hdrlen(skb) > sizeof(struct tcphdr))
		features &= ~NETIF_F_ALL_TSO;

	else if (rtl_last_frag_len(skb) <= 6)
		features &= ~NETIF_F_ALL_TSO;

	return features;
}

4330 4331 4332 4333 4334 4335 4336 4337
static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
						struct net_device *dev,
						netdev_features_t features)
{
	int transport_offset = skb_transport_offset(skb);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (skb_is_gso(skb)) {
4338 4339 4340
		if (tp->mac_version == RTL_GIGA_MAC_VER_34)
			features = rtl8168evl_fix_tso(skb, features);

4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365
		if (transport_offset > GTTCPHO_MAX &&
		    rtl_chip_supports_csum_v2(tp))
			features &= ~NETIF_F_ALL_TSO;
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
		if (skb->len < ETH_ZLEN) {
			switch (tp->mac_version) {
			case RTL_GIGA_MAC_VER_11:
			case RTL_GIGA_MAC_VER_12:
			case RTL_GIGA_MAC_VER_17:
			case RTL_GIGA_MAC_VER_34:
				features &= ~NETIF_F_CSUM_MASK;
				break;
			default:
				break;
			}
		}

		if (transport_offset > TCPHO_MAX &&
		    rtl_chip_supports_csum_v2(tp))
			features &= ~NETIF_F_CSUM_MASK;
	}

	return vlan_features_check(skb, features);
}

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4366 4367 4368 4369
static void rtl8169_pcierr_interrupt(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
4370 4371
	int pci_status_errs;
	u16 pci_cmd;
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4372 4373 4374

	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);

4375 4376
	pci_status_errs = pci_status_get_and_clear_errors(pdev);

4377 4378 4379
	if (net_ratelimit())
		netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
			   pci_cmd, pci_status_errs);
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4380 4381 4382
	/*
	 * The recovery sequence below admits a very elaborated explanation:
	 * - it seems to work;
4383 4384
	 * - I did not see what else could be done;
	 * - it makes iop3xx happy.
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4385 4386 4387
	 *
	 * Feel free to adjust to your needs.
	 */
4388
	if (pdev->broken_parity_status)
4389 4390 4391 4392 4393
		pci_cmd &= ~PCI_COMMAND_PARITY;
	else
		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;

	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
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4394

4395
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
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4396 4397
}

4398 4399
static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
		   int budget)
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4400
{
4401
	unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
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4402 4403 4404 4405

	dirty_tx = tp->dirty_tx;
	smp_rmb();

4406
	for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
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4407
		unsigned int entry = dirty_tx % NUM_TX_DESC;
4408
		struct sk_buff *skb = tp->tx_skb[entry].skb;
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4409 4410 4411 4412 4413 4414
		u32 status;

		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
		if (status & DescOwn)
			break;

4415 4416
		rtl8169_unmap_tx_skb(tp, entry);

4417
		if (skb) {
4418
			pkts_compl++;
4419 4420
			bytes_compl += skb->len;
			napi_consume_skb(skb, budget);
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4421 4422 4423 4424 4425
		}
		dirty_tx++;
	}

	if (tp->dirty_tx != dirty_tx) {
4426 4427
		netdev_completed_queue(dev, pkts_compl, bytes_compl);

4428
		rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl);
4429

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4430
		tp->dirty_tx = dirty_tx;
4431 4432 4433 4434 4435 4436 4437
		/* Sync with rtl8169_start_xmit:
		 * - publish dirty_tx ring index (write barrier)
		 * - refresh cur_tx ring index and queue status (read barrier)
		 * May the current thread miss the stopped queue condition,
		 * a racing xmit thread can only have a right view of the
		 * ring status.
		 */
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4438
		smp_mb();
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4439
		if (netif_queue_stopped(dev) &&
4440
		    rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
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4441 4442
			netif_wake_queue(dev);
		}
4443 4444 4445 4446 4447 4448
		/*
		 * 8168 hack: TxPoll requests are lost when the Tx packets are
		 * too close. Let's kick an extra TxPoll request when a burst
		 * of start_xmit activity is detected (if it is not detected,
		 * it is slow enough). -- FR
		 */
4449
		if (tp->cur_tx != dirty_tx)
4450
			rtl8169_doorbell(tp);
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4451 4452 4453
	}
}

4454 4455 4456 4457 4458
static inline int rtl8169_fragmented_frame(u32 status)
{
	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
}

4459
static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
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4460 4461 4462 4463
{
	u32 status = opts1 & RxProtoMask;

	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
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4464
	    ((status == RxProtoUDP) && !(opts1 & UDPFail)))
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4465 4466
		skb->ip_summed = CHECKSUM_UNNECESSARY;
	else
4467
		skb_checksum_none_assert(skb);
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4468 4469
}

4470
static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
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4471
{
4472 4473
	unsigned int cur_rx, rx_left, count;
	struct device *d = tp_to_dev(tp);
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	cur_rx = tp->cur_rx;

4477
	for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4478
		unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4479
		struct RxDesc *desc = tp->RxDescArray + entry;
4480 4481 4482
		struct sk_buff *skb;
		const void *rx_buf;
		dma_addr_t addr;
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4483 4484
		u32 status;

4485
		status = le32_to_cpu(desc->opts1);
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4486 4487
		if (status & DescOwn)
			break;
4488 4489 4490 4491 4492 4493 4494

		/* This barrier is needed to keep us from reading
		 * any other fields out of the Rx descriptor until
		 * we know the status of DescOwn
		 */
		dma_rmb();

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4495
		if (unlikely(status & RxRES)) {
4496 4497 4498
			if (net_ratelimit())
				netdev_warn(dev, "Rx ERROR. status = %08x\n",
					    status);
4499
			dev->stats.rx_errors++;
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4500
			if (status & (RxRWT | RxRUNT))
4501
				dev->stats.rx_length_errors++;
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4502
			if (status & RxCRC)
4503
				dev->stats.rx_crc_errors++;
4504

4505
			if (!(dev->features & NETIF_F_RXALL))
4506
				goto release_descriptor;
4507 4508 4509
			else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
				goto release_descriptor;
		}
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4510

4511 4512 4513
		pkt_size = status & GENMASK(13, 0);
		if (likely(!(dev->features & NETIF_F_RXFCS)))
			pkt_size -= ETH_FCS_LEN;
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4514

4515 4516 4517 4518 4519 4520 4521 4522
		/* The driver does not support incoming fragmented frames.
		 * They are seen as a symptom of over-mtu sized frames.
		 */
		if (unlikely(rtl8169_fragmented_frame(status))) {
			dev->stats.rx_dropped++;
			dev->stats.rx_length_errors++;
			goto release_descriptor;
		}
4523

4524 4525 4526 4527 4528
		skb = napi_alloc_skb(&tp->napi, pkt_size);
		if (unlikely(!skb)) {
			dev->stats.rx_dropped++;
			goto release_descriptor;
		}
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4529

4530 4531
		addr = le64_to_cpu(desc->addr);
		rx_buf = page_address(tp->Rx_databuff[entry]);
4532

4533 4534 4535 4536 4537 4538
		dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
		prefetch(rx_buf);
		skb_copy_to_linear_data(skb, rx_buf, pkt_size);
		skb->tail += pkt_size;
		skb->len = pkt_size;
		dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4539

4540 4541 4542 4543 4544 4545 4546 4547 4548 4549
		rtl8169_rx_csum(skb, status);
		skb->protocol = eth_type_trans(skb, dev);

		rtl8169_rx_vlan_tag(desc, skb);

		if (skb->pkt_type == PACKET_MULTICAST)
			dev->stats.multicast++;

		napi_gro_receive(&tp->napi, skb);

4550
		rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size);
4551
release_descriptor:
4552
		rtl8169_mark_to_asic(desc);
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4553 4554 4555 4556 4557 4558 4559 4560
	}

	count = cur_rx - tp->cur_rx;
	tp->cur_rx = cur_rx;

	return count;
}

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4561
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
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4562
{
4563
	struct rtl8169_private *tp = dev_instance;
4564
	u32 status = rtl_get_events(tp);
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4565

4566
	if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4567
		return IRQ_NONE;
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4568

4569 4570 4571 4572
	if (unlikely(status & SYSErr)) {
		rtl8169_pcierr_interrupt(tp->dev);
		goto out;
	}
4573

4574 4575
	if (status & LinkChg)
		phy_mac_interrupt(tp->phydev);
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4576

4577 4578 4579
	if (unlikely(status & RxFIFOOver &&
	    tp->mac_version == RTL_GIGA_MAC_VER_11)) {
		netif_stop_queue(tp->dev);
4580
		rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4581
	}
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4582

4583
	rtl_irq_disable(tp);
4584
	napi_schedule(&tp->napi);
4585 4586
out:
	rtl_ack_events(tp, status);
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4587

4588
	return IRQ_HANDLED;
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4589 4590
}

4591 4592 4593 4594
static void rtl_task(struct work_struct *work)
{
	struct rtl8169_private *tp =
		container_of(work, struct rtl8169_private, wk.work);
4595

4596
	rtnl_lock();
4597

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4598
	if (!netif_running(tp->dev) ||
4599
	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4600 4601
		goto out_unlock;

4602
	if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
Heiner Kallweit's avatar
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4603
		rtl_reset_work(tp);
4604 4605
		netif_wake_queue(tp->dev);
	}
4606
out_unlock:
4607
	rtnl_unlock();
4608 4609
}

4610
static int rtl8169_poll(struct napi_struct *napi, int budget)
Linus Torvalds's avatar
Linus Torvalds committed
4611
{
4612 4613
	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
	struct net_device *dev = tp->dev;
4614
	int work_done;
4615

4616
	work_done = rtl_rx(dev, tp, (u32) budget);
4617

4618
	rtl_tx(dev, tp, budget);
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4619

4620
	if (work_done < budget && napi_complete_done(napi, work_done))
4621
		rtl_irq_enable(tp);
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Linus Torvalds committed
4622

4623
	return work_done;
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4624 4625
}

4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637
static void r8169_phylink_handler(struct net_device *ndev)
{
	struct rtl8169_private *tp = netdev_priv(ndev);

	if (netif_carrier_ok(ndev)) {
		rtl_link_chg_patch(tp);
		pm_request_resume(&tp->pci_dev->dev);
	} else {
		pm_runtime_idle(&tp->pci_dev->dev);
	}

	if (net_ratelimit())
4638
		phy_print_status(tp->phydev);
4639 4640 4641 4642
}

static int r8169_phy_connect(struct rtl8169_private *tp)
{
4643
	struct phy_device *phydev = tp->phydev;
4644 4645 4646
	phy_interface_t phy_mode;
	int ret;

4647
	phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4648 4649 4650 4651 4652 4653 4654
		   PHY_INTERFACE_MODE_MII;

	ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
				 phy_mode);
	if (ret)
		return ret;

4655
	if (!tp->supports_gmii)
4656 4657
		phy_set_max_speed(phydev, SPEED_100);

4658
	phy_support_asym_pause(phydev);
4659 4660 4661 4662 4663 4664

	phy_attached_info(phydev);

	return 0;
}

4665
static void rtl8169_down(struct rtl8169_private *tp)
Linus Torvalds's avatar
Linus Torvalds committed
4666
{
4667 4668
	/* Clear all task flags */
	bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4669

4670
	phy_stop(tp->phydev);
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4671

4672 4673
	rtl8169_update_counters(tp);

4674
	rtl8169_cleanup(tp, true);
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4675

françois romieu's avatar
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4676
	rtl_pll_power_down(tp);
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4677 4678
}

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4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689
static void rtl8169_up(struct rtl8169_private *tp)
{
	rtl_pll_power_up(tp);
	rtl8169_init_phy(tp);
	napi_enable(&tp->napi);
	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
	rtl_reset_work(tp);

	phy_start(tp->phydev);
}

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4690 4691 4692 4693 4694
static int rtl8169_close(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;

4695 4696
	pm_runtime_get_sync(&pdev->dev);

4697 4698 4699
	netif_stop_queue(dev);
	rtl8169_down(tp);
	rtl8169_rx_clear(tp);
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4700

4701 4702
	cancel_work_sync(&tp->wk.work);

4703
	phy_disconnect(tp->phydev);
4704

4705
	free_irq(pci_irq_vector(pdev, 0), tp);
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4706

4707 4708 4709 4710
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
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4711 4712 4713
	tp->TxDescArray = NULL;
	tp->RxDescArray = NULL;

4714 4715
	pm_runtime_put_sync(&pdev->dev);

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4716 4717 4718
	return 0;
}

4719 4720 4721 4722 4723
#ifdef CONFIG_NET_POLL_CONTROLLER
static void rtl8169_netpoll(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

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Ville Syrjälä committed
4724
	rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4725 4726 4727
}
#endif

4728 4729 4730 4731 4732 4733 4734 4735 4736
static int rtl_open(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
	int retval = -ENOMEM;

	pm_runtime_get_sync(&pdev->dev);

	/*
4737
	 * Rx and Tx descriptors needs 256 bytes alignment.
4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749
	 * dma_alloc_coherent provides more.
	 */
	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
					     &tp->TxPhyAddr, GFP_KERNEL);
	if (!tp->TxDescArray)
		goto err_pm_runtime_put;

	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
					     &tp->RxPhyAddr, GFP_KERNEL);
	if (!tp->RxDescArray)
		goto err_free_tx_0;

4750
	retval = rtl8169_init_ring(tp);
4751 4752 4753 4754 4755
	if (retval < 0)
		goto err_free_rx_1;

	rtl_request_firmware(tp);

4756
	retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4757
			     IRQF_SHARED, dev->name, tp);
4758 4759 4760
	if (retval < 0)
		goto err_release_fw_2;

4761 4762 4763 4764
	retval = r8169_phy_connect(tp);
	if (retval)
		goto err_free_irq;

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Heiner Kallweit committed
4765
	rtl8169_up(tp);
4766
	rtl8169_init_counter_offsets(tp);
4767 4768
	netif_start_queue(dev);

4769
	pm_runtime_put_sync(&pdev->dev);
4770 4771 4772
out:
	return retval;

4773
err_free_irq:
4774
	free_irq(pci_irq_vector(pdev, 0), tp);
4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790
err_release_fw_2:
	rtl_release_firmware(tp);
	rtl8169_rx_clear(tp);
err_free_rx_1:
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	tp->RxDescArray = NULL;
err_free_tx_0:
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
	tp->TxDescArray = NULL;
err_pm_runtime_put:
	pm_runtime_put_noidle(&pdev->dev);
	goto out;
}

4791
static void
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4792
rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
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4793 4794
{
	struct rtl8169_private *tp = netdev_priv(dev);
4795
	struct pci_dev *pdev = tp->pci_dev;
4796
	struct rtl8169_counters *counters = tp->counters;
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Linus Torvalds committed
4797

4798 4799
	pm_runtime_get_noresume(&pdev->dev);

4800 4801
	netdev_stats_to_stats64(stats, &dev->stats);

4802 4803
	rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes);
	rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes);
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Junchang Wang committed
4804

4805
	/*
4806
	 * Fetch additional counter values missing in stats collected by driver
4807 4808
	 * from tally counters.
	 */
4809
	if (pm_runtime_active(&pdev->dev))
4810
		rtl8169_update_counters(tp);
4811 4812 4813 4814 4815

	/*
	 * Subtract values fetched during initalization.
	 * See rtl8169_init_counter_offsets for a description why we do that.
	 */
4816
	stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4817
		le64_to_cpu(tp->tc_offset.tx_errors);
4818
	stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4819
		le32_to_cpu(tp->tc_offset.tx_multi_collision);
4820
	stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4821
		le16_to_cpu(tp->tc_offset.tx_aborted);
4822 4823
	stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
		le16_to_cpu(tp->tc_offset.rx_missed);
4824

4825
	pm_runtime_put_noidle(&pdev->dev);
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Linus Torvalds committed
4826 4827
}

4828
static void rtl8169_net_suspend(struct rtl8169_private *tp)
4829
{
4830
	netif_device_detach(tp->dev);
4831 4832 4833

	if (netif_running(tp->dev))
		rtl8169_down(tp);
4834 4835 4836 4837
}

#ifdef CONFIG_PM

4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849
static int rtl8169_net_resume(struct rtl8169_private *tp)
{
	rtl_rar_set(tp, tp->dev->dev_addr);

	if (tp->TxDescArray)
		rtl8169_up(tp);

	netif_device_attach(tp->dev);

	return 0;
}

4850
static int __maybe_unused rtl8169_suspend(struct device *device)
4851
{
4852
	struct rtl8169_private *tp = dev_get_drvdata(device);
4853

4854
	rtnl_lock();
4855
	rtl8169_net_suspend(tp);
4856 4857
	if (!device_may_wakeup(tp_to_dev(tp)))
		clk_disable_unprepare(tp->clk);
4858
	rtnl_unlock();
4859

4860 4861 4862
	return 0;
}

4863
static int __maybe_unused rtl8169_resume(struct device *device)
4864
{
4865
	struct rtl8169_private *tp = dev_get_drvdata(device);
4866

4867 4868
	if (!device_may_wakeup(tp_to_dev(tp)))
		clk_prepare_enable(tp->clk);
4869

4870 4871 4872
	/* Reportedly at least Asus X453MA truncates packets otherwise */
	if (tp->mac_version == RTL_GIGA_MAC_VER_37)
		rtl_init_rxcfg(tp);
4873

4874
	return rtl8169_net_resume(tp);
4875 4876 4877 4878
}

static int rtl8169_runtime_suspend(struct device *device)
{
4879
	struct rtl8169_private *tp = dev_get_drvdata(device);
4880

4881 4882
	if (!tp->TxDescArray) {
		netif_device_detach(tp->dev);
4883
		return 0;
4884
	}
4885

4886
	rtnl_lock();
4887
	__rtl8169_set_wol(tp, WAKE_PHY);
4888
	rtl8169_net_suspend(tp);
4889
	rtnl_unlock();
4890 4891 4892 4893 4894 4895

	return 0;
}

static int rtl8169_runtime_resume(struct device *device)
{
4896
	struct rtl8169_private *tp = dev_get_drvdata(device);
4897

4898 4899
	__rtl8169_set_wol(tp, tp->saved_wolopts);

4900
	return rtl8169_net_resume(tp);
4901 4902
}

4903 4904
static int rtl8169_runtime_idle(struct device *device)
{
4905
	struct rtl8169_private *tp = dev_get_drvdata(device);
4906

4907
	if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4908 4909 4910
		pm_schedule_suspend(device, 10000);

	return -EBUSY;
4911 4912
}

4913
static const struct dev_pm_ops rtl8169_pm_ops = {
4914 4915 4916
	SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
	SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
			   rtl8169_runtime_idle)
4917 4918
};

4919
#endif /* CONFIG_PM */
4920

4921 4922 4923 4924 4925 4926 4927 4928 4929
static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
{
	/* WoL fails with 8168b when the receiver is disabled. */
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		pci_clear_master(tp->pci_dev);

4930
		RTL_W8(tp, ChipCmd, CmdRxEnb);
4931
		rtl_pci_commit(tp);
4932 4933 4934 4935 4936 4937
		break;
	default:
		break;
	}
}

4938 4939
static void rtl_shutdown(struct pci_dev *pdev)
{
4940
	struct rtl8169_private *tp = pci_get_drvdata(pdev);
4941

4942
	rtnl_lock();
4943
	rtl8169_net_suspend(tp);
4944
	rtnl_unlock();
4945

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Francois Romieu committed
4946
	/* Restore original MAC address */
4947
	rtl_rar_set(tp, tp->dev->perm_addr);
4948

4949
	if (system_state == SYSTEM_POWER_OFF) {
4950
		if (tp->saved_wolopts) {
4951 4952
			rtl_wol_suspend_quirk(tp);
			rtl_wol_shutdown_quirk(tp);
4953 4954
		}

4955 4956 4957 4958
		pci_wake_from_d3(pdev, true);
		pci_set_power_state(pdev, PCI_D3hot);
	}
}
4959

4960
static void rtl_remove_one(struct pci_dev *pdev)
4961
{
4962
	struct rtl8169_private *tp = pci_get_drvdata(pdev);
4963

4964 4965
	if (pci_dev_run_wake(pdev))
		pm_runtime_get_noresume(&pdev->dev);
4966

4967
	unregister_netdev(tp->dev);
4968

4969 4970
	if (r8168_check_dash(tp))
		rtl8168_driver_stop(tp);
4971

4972
	rtl_release_firmware(tp);
4973 4974

	/* restore original MAC address */
4975
	rtl_rar_set(tp, tp->dev->perm_addr);
4976 4977
}

4978
static const struct net_device_ops rtl_netdev_ops = {
4979
	.ndo_open		= rtl_open,
4980 4981 4982
	.ndo_stop		= rtl8169_close,
	.ndo_get_stats64	= rtl8169_get_stats64,
	.ndo_start_xmit		= rtl8169_start_xmit,
4983
	.ndo_features_check	= rtl8169_features_check,
4984 4985 4986 4987 4988 4989
	.ndo_tx_timeout		= rtl8169_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= rtl8169_change_mtu,
	.ndo_fix_features	= rtl8169_fix_features,
	.ndo_set_features	= rtl8169_set_features,
	.ndo_set_mac_address	= rtl_set_mac_address,
4990
	.ndo_do_ioctl		= phy_do_ioctl_running,
4991 4992 4993 4994 4995 4996 4997
	.ndo_set_rx_mode	= rtl_set_rx_mode,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= rtl8169_netpoll,
#endif

};

4998 4999
static void rtl_set_irq_mask(struct rtl8169_private *tp)
{
5000
	tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5001 5002 5003 5004 5005 5006 5007 5008 5009 5010

	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
	else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
		/* special workaround needed */
		tp->irq_mask |= RxFIFOOver;
	else
		tp->irq_mask |= RxOverflow;
}

5011
static int rtl_alloc_irq(struct rtl8169_private *tp)
5012
{
5013
	unsigned int flags;
5014

5015 5016
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5017
		rtl_unlock_config_regs(tp);
5018
		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5019
		rtl_lock_config_regs(tp);
5020
		fallthrough;
5021
	case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5022
		flags = PCI_IRQ_LEGACY;
5023 5024
		break;
	default:
5025
		flags = PCI_IRQ_ALL_TYPES;
5026
		break;
5027
	}
5028 5029

	return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5030 5031
}

5032 5033 5034 5035
static void rtl_read_mac_address(struct rtl8169_private *tp,
				 u8 mac_addr[ETH_ALEN])
{
	/* Get MAC address */
5036 5037 5038
	if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
		u32 value = rtl_eri_read(tp, 0xe0);

5039 5040 5041 5042 5043
		mac_addr[0] = (value >>  0) & 0xff;
		mac_addr[1] = (value >>  8) & 0xff;
		mac_addr[2] = (value >> 16) & 0xff;
		mac_addr[3] = (value >> 24) & 0xff;

5044
		value = rtl_eri_read(tp, 0xe4);
5045 5046
		mac_addr[4] = (value >>  0) & 0xff;
		mac_addr[5] = (value >>  8) & 0xff;
5047 5048
	} else if (rtl_is_8125(tp)) {
		rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5049 5050 5051
	}
}

Hayes Wang's avatar
Hayes Wang committed
5052 5053
DECLARE_RTL_COND(rtl_link_list_ready_cond)
{
5054
	return RTL_R8(tp, MCU) & LINK_LIST_RDY;
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Hayes Wang committed
5055 5056
}

5057 5058 5059 5060 5061
static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
{
	rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
}

5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098
static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
{
	struct rtl8169_private *tp = mii_bus->priv;

	if (phyaddr > 0)
		return -ENODEV;

	return rtl_readphy(tp, phyreg);
}

static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
				int phyreg, u16 val)
{
	struct rtl8169_private *tp = mii_bus->priv;

	if (phyaddr > 0)
		return -ENODEV;

	rtl_writephy(tp, phyreg, val);

	return 0;
}

static int r8169_mdio_register(struct rtl8169_private *tp)
{
	struct pci_dev *pdev = tp->pci_dev;
	struct mii_bus *new_bus;
	int ret;

	new_bus = devm_mdiobus_alloc(&pdev->dev);
	if (!new_bus)
		return -ENOMEM;

	new_bus->name = "r8169";
	new_bus->priv = tp;
	new_bus->parent = &pdev->dev;
	new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5099
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5100 5101 5102 5103

	new_bus->read = r8169_mdio_read_reg;
	new_bus->write = r8169_mdio_write_reg;

5104
	ret = devm_mdiobus_register(&pdev->dev, new_bus);
5105 5106 5107
	if (ret)
		return ret;

5108 5109
	tp->phydev = mdiobus_get_phy(new_bus, 0);
	if (!tp->phydev) {
5110
		return -ENODEV;
5111 5112 5113 5114
	} else if (!tp->phydev->drv) {
		/* Most chip versions fail with the genphy driver.
		 * Therefore ensure that the dedicated PHY driver is loaded.
		 */
5115 5116
		dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
			tp->phydev->phy_id);
5117
		return -EUNATCH;
5118 5119
	}

5120
	/* PHY will be woken up in rtl_open() */
5121
	phy_suspend(tp->phydev);
5122 5123 5124 5125

	return 0;
}

5126
static void rtl_hw_init_8168g(struct rtl8169_private *tp)
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5127
{
5128
	rtl_enable_rxdvgate(tp);
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5129

5130
	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
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5131
	msleep(1);
5132
	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
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5133

5134
	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5135
	r8168g_wait_ll_share_fifo_ready(tp);
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5136

5137
	r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5138
	r8168g_wait_ll_share_fifo_ready(tp);
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5139 5140
}

5141 5142
static void rtl_hw_init_8125(struct rtl8169_private *tp)
{
5143
	rtl_enable_rxdvgate(tp);
5144 5145 5146 5147 5148 5149

	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
	msleep(1);
	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);

	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5150
	r8168g_wait_ll_share_fifo_ready(tp);
5151 5152 5153 5154

	r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
	r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
	r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5155
	r8168g_wait_ll_share_fifo_ready(tp);
5156 5157
}

5158
static void rtl_hw_initialize(struct rtl8169_private *tp)
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5159 5160
{
	switch (tp->mac_version) {
5161
	case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5162
		rtl8168ep_stop_cmac(tp);
5163
		fallthrough;
5164
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5165 5166
		rtl_hw_init_8168g(tp);
		break;
5167
	case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5168 5169
		rtl_hw_init_8125(tp);
		break;
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5170 5171 5172 5173 5174
	default:
		break;
	}
}

5175 5176 5177 5178
static int rtl_jumbo_max(struct rtl8169_private *tp)
{
	/* Non-GBit versions don't support jumbo frames */
	if (!tp->supports_gmii)
5179
		return 0;
5180 5181 5182

	switch (tp->mac_version) {
	/* RTL8169 */
5183
	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197
		return JUMBO_7K;
	/* RTL8168b */
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		return JUMBO_4K;
	/* RTL8168c */
	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
		return JUMBO_6K;
	default:
		return JUMBO_9K;
	}
}

5198 5199 5200 5201 5202
static void rtl_disable_clk(void *data)
{
	clk_disable_unprepare(data);
}

5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228
static int rtl_get_ether_clk(struct rtl8169_private *tp)
{
	struct device *d = tp_to_dev(tp);
	struct clk *clk;
	int rc;

	clk = devm_clk_get(d, "ether_clk");
	if (IS_ERR(clk)) {
		rc = PTR_ERR(clk);
		if (rc == -ENOENT)
			/* clk-core allows NULL (for suspend / resume) */
			rc = 0;
		else if (rc != -EPROBE_DEFER)
			dev_err(d, "failed to get clk: %d\n", rc);
	} else {
		tp->clk = clk;
		rc = clk_prepare_enable(clk);
		if (rc)
			dev_err(d, "failed to enable clk: %d\n", rc);
		else
			rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
	}

	return rc;
}

5229 5230 5231 5232
static void rtl_init_mac_address(struct rtl8169_private *tp)
{
	struct net_device *dev = tp->dev;
	u8 *mac_addr = dev->dev_addr;
5233
	int rc;
5234 5235 5236 5237 5238 5239 5240 5241 5242

	rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
	if (!rc)
		goto done;

	rtl_read_mac_address(tp, mac_addr);
	if (is_valid_ether_addr(mac_addr))
		goto done;

5243
	rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5244 5245 5246 5247 5248 5249 5250 5251 5252
	if (is_valid_ether_addr(mac_addr))
		goto done;

	eth_hw_addr_random(dev);
	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
done:
	rtl_rar_set(tp, mac_addr);
}

5253
static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5254 5255
{
	struct rtl8169_private *tp;
5256 5257
	int jumbo_max, region, rc;
	enum mac_version chipset;
5258
	struct net_device *dev;
5259
	u16 xid;
5260

5261 5262 5263
	dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
	if (!dev)
		return -ENOMEM;
5264 5265

	SET_NETDEV_DEV(dev, &pdev->dev);
5266
	dev->netdev_ops = &rtl_netdev_ops;
5267 5268 5269
	tp = netdev_priv(dev);
	tp->dev = dev;
	tp->pci_dev = pdev;
5270
	tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5271
	tp->eee_adv = -1;
5272
	tp->ocp_base = OCP_STD_PHY_BASE;
5273

5274
	/* Get the *optional* external "ether_clk" used on some boards */
5275 5276 5277
	rc = rtl_get_ether_clk(tp);
	if (rc)
		return rc;
5278

5279 5280 5281
	/* Disable ASPM completely as that cause random device stop working
	 * problems as well as full system hangs for some PCIe devices users.
	 */
5282 5283 5284
	rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
					  PCIE_LINK_STATE_L1);
	tp->aspm_manageable = !rc;
5285

5286
	/* enable device (incl. PCI PM wakeup and hotplug setup) */
5287
	rc = pcim_enable_device(pdev);
5288
	if (rc < 0) {
5289
		dev_err(&pdev->dev, "enable failure\n");
5290
		return rc;
5291 5292
	}

5293
	if (pcim_set_mwi(pdev) < 0)
5294
		dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5295

5296 5297 5298
	/* use first MMIO region */
	region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
	if (region < 0) {
5299
		dev_err(&pdev->dev, "no MMIO resource found\n");
5300
		return -ENODEV;
5301 5302 5303 5304
	}

	/* check for weird/broken PCI region reporting */
	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5305
		dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5306
		return -ENODEV;
5307 5308
	}

5309
	rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5310
	if (rc < 0) {
5311
		dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5312
		return rc;
5313 5314
	}

5315
	tp->mmio_addr = pcim_iomap_table(pdev)[region];
5316

5317 5318
	xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;

5319
	/* Identify chip attached to board */
5320 5321 5322
	chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
	if (chipset == RTL_GIGA_MAC_NONE) {
		dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5323
		return -ENODEV;
5324 5325 5326
	}

	tp->mac_version = chipset;
5327

5328
	tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5329

5330
	if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5331
	    !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5332 5333
		dev->features |= NETIF_F_HIGHDMA;

5334 5335
	rtl_init_rxcfg(tp);

5336
	rtl8169_irq_mask_and_ack(tp);
5337

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5338 5339
	rtl_hw_initialize(tp);

5340 5341 5342 5343
	rtl_hw_reset(tp);

	pci_set_master(pdev);

5344 5345
	rc = rtl_alloc_irq(tp);
	if (rc < 0) {
5346
		dev_err(&pdev->dev, "Can't allocate interrupt\n");
5347 5348
		return rc;
	}
5349

5350
	INIT_WORK(&tp->wk.work, rtl_task);
5351 5352
	u64_stats_init(&tp->rx_stats.syncp);
	u64_stats_init(&tp->tx_stats.syncp);
5353

5354
	rtl_init_mac_address(tp);
5355

5356
	dev->ethtool_ops = &rtl8169_ethtool_ops;
5357

5358
	netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5359

5360 5361
	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
			   NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5362
	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5363
	dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5364

5365 5366 5367 5368
	/*
	 * Pretend we are using VLANs; This bypasses a nasty bug where
	 * Interrupts stop flowing on high load on 8110SCd controllers.
	 */
5369
	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5370
		/* Disallow toggling */
5371
		dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5372

5373 5374 5375 5376 5377 5378 5379 5380 5381 5382
	if (rtl_chip_supports_csum_v2(tp))
		dev->hw_features |= NETIF_F_IPV6_CSUM;

	dev->features |= dev->hw_features;

	/* There has been a number of reports that using SG/TSO results in
	 * tx timeouts. However for a lot of people SG/TSO works fine.
	 * Therefore disable both features by default, but allow users to
	 * enable them. Use at own risk!
	 */
5383
	if (rtl_chip_supports_csum_v2(tp)) {
5384
		dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5385 5386 5387
		dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
		dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
	} else {
5388
		dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5389 5390 5391
		dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
		dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
	}
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5392

5393 5394 5395
	dev->hw_features |= NETIF_F_RXALL;
	dev->hw_features |= NETIF_F_RXFCS;

5396 5397 5398
	/* configure chip for default features */
	rtl8169_set_features(dev, dev->features);

5399
	jumbo_max = rtl_jumbo_max(tp);
5400 5401
	if (jumbo_max)
		dev->max_mtu = jumbo_max;
5402

5403
	rtl_set_irq_mask(tp);
5404

5405
	tp->fw_name = rtl_chip_infos[chipset].fw_name;
5406

5407 5408 5409
	tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
					    &tp->counters_phys_addr,
					    GFP_KERNEL);
5410 5411
	if (!tp->counters)
		return -ENOMEM;
5412

5413
	pci_set_drvdata(pdev, tp);
5414

5415 5416
	rc = r8169_mdio_register(tp);
	if (rc)
5417
		return rc;
5418

5419 5420 5421
	/* chip gets powered up in rtl_open() */
	rtl_pll_power_down(tp);

5422 5423
	rc = register_netdev(dev);
	if (rc)
5424
		return rc;
5425

5426 5427 5428
	netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
		    rtl_chip_infos[chipset].name, dev->dev_addr, xid,
		    pci_irq_vector(pdev, 0));
5429

5430
	if (jumbo_max)
5431 5432 5433
		netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
			    jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
			    "ok" : "ko");
5434

5435 5436
	if (r8168_check_dash(tp)) {
		netdev_info(dev, "DASH enabled\n");
5437
		rtl8168_driver_start(tp);
5438
	}
5439

5440 5441 5442
	if (pci_dev_run_wake(pdev))
		pm_runtime_put_sync(&pdev->dev);

5443
	return 0;
5444 5445
}

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5446 5447 5448
static struct pci_driver rtl8169_pci_driver = {
	.name		= MODULENAME,
	.id_table	= rtl8169_pci_tbl,
5449
	.probe		= rtl_init_one,
5450
	.remove		= rtl_remove_one,
5451
	.shutdown	= rtl_shutdown,
5452 5453 5454
#ifdef CONFIG_PM
	.driver.pm	= &rtl8169_pm_ops,
#endif
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Linus Torvalds committed
5455 5456
};

5457
module_pci_driver(rtl8169_pci_driver);