irq-gic-v3-its.c 140 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0-only
2
/*
3
 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 5 6
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 */

7
#include <linux/acpi.h>
8
#include <linux/acpi_iort.h>
9
#include <linux/bitfield.h>
10 11
#include <linux/bitmap.h>
#include <linux/cpu.h>
12
#include <linux/crash_dump.h>
13
#include <linux/delay.h>
14
#include <linux/efi.h>
15
#include <linux/interrupt.h>
16
#include <linux/iommu.h>
17
#include <linux/iopoll.h>
18
#include <linux/irqdomain.h>
19
#include <linux/list.h>
20
#include <linux/log2.h>
21
#include <linux/memblock.h>
22 23 24 25 26 27 28 29 30
#include <linux/mm.h>
#include <linux/msi.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/percpu.h>
#include <linux/slab.h>
31
#include <linux/syscore_ops.h>
32

33
#include <linux/irqchip.h>
34
#include <linux/irqchip/arm-gic-v3.h>
35
#include <linux/irqchip/arm-gic-v4.h>
36 37 38 39

#include <asm/cputype.h>
#include <asm/exception.h>

40 41
#include "irq-gic-common.h"

42 43
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
44
#define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
45
#define ITS_FLAGS_FORCE_NON_SHAREABLE		(1ULL << 3)
46

47
#define RD_LOCAL_LPI_ENABLED                    BIT(0)
48 49
#define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
#define RD_LOCAL_MEMRESERVE_DONE                BIT(2)
50

51 52 53 54 55 56 57 58 59 60 61
static u32 lpi_id_bits;

/*
 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
 * deal with (one configuration byte per interrupt). PENDBASE has to
 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 */
#define LPI_NRBITS		lpi_id_bits
#define LPI_PROPBASE_SZ		ALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZ		ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)

62
static u8 __ro_after_init lpi_prop_prio;
63

64 65 66 67 68 69 70 71 72 73
/*
 * Collection structure - just an ID, and a redistributor address to
 * ping. We use one per CPU as a bag of interrupts assigned to this
 * CPU.
 */
struct its_collection {
	u64			target_address;
	u16			col_id;
};

74
/*
75 76
 * The ITS_BASER structure - contains memory information, cached
 * value of BASER register configuration and ITS page size.
77 78 79 80 81
 */
struct its_baser {
	void		*base;
	u64		val;
	u32		order;
82
	u32		psz;
83 84
};

85 86
struct its_device;

87 88
/*
 * The ITS structure - contains most of the infrastructure, with the
89 90
 * top-level MSI domain, the command queue, the collections, and the
 * list of devices writing to it.
91 92 93 94
 *
 * dev_alloc_lock has to be taken for device allocations, while the
 * spinlock must be taken to parse data structures such as the device
 * list.
95 96 97
 */
struct its_node {
	raw_spinlock_t		lock;
98
	struct mutex		dev_alloc_lock;
99 100
	struct list_head	entry;
	void __iomem		*base;
101
	void __iomem		*sgir_base;
102
	phys_addr_t		phys_base;
103 104
	struct its_cmd_block	*cmd_base;
	struct its_cmd_block	*cmd_write;
105
	struct its_baser	tables[GITS_BASER_NR_REGS];
106
	struct its_collection	*collections;
107 108
	struct fwnode_handle	*fwnode_handle;
	u64			(*get_msi_base)(struct its_device *its_dev);
109
	u64			typer;
110 111
	u64			cbaser_save;
	u32			ctlr_save;
112
	u32			mpidr;
113 114
	struct list_head	its_device_list;
	u64			flags;
115
	unsigned long		list_nr;
116
	int			numa_node;
117 118
	unsigned int		msi_domain_flags;
	u32			pre_its_base; /* for Socionext Synquacer */
119
	int			vlpi_redist_offset;
120 121
};

122
#define is_v4(its)		(!!((its)->typer & GITS_TYPER_VLPIS))
123
#define is_v4_1(its)		(!!((its)->typer & GITS_TYPER_VMAPP))
124
#define device_ids(its)		(FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
125

126 127
#define ITS_ITT_ALIGN		SZ_256

128
/* The maximum number of VPEID bits supported by VLPI commands */
129 130 131 132 133 134 135 136 137 138
#define ITS_MAX_VPEID_BITS						\
	({								\
		int nvpeid = 16;					\
		if (gic_rdists->has_rvpeid &&				\
		    gic_rdists->gicd_typer2 & GICD_TYPER2_VIL)		\
			nvpeid = 1 + (gic_rdists->gicd_typer2 &		\
				      GICD_TYPER2_VID);			\
									\
		nvpeid;							\
	})
139 140
#define ITS_MAX_VPEID		(1 << (ITS_MAX_VPEID_BITS))

141 142 143
/* Convert page order to size in bytes */
#define PAGE_ORDER_TO_SIZE(o)	(PAGE_SIZE << (o))

144 145 146 147 148
struct event_lpi_map {
	unsigned long		*lpi_map;
	u16			*col_map;
	irq_hw_number_t		lpi_base;
	int			nr_lpis;
149
	raw_spinlock_t		vlpi_lock;
150 151 152
	struct its_vm		*vm;
	struct its_vlpi_map	*vlpi_maps;
	int			nr_vlpis;
153 154
};

155
/*
156 157 158 159
 * The ITS view of a device - belongs to an ITS, owns an interrupt
 * translation table, and a list of interrupts.  If it some of its
 * LPIs are injected into a guest (GICv4), the event_map.vm field
 * indicates which one.
160 161 162 163
 */
struct its_device {
	struct list_head	entry;
	struct its_node		*its;
164
	struct event_lpi_map	event_map;
165 166 167
	void			*itt;
	u32			nr_ites;
	u32			device_id;
168
	bool			shared;
169 170
};

171 172 173 174 175 176 177
static struct {
	raw_spinlock_t		lock;
	struct its_device	*dev;
	struct its_vpe		**vpes;
	int			next_victim;
} vpe_proxy;

178 179 180 181 182 183 184
struct cpu_lpi_count {
	atomic_t	managed;
	atomic_t	unmanaged;
};

static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);

185
static LIST_HEAD(its_nodes);
186
static DEFINE_RAW_SPINLOCK(its_lock);
187
static struct rdists *gic_rdists;
188
static struct irq_domain *its_parent;
189

190
static unsigned long its_list_map;
191 192 193
static u16 vmovp_seq_num;
static DEFINE_RAW_SPINLOCK(vmovp_lock);

194
static DEFINE_IDA(its_vpeid_ida);
195

196
#define gic_data_rdist()		(raw_cpu_ptr(gic_rdists->rdist))
197
#define gic_data_rdist_cpu(cpu)		(per_cpu_ptr(gic_rdists->rdist, cpu))
198
#define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
199
#define gic_data_rdist_vlpi_base()	(gic_data_rdist_rd_base() + SZ_128K)
200

201 202 203 204 205 206 207 208 209
/*
 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
 * always have vSGIs mapped.
 */
static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
{
	return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
}

210 211 212 213 214
static bool rdists_support_shareable(void)
{
	return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE);
}

215 216 217 218 219 220
static u16 get_its_list(struct its_vm *vm)
{
	struct its_node *its;
	unsigned long its_list = 0;

	list_for_each_entry(its, &its_nodes, entry) {
221
		if (!is_v4(its))
222 223
			continue;

224
		if (require_its_list_vmovp(vm, its))
225 226 227 228 229 230
			__set_bit(its->list_nr, &its_list);
	}

	return (u16)its_list;
}

231 232 233 234 235 236
static inline u32 its_get_event_id(struct irq_data *d)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	return d->hwirq - its_dev->event_map.lpi_base;
}

237 238 239 240 241 242 243 244
static struct its_collection *dev_event_to_col(struct its_device *its_dev,
					       u32 event)
{
	struct its_node *its = its_dev->its;

	return its->collections + its_dev->event_map.col_map[event];
}

245 246 247 248 249 250 251 252 253
static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
					       u32 event)
{
	if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
		return NULL;

	return &its_dev->event_map.vlpi_maps[event];
}

254 255 256 257 258 259 260 261 262 263 264 265
static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
{
	if (irqd_is_forwarded_to_vcpu(d)) {
		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
		u32 event = its_get_event_id(d);

		return dev_event_to_vlpi_map(its_dev, event);
	}

	return NULL;
}

266 267 268 269 270 271 272 273 274 275 276
static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
{
	raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
	return vpe->col_idx;
}

static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
{
	raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
}

277 278
static struct irq_chip its_vpe_irq_chip;

279
static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
280
{
281
	struct its_vpe *vpe = NULL;
282
	int cpu;
283

284 285 286 287 288 289 290 291 292 293
	if (d->chip == &its_vpe_irq_chip) {
		vpe = irq_data_get_irq_chip_data(d);
	} else {
		struct its_vlpi_map *map = get_vlpi_map(d);
		if (map)
			vpe = map->vpe;
	}

	if (vpe) {
		cpu = vpe_to_cpuid_lock(vpe, flags);
294 295 296 297 298 299 300
	} else {
		/* Physical LPIs are already locked via the irq_desc lock */
		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
		cpu = its_dev->event_map.col_map[its_get_event_id(d)];
		/* Keep GCC quiet... */
		*flags = 0;
	}
301

302 303 304 305
	return cpu;
}

static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
306
{
307 308 309 310 311 312 313 314 315
	struct its_vpe *vpe = NULL;

	if (d->chip == &its_vpe_irq_chip) {
		vpe = irq_data_get_irq_chip_data(d);
	} else {
		struct its_vlpi_map *map = get_vlpi_map(d);
		if (map)
			vpe = map->vpe;
	}
316

317 318
	if (vpe)
		vpe_to_cpuid_unlock(vpe, flags);
319 320
}

321 322
static struct its_collection *valid_col(struct its_collection *col)
{
323
	if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
324 325 326 327 328
		return NULL;

	return col;
}

329 330 331 332 333 334 335 336
static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
{
	if (valid_col(its->collections + vpe->col_idx))
		return vpe;

	return NULL;
}

337 338 339 340 341 342 343 344 345 346 347
/*
 * ITS command descriptors - parameters to be encoded in a command
 * block.
 */
struct its_cmd_desc {
	union {
		struct {
			struct its_device *dev;
			u32 event_id;
		} its_inv_cmd;

348 349 350 351 352
		struct {
			struct its_device *dev;
			u32 event_id;
		} its_clear_cmd;

353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371
		struct {
			struct its_device *dev;
			u32 event_id;
		} its_int_cmd;

		struct {
			struct its_device *dev;
			int valid;
		} its_mapd_cmd;

		struct {
			struct its_collection *col;
			int valid;
		} its_mapc_cmd;

		struct {
			struct its_device *dev;
			u32 phys_id;
			u32 event_id;
372
		} its_mapti_cmd;
373 374 375 376

		struct {
			struct its_device *dev;
			struct its_collection *col;
377
			u32 event_id;
378 379 380 381 382 383 384 385 386 387
		} its_movi_cmd;

		struct {
			struct its_device *dev;
			u32 event_id;
		} its_discard_cmd;

		struct {
			struct its_collection *col;
		} its_invall_cmd;
388

389 390 391 392 393 394 395 396 397 398
		struct {
			struct its_vpe *vpe;
		} its_vinvall_cmd;

		struct {
			struct its_vpe *vpe;
			struct its_collection *col;
			bool valid;
		} its_vmapp_cmd;

399 400 401 402 403 404 405 406 407 408 409 410 411 412
		struct {
			struct its_vpe *vpe;
			struct its_device *dev;
			u32 virt_id;
			u32 event_id;
			bool db_enabled;
		} its_vmapti_cmd;

		struct {
			struct its_vpe *vpe;
			struct its_device *dev;
			u32 event_id;
			bool db_enabled;
		} its_vmovi_cmd;
413 414 415 416 417 418 419

		struct {
			struct its_vpe *vpe;
			struct its_collection *col;
			u16 seq_num;
			u16 its_list;
		} its_vmovp_cmd;
420 421 422 423

		struct {
			struct its_vpe *vpe;
		} its_invdb_cmd;
424 425 426 427 428 429 430 431 432

		struct {
			struct its_vpe *vpe;
			u8 sgi;
			u8 priority;
			bool enable;
			bool group;
			bool clear;
		} its_vsgi_cmd;
433 434 435 436 437 438 439
	};
};

/*
 * The ITS command block, which is what the ITS actually parses.
 */
struct its_cmd_block {
440 441 442 443
	union {
		u64	raw_cmd[4];
		__le64	raw_cmd_le[4];
	};
444 445 446 447 448
};

#define ITS_CMD_QUEUE_SZ		SZ_64K
#define ITS_CMD_QUEUE_NR_ENTRIES	(ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))

449 450
typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
						    struct its_cmd_block *,
451 452
						    struct its_cmd_desc *);

453 454
typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
					      struct its_cmd_block *,
455 456
					      struct its_cmd_desc *);

457 458 459 460 461 462 463
static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
{
	u64 mask = GENMASK_ULL(h, l);
	*raw_cmd &= ~mask;
	*raw_cmd |= (val << l) & mask;
}

464 465
static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
{
466
	its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
467 468 469 470
}

static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
{
471
	its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
472 473 474 475
}

static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
{
476
	its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
477 478 479 480
}

static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
{
481
	its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
482 483 484 485
}

static void its_encode_size(struct its_cmd_block *cmd, u8 size)
{
486
	its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
487 488 489 490
}

static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
{
491
	its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
492 493 494 495
}

static void its_encode_valid(struct its_cmd_block *cmd, int valid)
{
496
	its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
497 498 499 500
}

static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
{
501
	its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
502 503 504 505
}

static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
{
506
	its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
507 508
}

509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528
static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
{
	its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
}

static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
{
	its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
}

static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
{
	its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
}

static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
{
	its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
}

529 530 531 532 533 534 535 536 537 538
static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
{
	its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
}

static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
{
	its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
}

539 540
static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
{
541
	its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
542 543 544 545 546 547 548
}

static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
{
	its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
}

549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569
static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
{
	its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
}

static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
{
	its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
}

static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
{
	its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
}

static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
					u32 vpe_db_lpi)
{
	its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
}

570 571 572 573 574 575 576 577 578 579 580
static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
					u32 vpe_db_lpi)
{
	its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
}

static void its_encode_db(struct its_cmd_block *cmd, bool db)
{
	its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
}

581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605
static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
{
	its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
}

static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
{
	its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
}

static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
{
	its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
}

static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
{
	its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
}

static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
{
	its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
}

606 607 608
static inline void its_fixup_cmd(struct its_cmd_block *cmd)
{
	/* Let's fixup BE commands */
609 610 611 612
	cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
	cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
	cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
	cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
613 614
}

615 616
static struct its_collection *its_build_mapd_cmd(struct its_node *its,
						 struct its_cmd_block *cmd,
617 618 619
						 struct its_cmd_desc *desc)
{
	unsigned long itt_addr;
620
	u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
621 622 623 624 625 626 627 628 629 630 631 632

	itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
	itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);

	its_encode_cmd(cmd, GITS_CMD_MAPD);
	its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
	its_encode_size(cmd, size - 1);
	its_encode_itt(cmd, itt_addr);
	its_encode_valid(cmd, desc->its_mapd_cmd.valid);

	its_fixup_cmd(cmd);

633
	return NULL;
634 635
}

636 637
static struct its_collection *its_build_mapc_cmd(struct its_node *its,
						 struct its_cmd_block *cmd,
638 639 640 641 642 643 644 645 646 647 648 649
						 struct its_cmd_desc *desc)
{
	its_encode_cmd(cmd, GITS_CMD_MAPC);
	its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
	its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
	its_encode_valid(cmd, desc->its_mapc_cmd.valid);

	its_fixup_cmd(cmd);

	return desc->its_mapc_cmd.col;
}

650 651
static struct its_collection *its_build_mapti_cmd(struct its_node *its,
						  struct its_cmd_block *cmd,
652 653
						  struct its_cmd_desc *desc)
{
654 655
	struct its_collection *col;

656 657
	col = dev_event_to_col(desc->its_mapti_cmd.dev,
			       desc->its_mapti_cmd.event_id);
658

659 660 661 662
	its_encode_cmd(cmd, GITS_CMD_MAPTI);
	its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
	its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
663
	its_encode_collection(cmd, col->col_id);
664 665 666

	its_fixup_cmd(cmd);

667
	return valid_col(col);
668 669
}

670 671
static struct its_collection *its_build_movi_cmd(struct its_node *its,
						 struct its_cmd_block *cmd,
672 673
						 struct its_cmd_desc *desc)
{
674 675 676 677 678
	struct its_collection *col;

	col = dev_event_to_col(desc->its_movi_cmd.dev,
			       desc->its_movi_cmd.event_id);

679 680
	its_encode_cmd(cmd, GITS_CMD_MOVI);
	its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
681
	its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
682 683 684 685
	its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);

	its_fixup_cmd(cmd);

686
	return valid_col(col);
687 688
}

689 690
static struct its_collection *its_build_discard_cmd(struct its_node *its,
						    struct its_cmd_block *cmd,
691 692
						    struct its_cmd_desc *desc)
{
693 694 695 696 697
	struct its_collection *col;

	col = dev_event_to_col(desc->its_discard_cmd.dev,
			       desc->its_discard_cmd.event_id);

698 699 700 701 702 703
	its_encode_cmd(cmd, GITS_CMD_DISCARD);
	its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_discard_cmd.event_id);

	its_fixup_cmd(cmd);

704
	return valid_col(col);
705 706
}

707 708
static struct its_collection *its_build_inv_cmd(struct its_node *its,
						struct its_cmd_block *cmd,
709 710
						struct its_cmd_desc *desc)
{
711 712 713 714 715
	struct its_collection *col;

	col = dev_event_to_col(desc->its_inv_cmd.dev,
			       desc->its_inv_cmd.event_id);

716 717 718 719 720 721
	its_encode_cmd(cmd, GITS_CMD_INV);
	its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_inv_cmd.event_id);

	its_fixup_cmd(cmd);

722
	return valid_col(col);
723 724
}

725 726
static struct its_collection *its_build_int_cmd(struct its_node *its,
						struct its_cmd_block *cmd,
727 728 729 730 731 732 733 734 735 736 737 738 739
						struct its_cmd_desc *desc)
{
	struct its_collection *col;

	col = dev_event_to_col(desc->its_int_cmd.dev,
			       desc->its_int_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_INT);
	its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_int_cmd.event_id);

	its_fixup_cmd(cmd);

740
	return valid_col(col);
741 742
}

743 744
static struct its_collection *its_build_clear_cmd(struct its_node *its,
						  struct its_cmd_block *cmd,
745 746 747 748 749 750 751 752 753 754 755 756 757
						  struct its_cmd_desc *desc)
{
	struct its_collection *col;

	col = dev_event_to_col(desc->its_clear_cmd.dev,
			       desc->its_clear_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_CLEAR);
	its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_clear_cmd.event_id);

	its_fixup_cmd(cmd);

758
	return valid_col(col);
759 760
}

761 762
static struct its_collection *its_build_invall_cmd(struct its_node *its,
						   struct its_cmd_block *cmd,
763 764 765
						   struct its_cmd_desc *desc)
{
	its_encode_cmd(cmd, GITS_CMD_INVALL);
766
	its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
767 768 769

	its_fixup_cmd(cmd);

770
	return desc->its_invall_cmd.col;
771 772
}

773 774
static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
					     struct its_cmd_block *cmd,
775 776 777 778 779 780 781
					     struct its_cmd_desc *desc)
{
	its_encode_cmd(cmd, GITS_CMD_VINVALL);
	its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);

	its_fixup_cmd(cmd);

782
	return valid_vpe(its, desc->its_vinvall_cmd.vpe);
783 784
}

785 786
static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
787 788
					   struct its_cmd_desc *desc)
{
789
	struct its_vpe *vpe = valid_vpe(its, desc->its_vmapp_cmd.vpe);
790
	unsigned long vpt_addr, vconf_addr;
791
	u64 target;
792
	bool alloc;
793 794 795 796

	its_encode_cmd(cmd, GITS_CMD_VMAPP);
	its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
	its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
797 798 799 800 801

	if (!desc->its_vmapp_cmd.valid) {
		if (is_v4_1(its)) {
			alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
			its_encode_alloc(cmd, alloc);
802 803 804 805 806
			/*
			 * Unmapping a VPE is self-synchronizing on GICv4.1,
			 * no need to issue a VSYNC.
			 */
			vpe = NULL;
807 808 809 810 811 812 813 814
		}

		goto out;
	}

	vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
	target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;

815
	its_encode_target(cmd, target);
816 817 818
	its_encode_vpt_addr(cmd, vpt_addr);
	its_encode_vpt_size(cmd, LPI_NRBITS - 1);

819 820 821 822 823 824 825 826 827
	if (!is_v4_1(its))
		goto out;

	vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));

	alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);

	its_encode_alloc(cmd, alloc);

828 829 830 831 832 833 834
	/*
	 * GICv4.1 provides a way to get the VLPI state, which needs the vPE
	 * to be unmapped first, and in this case, we may remap the vPE
	 * back while the VPT is not empty. So we can't assume that the
	 * VPT is empty on map. This is why we never advertise PTZ.
	 */
	its_encode_ptz(cmd, false);
835 836 837 838
	its_encode_vconf_addr(cmd, vconf_addr);
	its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);

out:
839 840
	its_fixup_cmd(cmd);

841
	return vpe;
842 843
}

844 845
static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
					    struct its_cmd_block *cmd,
846 847 848 849
					    struct its_cmd_desc *desc)
{
	u32 db;

850
	if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
851 852 853 854 855 856 857 858 859 860 861 862 863
		db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
	else
		db = 1023;

	its_encode_cmd(cmd, GITS_CMD_VMAPTI);
	its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
	its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
	its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
	its_encode_db_phys_id(cmd, db);
	its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);

	its_fixup_cmd(cmd);

864
	return valid_vpe(its, desc->its_vmapti_cmd.vpe);
865 866
}

867 868
static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
869 870 871 872
					   struct its_cmd_desc *desc)
{
	u32 db;

873
	if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
874 875 876 877 878 879 880 881 882 883 884 885 886
		db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
	else
		db = 1023;

	its_encode_cmd(cmd, GITS_CMD_VMOVI);
	its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
	its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
	its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
	its_encode_db_phys_id(cmd, db);
	its_encode_db_valid(cmd, true);

	its_fixup_cmd(cmd);

887
	return valid_vpe(its, desc->its_vmovi_cmd.vpe);
888 889
}

890 891
static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
892 893
					   struct its_cmd_desc *desc)
{
894 895 896
	u64 target;

	target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
897 898 899 900
	its_encode_cmd(cmd, GITS_CMD_VMOVP);
	its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
	its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
	its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
901
	its_encode_target(cmd, target);
902

903 904 905 906 907
	if (is_v4_1(its)) {
		its_encode_db(cmd, true);
		its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
	}

908 909
	its_fixup_cmd(cmd);

910
	return valid_vpe(its, desc->its_vmovp_cmd.vpe);
911 912
}

913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930
static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
					  struct its_cmd_block *cmd,
					  struct its_cmd_desc *desc)
{
	struct its_vlpi_map *map;

	map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
				    desc->its_inv_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_INV);
	its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_inv_cmd.event_id);

	its_fixup_cmd(cmd);

	return valid_vpe(its, map->vpe);
}

931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966
static struct its_vpe *its_build_vint_cmd(struct its_node *its,
					  struct its_cmd_block *cmd,
					  struct its_cmd_desc *desc)
{
	struct its_vlpi_map *map;

	map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
				    desc->its_int_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_INT);
	its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_int_cmd.event_id);

	its_fixup_cmd(cmd);

	return valid_vpe(its, map->vpe);
}

static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
					    struct its_cmd_block *cmd,
					    struct its_cmd_desc *desc)
{
	struct its_vlpi_map *map;

	map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
				    desc->its_clear_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_CLEAR);
	its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_clear_cmd.event_id);

	its_fixup_cmd(cmd);

	return valid_vpe(its, map->vpe);
}

967 968 969 970 971 972 973 974 975 976 977 978 979 980 981
static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
					   struct its_cmd_desc *desc)
{
	if (WARN_ON(!is_v4_1(its)))
		return NULL;

	its_encode_cmd(cmd, GITS_CMD_INVDB);
	its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);

	its_fixup_cmd(cmd);

	return valid_vpe(its, desc->its_invdb_cmd.vpe);
}

982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001
static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
					  struct its_cmd_block *cmd,
					  struct its_cmd_desc *desc)
{
	if (WARN_ON(!is_v4_1(its)))
		return NULL;

	its_encode_cmd(cmd, GITS_CMD_VSGI);
	its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
	its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
	its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
	its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
	its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
	its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);

	its_fixup_cmd(cmd);

	return valid_vpe(its, desc->its_vsgi_cmd.vpe);
}

1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
static u64 its_cmd_ptr_to_offset(struct its_node *its,
				 struct its_cmd_block *ptr)
{
	return (ptr - its->cmd_base) * sizeof(*ptr);
}

static int its_queue_full(struct its_node *its)
{
	int widx;
	int ridx;

	widx = its->cmd_write - its->cmd_base;
	ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);

	/* This is incredibly unlikely to happen, unless the ITS locks up. */
	if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
		return 1;

	return 0;
}

static struct its_cmd_block *its_allocate_entry(struct its_node *its)
{
	struct its_cmd_block *cmd;
	u32 count = 1000000;	/* 1s! */

	while (its_queue_full(its)) {
		count--;
		if (!count) {
			pr_err_ratelimited("ITS queue not draining\n");
			return NULL;
		}
		cpu_relax();
		udelay(1);
	}

	cmd = its->cmd_write++;

	/* Handle queue wrapping */
	if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
		its->cmd_write = its->cmd_base;

1044 1045 1046 1047 1048 1049
	/* Clear command  */
	cmd->raw_cmd[0] = 0;
	cmd->raw_cmd[1] = 0;
	cmd->raw_cmd[2] = 0;
	cmd->raw_cmd[3] = 0;

1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
	return cmd;
}

static struct its_cmd_block *its_post_commands(struct its_node *its)
{
	u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);

	writel_relaxed(wr, its->base + GITS_CWRITER);

	return its->cmd_write;
}

static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
{
	/*
	 * Make sure the commands written to memory are observable by
	 * the ITS.
	 */
	if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1069
		gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1070 1071 1072 1073
	else
		dsb(ishst);
}

1074
static int its_wait_for_range_completion(struct its_node *its,
1075
					 u64	prev_idx,
1076
					 struct its_cmd_block *to)
1077
{
1078
	u64 rd_idx, to_idx, linear_idx;
1079 1080
	u32 count = 1000000;	/* 1s! */

1081
	/* Linearize to_idx if the command set has wrapped around */
1082
	to_idx = its_cmd_ptr_to_offset(its, to);
1083 1084 1085 1086
	if (to_idx < prev_idx)
		to_idx += ITS_CMD_QUEUE_SZ;

	linear_idx = prev_idx;
1087 1088

	while (1) {
1089 1090
		s64 delta;

1091
		rd_idx = readl_relaxed(its->base + GITS_CREADR);
1092

1093 1094 1095 1096 1097 1098 1099
		/*
		 * Compute the read pointer progress, taking the
		 * potential wrap-around into account.
		 */
		delta = rd_idx - prev_idx;
		if (rd_idx < prev_idx)
			delta += ITS_CMD_QUEUE_SZ;
1100

1101 1102
		linear_idx += delta;
		if (linear_idx >= to_idx)
1103 1104 1105 1106
			break;

		count--;
		if (!count) {
1107 1108
			pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
					   to_idx, linear_idx);
1109
			return -1;
1110
		}
1111
		prev_idx = rd_idx;
1112 1113 1114
		cpu_relax();
		udelay(1);
	}
1115 1116

	return 0;
1117 1118
}

1119 1120 1121 1122 1123 1124 1125 1126 1127
/* Warning, macro hell follows */
#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)	\
void name(struct its_node *its,						\
	  buildtype builder,						\
	  struct its_cmd_desc *desc)					\
{									\
	struct its_cmd_block *cmd, *sync_cmd, *next_cmd;		\
	synctype *sync_obj;						\
	unsigned long flags;						\
1128
	u64 rd_idx;							\
1129 1130 1131 1132 1133 1134 1135 1136
									\
	raw_spin_lock_irqsave(&its->lock, flags);			\
									\
	cmd = its_allocate_entry(its);					\
	if (!cmd) {		/* We're soooooo screewed... */		\
		raw_spin_unlock_irqrestore(&its->lock, flags);		\
		return;							\
	}								\
1137
	sync_obj = builder(its, cmd, desc);				\
1138 1139 1140 1141 1142 1143 1144
	its_flush_cmd(its, cmd);					\
									\
	if (sync_obj) {							\
		sync_cmd = its_allocate_entry(its);			\
		if (!sync_cmd)						\
			goto post;					\
									\
1145
		buildfn(its, sync_cmd, sync_obj);			\
1146 1147 1148 1149
		its_flush_cmd(its, sync_cmd);				\
	}								\
									\
post:									\
1150
	rd_idx = readl_relaxed(its->base + GITS_CREADR);		\
1151 1152 1153
	next_cmd = its_post_commands(its);				\
	raw_spin_unlock_irqrestore(&its->lock, flags);			\
									\
1154
	if (its_wait_for_range_completion(its, rd_idx, next_cmd))	\
1155
		pr_err_ratelimited("ITS cmd %ps failed\n", builder);	\
1156
}
1157

1158 1159
static void its_build_sync_cmd(struct its_node *its,
			       struct its_cmd_block *sync_cmd,
1160 1161 1162 1163
			       struct its_collection *sync_col)
{
	its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
	its_encode_target(sync_cmd, sync_col->target_address);
1164

1165
	its_fixup_cmd(sync_cmd);
1166 1167
}

1168 1169 1170
static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
			     struct its_collection, its_build_sync_cmd)

1171 1172
static void its_build_vsync_cmd(struct its_node *its,
				struct its_cmd_block *sync_cmd,
1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183
				struct its_vpe *sync_vpe)
{
	its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
	its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);

	its_fixup_cmd(sync_cmd);
}

static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
			     struct its_vpe, its_build_vsync_cmd)

1184
static void its_send_int(struct its_device *dev, u32 event_id)
1185
{
1186
	struct its_cmd_desc desc;
1187

1188 1189
	desc.its_int_cmd.dev = dev;
	desc.its_int_cmd.event_id = event_id;
1190

1191 1192
	its_send_single_command(dev->its, its_build_int_cmd, &desc);
}
1193

1194 1195 1196
static void its_send_clear(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;
1197

1198 1199
	desc.its_clear_cmd.dev = dev;
	desc.its_clear_cmd.event_id = event_id;
1200

1201
	its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234
}

static void its_send_inv(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;

	desc.its_inv_cmd.dev = dev;
	desc.its_inv_cmd.event_id = event_id;

	its_send_single_command(dev->its, its_build_inv_cmd, &desc);
}

static void its_send_mapd(struct its_device *dev, int valid)
{
	struct its_cmd_desc desc;

	desc.its_mapd_cmd.dev = dev;
	desc.its_mapd_cmd.valid = !!valid;

	its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
}

static void its_send_mapc(struct its_node *its, struct its_collection *col,
			  int valid)
{
	struct its_cmd_desc desc;

	desc.its_mapc_cmd.col = col;
	desc.its_mapc_cmd.valid = !!valid;

	its_send_single_command(its, its_build_mapc_cmd, &desc);
}

1235
static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1236 1237 1238
{
	struct its_cmd_desc desc;

1239 1240 1241
	desc.its_mapti_cmd.dev = dev;
	desc.its_mapti_cmd.phys_id = irq_id;
	desc.its_mapti_cmd.event_id = id;
1242

1243
	its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1244 1245 1246 1247 1248 1249 1250 1251 1252
}

static void its_send_movi(struct its_device *dev,
			  struct its_collection *col, u32 id)
{
	struct its_cmd_desc desc;

	desc.its_movi_cmd.dev = dev;
	desc.its_movi_cmd.col = col;
1253
	desc.its_movi_cmd.event_id = id;
1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275

	its_send_single_command(dev->its, its_build_movi_cmd, &desc);
}

static void its_send_discard(struct its_device *dev, u32 id)
{
	struct its_cmd_desc desc;

	desc.its_discard_cmd.dev = dev;
	desc.its_discard_cmd.event_id = id;

	its_send_single_command(dev->its, its_build_discard_cmd, &desc);
}

static void its_send_invall(struct its_node *its, struct its_collection *col)
{
	struct its_cmd_desc desc;

	desc.its_invall_cmd.col = col;

	its_send_single_command(its, its_build_invall_cmd, &desc);
}
1276

1277 1278
static void its_send_vmapti(struct its_device *dev, u32 id)
{
1279
	struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292
	struct its_cmd_desc desc;

	desc.its_vmapti_cmd.vpe = map->vpe;
	desc.its_vmapti_cmd.dev = dev;
	desc.its_vmapti_cmd.virt_id = map->vintid;
	desc.its_vmapti_cmd.event_id = id;
	desc.its_vmapti_cmd.db_enabled = map->db_enabled;

	its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
}

static void its_send_vmovi(struct its_device *dev, u32 id)
{
1293
	struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
	struct its_cmd_desc desc;

	desc.its_vmovi_cmd.vpe = map->vpe;
	desc.its_vmovi_cmd.dev = dev;
	desc.its_vmovi_cmd.event_id = id;
	desc.its_vmovi_cmd.db_enabled = map->db_enabled;

	its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
}

1304 1305
static void its_send_vmapp(struct its_node *its,
			   struct its_vpe *vpe, bool valid)
1306 1307 1308 1309 1310
{
	struct its_cmd_desc desc;

	desc.its_vmapp_cmd.vpe = vpe;
	desc.its_vmapp_cmd.valid = valid;
1311
	desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1312

1313
	its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1314 1315
}

1316 1317
static void its_send_vmovp(struct its_vpe *vpe)
{
1318
	struct its_cmd_desc desc = {};
1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342
	struct its_node *its;
	unsigned long flags;
	int col_id = vpe->col_idx;

	desc.its_vmovp_cmd.vpe = vpe;

	if (!its_list_map) {
		its = list_first_entry(&its_nodes, struct its_node, entry);
		desc.its_vmovp_cmd.col = &its->collections[col_id];
		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
		return;
	}

	/*
	 * Yet another marvel of the architecture. If using the
	 * its_list "feature", we need to make sure that all ITSs
	 * receive all VMOVP commands in the same order. The only way
	 * to guarantee this is to make vmovp a serialization point.
	 *
	 * Wall <-- Head.
	 */
	raw_spin_lock_irqsave(&vmovp_lock, flags);

	desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1343
	desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1344 1345 1346

	/* Emit VMOVPs */
	list_for_each_entry(its, &its_nodes, entry) {
1347
		if (!is_v4(its))
1348 1349
			continue;

1350
		if (!require_its_list_vmovp(vpe->its_vm, its))
1351 1352
			continue;

1353 1354 1355 1356 1357 1358 1359
		desc.its_vmovp_cmd.col = &its->collections[col_id];
		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
	}

	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
}

1360
static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1361 1362 1363 1364
{
	struct its_cmd_desc desc;

	desc.its_vinvall_cmd.vpe = vpe;
1365
	its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1366 1367
}

1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
static void its_send_vinv(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;

	/*
	 * There is no real VINV command. This is just a normal INV,
	 * with a VSYNC instead of a SYNC.
	 */
	desc.its_inv_cmd.dev = dev;
	desc.its_inv_cmd.event_id = event_id;

	its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
}

1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
static void its_send_vint(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;

	/*
	 * There is no real VINT command. This is just a normal INT,
	 * with a VSYNC instead of a SYNC.
	 */
	desc.its_int_cmd.dev = dev;
	desc.its_int_cmd.event_id = event_id;

	its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
}

static void its_send_vclear(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;

	/*
	 * There is no real VCLEAR command. This is just a normal CLEAR,
	 * with a VSYNC instead of a SYNC.
	 */
	desc.its_clear_cmd.dev = dev;
	desc.its_clear_cmd.event_id = event_id;

	its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
}

1410 1411 1412 1413 1414 1415 1416 1417
static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
{
	struct its_cmd_desc desc;

	desc.its_invdb_cmd.vpe = vpe;
	its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
}

1418 1419 1420
/*
 * irqchip functions - assumes MSI, mostly.
 */
1421
static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1422
{
1423
	struct its_vlpi_map *map = get_vlpi_map(d);
1424
	irq_hw_number_t hwirq;
1425
	void *va;
1426
	u8 *cfg;
1427

1428 1429
	if (map) {
		va = page_address(map->vm->vprop_page);
1430 1431 1432 1433 1434
		hwirq = map->vintid;

		/* Remember the updated property */
		map->properties &= ~clr;
		map->properties |= set | LPI_PROP_GROUP1;
1435
	} else {
1436
		va = gic_rdists->prop_table_va;
1437 1438
		hwirq = d->hwirq;
	}
1439

1440
	cfg = va + hwirq - 8192;
1441
	*cfg &= ~clr;
1442
	*cfg |= set | LPI_PROP_GROUP1;
1443 1444 1445 1446 1447 1448 1449

	/*
	 * Make the above write visible to the redistributors.
	 * And yes, we're flushing exactly: One. Single. Byte.
	 * Humpf...
	 */
	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1450
		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1451 1452
	else
		dsb(ishst);
1453 1454
}

1455 1456
static void wait_for_syncr(void __iomem *rdbase)
{
1457
	while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1458 1459 1460
		cpu_relax();
}

1461
static void __direct_lpi_inv(struct irq_data *d, u64 val)
1462 1463
{
	void __iomem *rdbase;
1464 1465
	unsigned long flags;
	int cpu;
1466

1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
	/* Target the redistributor this LPI is currently routed to */
	cpu = irq_to_cpuid_lock(d, &flags);
	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);

	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
	gic_write_lpir(val, rdbase + GICR_INVLPIR);
	wait_for_syncr(rdbase);

	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
	irq_to_cpuid_unlock(d, flags);
}

static void direct_lpi_inv(struct irq_data *d)
{
	struct its_vlpi_map *map = get_vlpi_map(d);
	u64 val;

1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494
	if (map) {
		struct its_device *its_dev = irq_data_get_irq_chip_data(d);

		WARN_ON(!is_v4_1(its_dev->its));

		val  = GICR_INVLPIR_V;
		val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
		val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
	} else {
		val = d->hwirq;
	}
1495

1496
	__direct_lpi_inv(d, val);
1497 1498
}

1499 1500 1501 1502 1503
static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);

	lpi_write_config(d, clr, set);
1504 1505
	if (gic_rdists->has_direct_lpi &&
	    (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1506
		direct_lpi_inv(d);
1507
	else if (!irqd_is_forwarded_to_vcpu(d))
1508
		its_send_inv(its_dev, its_get_event_id(d));
1509 1510
	else
		its_send_vinv(its_dev, its_get_event_id(d));
1511 1512
}

1513 1514 1515 1516
static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);
1517
	struct its_vlpi_map *map;
1518

1519 1520 1521 1522 1523 1524 1525
	/*
	 * GICv4.1 does away with the per-LPI nonsense, nothing to do
	 * here.
	 */
	if (is_v4_1(its_dev->its))
		return;

1526 1527 1528
	map = dev_event_to_vlpi_map(its_dev, event);

	if (map->db_enabled == enable)
1529 1530
		return;

1531
	map->db_enabled = enable;
1532 1533 1534 1535 1536 1537

	/*
	 * More fun with the architecture:
	 *
	 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
	 * value or to 1023, depending on the enable bit. But that
Ingo Molnar's avatar
Ingo Molnar committed
1538
	 * would be issuing a mapping for an /existing/ DevID+EventID
1539 1540 1541 1542 1543
	 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
	 * to the /same/ vPE, using this opportunity to adjust the
	 * doorbell. Mouahahahaha. We loves it, Precious.
	 */
	its_send_vmovi(its_dev, event);
1544 1545 1546 1547
}

static void its_mask_irq(struct irq_data *d)
{
1548 1549 1550
	if (irqd_is_forwarded_to_vcpu(d))
		its_vlpi_set_doorbell(d, false);

1551
	lpi_update_config(d, LPI_PROP_ENABLED, 0);
1552 1553 1554 1555
}

static void its_unmask_irq(struct irq_data *d)
{
1556 1557 1558
	if (irqd_is_forwarded_to_vcpu(d))
		its_vlpi_set_doorbell(d, true);

1559
	lpi_update_config(d, 0, LPI_PROP_ENABLED);
1560 1561
}

1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585
static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
{
	if (irqd_affinity_is_managed(d))
		return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);

	return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
}

static void its_inc_lpi_count(struct irq_data *d, int cpu)
{
	if (irqd_affinity_is_managed(d))
		atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
	else
		atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
}

static void its_dec_lpi_count(struct irq_data *d, int cpu)
{
	if (irqd_affinity_is_managed(d))
		atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
	else
		atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
}

1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
					      const struct cpumask *cpu_mask)
{
	unsigned int cpu = nr_cpu_ids, tmp;
	int count = S32_MAX;

	for_each_cpu(tmp, cpu_mask) {
		int this_count = its_read_lpi_count(d, tmp);
		if (this_count < count) {
			cpu = tmp;
		        count = this_count;
		}
	}

	return cpu;
}

/*
 * As suggested by Thomas Gleixner in:
 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
 */
static int its_select_cpu(struct irq_data *d,
			  const struct cpumask *aff_mask)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1611 1612 1613 1614
	static DEFINE_RAW_SPINLOCK(tmpmask_lock);
	static struct cpumask __tmpmask;
	struct cpumask *tmpmask;
	unsigned long flags;
1615 1616
	int cpu, node;
	node = its_dev->its->numa_node;
1617 1618 1619
	tmpmask = &__tmpmask;

	raw_spin_lock_irqsave(&tmpmask_lock, flags);
1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662

	if (!irqd_affinity_is_managed(d)) {
		/* First try the NUMA node */
		if (node != NUMA_NO_NODE) {
			/*
			 * Try the intersection of the affinity mask and the
			 * node mask (and the online mask, just to be safe).
			 */
			cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
			cpumask_and(tmpmask, tmpmask, cpu_online_mask);

			/*
			 * Ideally, we would check if the mask is empty, and
			 * try again on the full node here.
			 *
			 * But it turns out that the way ACPI describes the
			 * affinity for ITSs only deals about memory, and
			 * not target CPUs, so it cannot describe a single
			 * ITS placed next to two NUMA nodes.
			 *
			 * Instead, just fallback on the online mask. This
			 * diverges from Thomas' suggestion above.
			 */
			cpu = cpumask_pick_least_loaded(d, tmpmask);
			if (cpu < nr_cpu_ids)
				goto out;

			/* If we can't cross sockets, give up */
			if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
				goto out;

			/* If the above failed, expand the search */
		}

		/* Try the intersection of the affinity and online masks */
		cpumask_and(tmpmask, aff_mask, cpu_online_mask);

		/* If that doesn't fly, the online mask is the last resort */
		if (cpumask_empty(tmpmask))
			cpumask_copy(tmpmask, cpu_online_mask);

		cpu = cpumask_pick_least_loaded(d, tmpmask);
	} else {
1663
		cpumask_copy(tmpmask, aff_mask);
1664 1665 1666 1667 1668 1669 1670 1671 1672

		/* If we cannot cross sockets, limit the search to that node */
		if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
		    node != NUMA_NO_NODE)
			cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));

		cpu = cpumask_pick_least_loaded(d, tmpmask);
	}
out:
1673
	raw_spin_unlock_irqrestore(&tmpmask_lock, flags);
1674 1675 1676 1677 1678

	pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
	return cpu;
}

1679 1680 1681 1682 1683 1684
static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
			    bool force)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	struct its_collection *target_col;
	u32 id = its_get_event_id(d);
1685
	int cpu, prev_cpu;
1686

1687 1688 1689 1690
	/* A forwarded interrupt should use irq_set_vcpu_affinity */
	if (irqd_is_forwarded_to_vcpu(d))
		return -EINVAL;

1691 1692 1693
	prev_cpu = its_dev->event_map.col_map[id];
	its_dec_lpi_count(d, prev_cpu);

1694 1695 1696 1697
	if (!force)
		cpu = its_select_cpu(d, mask_val);
	else
		cpu = cpumask_pick_least_loaded(d, mask_val);
1698

1699
	if (cpu < 0 || cpu >= nr_cpu_ids)
1700
		goto err;
1701

1702
	/* don't set the affinity when the target cpu is same as current one */
1703
	if (cpu != prev_cpu) {
1704 1705 1706
		target_col = &its_dev->its->collections[cpu];
		its_send_movi(its_dev, target_col, id);
		its_dev->event_map.col_map[id] = cpu;
1707
		irq_data_update_effective_affinity(d, cpumask_of(cpu));
1708
	}
1709

1710 1711
	its_inc_lpi_count(d, cpu);

1712
	return IRQ_SET_MASK_OK_DONE;
1713 1714 1715 1716

err:
	its_inc_lpi_count(d, prev_cpu);
	return -EINVAL;
1717 1718
}

1719 1720 1721 1722 1723 1724 1725
static u64 its_irq_get_msi_base(struct its_device *its_dev)
{
	struct its_node *its = its_dev->its;

	return its->phys_base + GITS_TRANSLATER;
}

1726 1727 1728 1729 1730 1731 1732
static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	struct its_node *its;
	u64 addr;

	its = its_dev->its;
1733
	addr = its->get_msi_base(its_dev);
1734

1735 1736
	msg->address_lo		= lower_32_bits(addr);
	msg->address_hi		= upper_32_bits(addr);
1737
	msg->data		= its_get_event_id(d);
1738

1739
	iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1740 1741
}

1742 1743 1744 1745 1746 1747 1748 1749 1750 1751
static int its_irq_set_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which,
				     bool state)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

	if (which != IRQCHIP_STATE_PENDING)
		return -EINVAL;

1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762
	if (irqd_is_forwarded_to_vcpu(d)) {
		if (state)
			its_send_vint(its_dev, event);
		else
			its_send_vclear(its_dev, event);
	} else {
		if (state)
			its_send_int(its_dev, event);
		else
			its_send_clear(its_dev, event);
	}
1763 1764 1765 1766

	return 0;
}

1767 1768 1769 1770 1771
static int its_irq_retrigger(struct irq_data *d)
{
	return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
}

1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791
/*
 * Two favourable cases:
 *
 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
 *     for vSGI delivery
 *
 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
 *     and we're better off mapping all VPEs always
 *
 * If neither (a) nor (b) is true, then we map vPEs on demand.
 *
 */
static bool gic_requires_eager_mapping(void)
{
	if (!its_list_map || gic_rdists->has_rvpeid)
		return true;

	return false;
}

1792 1793 1794 1795
static void its_map_vm(struct its_node *its, struct its_vm *vm)
{
	unsigned long flags;

1796
	if (gic_requires_eager_mapping())
1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811
		return;

	raw_spin_lock_irqsave(&vmovp_lock, flags);

	/*
	 * If the VM wasn't mapped yet, iterate over the vpes and get
	 * them mapped now.
	 */
	vm->vlpi_count[its->list_nr]++;

	if (vm->vlpi_count[its->list_nr] == 1) {
		int i;

		for (i = 0; i < vm->nr_vpes; i++) {
			struct its_vpe *vpe = vm->vpes[i];
1812
			struct irq_data *d = irq_get_irq_data(vpe->irq);
1813 1814 1815 1816 1817

			/* Map the VPE to the first possible CPU */
			vpe->col_idx = cpumask_first(cpu_online_mask);
			its_send_vmapp(its, vpe, true);
			its_send_vinvall(its, vpe);
1818
			irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829
		}
	}

	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
}

static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
{
	unsigned long flags;

	/* Not using the ITS list? Everything is always mapped. */
1830
	if (gic_requires_eager_mapping())
1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844
		return;

	raw_spin_lock_irqsave(&vmovp_lock, flags);

	if (!--vm->vlpi_count[its->list_nr]) {
		int i;

		for (i = 0; i < vm->nr_vpes; i++)
			its_send_vmapp(its, vm->vpes[i], false);
	}

	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
}

1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855
static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

	if (!info->map)
		return -EINVAL;

	if (!its_dev->event_map.vm) {
		struct its_vlpi_map *maps;

1856
		maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1857
			       GFP_ATOMIC);
1858 1859
		if (!maps)
			return -ENOMEM;
1860 1861 1862 1863

		its_dev->event_map.vm = info->map->vm;
		its_dev->event_map.vlpi_maps = maps;
	} else if (its_dev->event_map.vm != info->map->vm) {
1864
		return -EINVAL;
1865 1866 1867 1868 1869 1870 1871 1872 1873
	}

	/* Get our private copy of the mapping information */
	its_dev->event_map.vlpi_maps[event] = *info->map;

	if (irqd_is_forwarded_to_vcpu(d)) {
		/* Already mapped, move it around */
		its_send_vmovi(its_dev, event);
	} else {
1874 1875 1876
		/* Ensure all the VPEs are mapped on this ITS */
		its_map_vm(its_dev->its, info->map->vm);

1877 1878 1879 1880 1881 1882 1883 1884 1885
		/*
		 * Flag the interrupt as forwarded so that we can
		 * start poking the virtual property table.
		 */
		irqd_set_forwarded_to_vcpu(d);

		/* Write out the property to the prop table */
		lpi_write_config(d, 0xff, info->map->properties);

1886 1887 1888 1889 1890 1891 1892 1893 1894 1895
		/* Drop the physical mapping */
		its_send_discard(its_dev, event);

		/* and install the virtual one */
		its_send_vmapti(its_dev, event);

		/* Increment the number of VLPIs */
		its_dev->event_map.nr_vlpis++;
	}

1896
	return 0;
1897 1898 1899 1900 1901
}

static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1902
	struct its_vlpi_map *map;
1903

1904 1905
	map = get_vlpi_map(d);

1906 1907
	if (!its_dev->event_map.vm || !map)
		return -EINVAL;
1908 1909

	/* Copy our mapping information to the incoming request */
1910
	*info->map = *map;
1911

1912
	return 0;
1913 1914 1915 1916 1917 1918 1919
}

static int its_vlpi_unmap(struct irq_data *d)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

1920 1921
	if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
		return -EINVAL;
1922 1923 1924 1925 1926 1927 1928

	/* Drop the virtual mapping */
	its_send_discard(its_dev, event);

	/* and restore the physical one */
	irqd_clr_forwarded_to_vcpu(d);
	its_send_mapti(its_dev, d->hwirq, event);
1929
	lpi_update_config(d, 0xff, (lpi_prop_prio |
1930 1931 1932
				    LPI_PROP_ENABLED |
				    LPI_PROP_GROUP1));

1933 1934 1935
	/* Potentially unmap the VM from this ITS */
	its_unmap_vm(its_dev->its, its_dev->event_map.vm);

1936 1937 1938 1939 1940 1941 1942 1943 1944
	/*
	 * Drop the refcount and make the device available again if
	 * this was the last VLPI.
	 */
	if (!--its_dev->event_map.nr_vlpis) {
		its_dev->event_map.vm = NULL;
		kfree(its_dev->event_map.vlpi_maps);
	}

1945
	return 0;
1946 1947
}

1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963
static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);

	if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
		return -EINVAL;

	if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
		lpi_update_config(d, 0xff, info->config);
	else
		lpi_write_config(d, 0xff, info->config);
	its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));

	return 0;
}

1964 1965 1966 1967 1968 1969
static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	struct its_cmd_info *info = vcpu_info;

	/* Need a v4 ITS */
1970
	if (!is_v4(its_dev->its))
1971 1972
		return -EINVAL;

1973 1974
	guard(raw_spinlock_irq)(&its_dev->event_map.vlpi_lock);

1975 1976 1977 1978
	/* Unmap request? */
	if (!info)
		return its_vlpi_unmap(d);

1979 1980
	switch (info->cmd_type) {
	case MAP_VLPI:
1981
		return its_vlpi_map(d, info);
1982 1983

	case GET_VLPI:
1984
		return its_vlpi_get(d, info);
1985 1986 1987

	case PROP_UPDATE_VLPI:
	case PROP_UPDATE_AND_INV_VLPI:
1988
		return its_vlpi_prop_update(d, info);
1989 1990 1991 1992 1993 1994

	default:
		return -EINVAL;
	}
}

1995 1996 1997 1998
static struct irq_chip its_irq_chip = {
	.name			= "ITS",
	.irq_mask		= its_mask_irq,
	.irq_unmask		= its_unmask_irq,
1999
	.irq_eoi		= irq_chip_eoi_parent,
2000
	.irq_set_affinity	= its_set_affinity,
2001
	.irq_compose_msi_msg	= its_irq_compose_msi_msg,
2002
	.irq_set_irqchip_state	= its_irq_set_irqchip_state,
2003
	.irq_retrigger		= its_irq_retrigger,
2004
	.irq_set_vcpu_affinity	= its_irq_set_vcpu_affinity,
2005 2006
};

2007

2008 2009 2010
/*
 * How we allocate LPIs:
 *
2011 2012 2013 2014 2015 2016 2017 2018
 * lpi_range_list contains ranges of LPIs that are to available to
 * allocate from. To allocate LPIs, just pick the first range that
 * fits the required allocation, and reduce it by the required
 * amount. Once empty, remove the range from the list.
 *
 * To free a range of LPIs, add a free range to the list, sort it and
 * merge the result if the new range happens to be adjacent to an
 * already free block.
2019
 *
2020 2021 2022
 * The consequence of the above is that allocation is cost is low, but
 * freeing is expensive. We assumes that freeing rarely occurs.
 */
2023
#define ITS_MAX_LPI_NRBITS	16 /* 64K LPIs */
2024 2025 2026 2027 2028 2029 2030 2031 2032

static DEFINE_MUTEX(lpi_range_lock);
static LIST_HEAD(lpi_range_list);

struct lpi_range {
	struct list_head	entry;
	u32			base_id;
	u32			span;
};
2033

2034
static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2035
{
2036 2037
	struct lpi_range *range;

2038
	range = kmalloc(sizeof(*range), GFP_KERNEL);
2039 2040 2041 2042 2043 2044
	if (range) {
		range->base_id = base;
		range->span = span;
	}

	return range;
2045 2046
}

2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073
static int alloc_lpi_range(u32 nr_lpis, u32 *base)
{
	struct lpi_range *range, *tmp;
	int err = -ENOSPC;

	mutex_lock(&lpi_range_lock);

	list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
		if (range->span >= nr_lpis) {
			*base = range->base_id;
			range->base_id += nr_lpis;
			range->span -= nr_lpis;

			if (range->span == 0) {
				list_del(&range->entry);
				kfree(range);
			}

			err = 0;
			break;
		}
	}

	mutex_unlock(&lpi_range_lock);

	pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
	return err;
2074 2075
}

2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087
static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
{
	if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
		return;
	if (a->base_id + a->span != b->base_id)
		return;
	b->base_id = a->base_id;
	b->span += a->span;
	list_del(&a->entry);
	kfree(a);
}

2088
static int free_lpi_range(u32 base, u32 nr_lpis)
2089
{
2090
	struct lpi_range *new, *old;
2091 2092

	new = mk_lpi_range(base, nr_lpis);
2093 2094
	if (!new)
		return -ENOMEM;
2095 2096 2097

	mutex_lock(&lpi_range_lock);

2098 2099 2100
	list_for_each_entry_reverse(old, &lpi_range_list, entry) {
		if (old->base_id < base)
			break;
2101
	}
2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115
	/*
	 * old is the last element with ->base_id smaller than base,
	 * so new goes right after it. If there are no elements with
	 * ->base_id smaller than base, &old->entry ends up pointing
	 * at the head of the list, and inserting new it the start of
	 * the list is the right thing to do in that case as well.
	 */
	list_add(&new->entry, &old->entry);
	/*
	 * Now check if we can merge with the preceding and/or
	 * following ranges.
	 */
	merge_lpi_ranges(old, new);
	merge_lpi_ranges(new, list_next_entry(new, entry));
2116 2117

	mutex_unlock(&lpi_range_lock);
2118
	return 0;
2119 2120 2121 2122 2123
}

static int __init its_lpi_init(u32 id_bits)
{
	u32 lpis = (1UL << id_bits) - 8192;
2124
	u32 numlpis;
2125 2126
	int err;

2127 2128 2129 2130 2131 2132 2133 2134
	numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);

	if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
		lpis = numlpis;
		pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
			lpis);
	}

2135 2136 2137 2138 2139 2140 2141 2142
	/*
	 * Initializing the allocator is just the same as freeing the
	 * full range of LPIs.
	 */
	err = free_lpi_range(8192, lpis);
	pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
	return err;
}
2143

2144
static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2145 2146 2147
{
	unsigned long *bitmap = NULL;
	int err = 0;
2148 2149

	do {
2150
		err = alloc_lpi_range(nr_irqs, base);
2151
		if (!err)
2152 2153
			break;

2154 2155
		nr_irqs /= 2;
	} while (nr_irqs > 0);
2156

2157 2158 2159
	if (!nr_irqs)
		err = -ENOSPC;

2160
	if (err)
2161 2162
		goto out;

2163
	bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2164 2165 2166
	if (!bitmap)
		goto out;

2167
	*nr_ids = nr_irqs;
2168 2169

out:
2170 2171 2172
	if (!bitmap)
		*base = *nr_ids = 0;

2173 2174 2175
	return bitmap;
}

2176
static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2177
{
2178
	WARN_ON(free_lpi_range(base, nr_ids));
2179
	bitmap_free(bitmap);
2180
}
2181

2182 2183
static void gic_reset_prop_table(void *va)
{
2184 2185
	/* Regular IRQ priority, Group-1, disabled */
	memset(va, lpi_prop_prio | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2186 2187 2188 2189 2190

	/* Make sure the GIC will observe the written configuration */
	gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
}

2191 2192 2193
static struct page *its_allocate_prop_table(gfp_t gfp_flags)
{
	struct page *prop_page;
2194

2195 2196 2197 2198
	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
	if (!prop_page)
		return NULL;

2199
	gic_reset_prop_table(page_address(prop_page));
2200 2201 2202 2203

	return prop_page;
}

2204 2205 2206 2207 2208
static void its_free_prop_table(struct page *prop_page)
{
	free_pages((unsigned long)page_address(prop_page),
		   get_order(LPI_PROPBASE_SZ));
}
2209

2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224
static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
{
	phys_addr_t start, end, addr_end;
	u64 i;

	/*
	 * We don't bother checking for a kdump kernel as by
	 * construction, the LPI tables are out of this kernel's
	 * memory map.
	 */
	if (is_kdump_kernel())
		return true;

	addr_end = addr + size - 1;

2225
	for_each_reserved_mem_range(i, &start, &end) {
2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236
		if (addr >= start && addr_end <= end)
			return true;
	}

	/* Not found, not a good sign... */
	pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
		&addr, &addr_end);
	add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
	return false;
}

2237 2238 2239 2240 2241 2242 2243 2244
static int gic_reserve_range(phys_addr_t addr, unsigned long size)
{
	if (efi_enabled(EFI_CONFIG_TABLES))
		return efi_mem_reserve_persistent(addr, size);

	return 0;
}

2245
static int __init its_setup_lpi_prop_table(void)
2246
{
2247 2248
	if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
		u64 val;
2249

2250 2251
		val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
		lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2252

2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
		gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
		gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
						     LPI_PROPBASE_SZ,
						     MEMREMAP_WB);
		gic_reset_prop_table(gic_rdists->prop_table_va);
	} else {
		struct page *page;

		lpi_id_bits = min_t(u32,
				    GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
				    ITS_MAX_LPI_NRBITS);
		page = its_allocate_prop_table(GFP_NOWAIT);
		if (!page) {
			pr_err("Failed to allocate PROPBASE\n");
			return -ENOMEM;
		}

		gic_rdists->prop_table_pa = page_to_phys(page);
		gic_rdists->prop_table_va = page_address(page);
2272 2273
		WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
					  LPI_PROPBASE_SZ));
2274
	}
2275 2276 2277

	pr_info("GICv3: using LPI property table @%pa\n",
		&gic_rdists->prop_table_pa);
2278

2279
	return its_lpi_init(lpi_id_bits);
2280 2281 2282 2283 2284
}

static const char *its_base_type_string[] = {
	[GITS_BASER_TYPE_DEVICE]	= "Devices",
	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
2285
	[GITS_BASER_TYPE_RESERVED3]	= "Reserved (3)",
2286 2287 2288 2289 2290 2291
	[GITS_BASER_TYPE_COLLECTION]	= "Interrupt Collections",
	[GITS_BASER_TYPE_RESERVED5] 	= "Reserved (5)",
	[GITS_BASER_TYPE_RESERVED6] 	= "Reserved (6)",
	[GITS_BASER_TYPE_RESERVED7] 	= "Reserved (7)",
};

2292 2293 2294 2295
static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
{
	u32 idx = baser - its->tables;

2296
	return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2297 2298 2299 2300 2301 2302 2303
}

static void its_write_baser(struct its_node *its, struct its_baser *baser,
			    u64 val)
{
	u32 idx = baser - its->tables;

2304
	gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2305 2306 2307
	baser->val = its_read_baser(its, baser);
}

2308
static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2309
			   u64 cache, u64 shr, u32 order, bool indirect)
2310 2311 2312 2313
{
	u64 val = its_read_baser(its, baser);
	u64 esz = GITS_BASER_ENTRY_SIZE(val);
	u64 type = GITS_BASER_TYPE(val);
2314
	u64 baser_phys, tmp;
2315
	u32 alloc_pages, psz;
2316
	struct page *page;
2317 2318
	void *base;

2319
	psz = baser->psz;
2320 2321 2322 2323 2324 2325 2326 2327 2328
	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
	if (alloc_pages > GITS_BASER_PAGES_MAX) {
		pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
			&its->phys_base, its_base_type_string[type],
			alloc_pages, GITS_BASER_PAGES_MAX);
		alloc_pages = GITS_BASER_PAGES_MAX;
		order = get_order(GITS_BASER_PAGES_MAX * psz);
	}

2329 2330
	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
	if (!page)
2331 2332
		return -ENOMEM;

2333
	base = (void *)page_address(page);
2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
	baser_phys = virt_to_phys(base);

	/* Check if the physical address of the memory is above 48bits */
	if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {

		/* 52bit PA is supported only when PageSize=64K */
		if (psz != SZ_64K) {
			pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
			free_pages((unsigned long)base, order);
			return -ENXIO;
		}

		/* Convert 52bit PA to 48bit field */
		baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
	}

2350
retry_baser:
2351
	val = (baser_phys					 |
2352 2353 2354 2355 2356 2357 2358
		(type << GITS_BASER_TYPE_SHIFT)			 |
		((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)	 |
		((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)	 |
		cache						 |
		shr						 |
		GITS_BASER_VALID);

2359 2360
	val |=	indirect ? GITS_BASER_INDIRECT : 0x0;

2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372
	switch (psz) {
	case SZ_4K:
		val |= GITS_BASER_PAGE_SIZE_4K;
		break;
	case SZ_16K:
		val |= GITS_BASER_PAGE_SIZE_16K;
		break;
	case SZ_64K:
		val |= GITS_BASER_PAGE_SIZE_64K;
		break;
	}

2373 2374 2375
	if (!shr)
		gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));

2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387
	its_write_baser(its, baser, val);
	tmp = baser->val;

	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
		/*
		 * Shareability didn't stick. Just use
		 * whatever the read reported, which is likely
		 * to be the only thing this redistributor
		 * supports. If that's zero, make it
		 * non-cacheable as well.
		 */
		shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2388
		if (!shr)
2389
			cache = GITS_BASER_nC;
2390

2391 2392 2393 2394
		goto retry_baser;
	}

	if (val != tmp) {
2395
		pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2396
		       &its->phys_base, its_base_type_string[type],
2397
		       val, tmp);
2398 2399 2400 2401 2402 2403 2404
		free_pages((unsigned long)base, order);
		return -ENXIO;
	}

	baser->order = order;
	baser->base = base;
	baser->psz = psz;
2405
	tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2406

2407
	pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2408
		&its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2409 2410
		its_base_type_string[type],
		(unsigned long)virt_to_phys(base),
2411
		indirect ? "indirect" : "flat", (int)esz,
2412 2413 2414 2415 2416
		psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);

	return 0;
}

2417 2418
static bool its_parse_indirect_baser(struct its_node *its,
				     struct its_baser *baser,
2419
				     u32 *order, u32 ids)
2420
{
2421 2422 2423
	u64 tmp = its_read_baser(its, baser);
	u64 type = GITS_BASER_TYPE(tmp);
	u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2424
	u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2425
	u32 new_order = *order;
2426
	u32 psz = baser->psz;
2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445
	bool indirect = false;

	/* No need to enable Indirection if memory requirement < (psz*2)bytes */
	if ((esz << ids) > (psz * 2)) {
		/*
		 * Find out whether hw supports a single or two-level table by
		 * table by reading bit at offset '62' after writing '1' to it.
		 */
		its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
		indirect = !!(baser->val & GITS_BASER_INDIRECT);

		if (indirect) {
			/*
			 * The size of the lvl2 table is equal to ITS page size
			 * which is 'psz'. For computing lvl1 table size,
			 * subtract ID bits that sparse lvl2 table from 'ids'
			 * which is reported by ITS hardware times lvl1 table
			 * entry size.
			 */
2446
			ids -= ilog2(psz / (int)esz);
2447 2448 2449
			esz = GITS_LVL1_ENTRY_SIZE;
		}
	}
2450 2451 2452 2453 2454

	/*
	 * Allocate as many entries as required to fit the
	 * range of device IDs that the ITS can grok... The ID
	 * space being incredibly sparse, this results in a
2455 2456
	 * massive waste of memory if two-level device table
	 * feature is not supported by hardware.
2457 2458
	 */
	new_order = max_t(u32, get_order(esz << ids), new_order);
2459 2460
	if (new_order > MAX_PAGE_ORDER) {
		new_order = MAX_PAGE_ORDER;
2461
		ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2462
		pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2463
			&its->phys_base, its_base_type_string[type],
2464
			device_ids(its), ids);
2465 2466 2467
	}

	*order = new_order;
2468 2469

	return indirect;
2470 2471
}

2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530
static u32 compute_common_aff(u64 val)
{
	u32 aff, clpiaff;

	aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
	clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);

	return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
}

static u32 compute_its_aff(struct its_node *its)
{
	u64 val;
	u32 svpet;

	/*
	 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
	 * the resulting affinity. We then use that to see if this match
	 * our own affinity.
	 */
	svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
	val  = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
	val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
	return compute_common_aff(val);
}

static struct its_node *find_sibling_its(struct its_node *cur_its)
{
	struct its_node *its;
	u32 aff;

	if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
		return NULL;

	aff = compute_its_aff(cur_its);

	list_for_each_entry(its, &its_nodes, entry) {
		u64 baser;

		if (!is_v4_1(its) || its == cur_its)
			continue;

		if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
			continue;

		if (aff != compute_its_aff(its))
			continue;

		/* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
		baser = its->tables[2].val;
		if (!(baser & GITS_BASER_VALID))
			continue;

		return its;
	}

	return NULL;
}

2531 2532 2533 2534 2535
static void its_free_tables(struct its_node *its)
{
	int i;

	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2536 2537 2538 2539
		if (its->tables[i].base) {
			free_pages((unsigned long)its->tables[i].base,
				   its->tables[i].order);
			its->tables[i].base = NULL;
2540 2541 2542 2543
		}
	}
}

2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591
static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
{
	u64 psz = SZ_64K;

	while (psz) {
		u64 val, gpsz;

		val = its_read_baser(its, baser);
		val &= ~GITS_BASER_PAGE_SIZE_MASK;

		switch (psz) {
		case SZ_64K:
			gpsz = GITS_BASER_PAGE_SIZE_64K;
			break;
		case SZ_16K:
			gpsz = GITS_BASER_PAGE_SIZE_16K;
			break;
		case SZ_4K:
		default:
			gpsz = GITS_BASER_PAGE_SIZE_4K;
			break;
		}

		gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;

		val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
		its_write_baser(its, baser, val);

		if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
			break;

		switch (psz) {
		case SZ_64K:
			psz = SZ_16K;
			break;
		case SZ_16K:
			psz = SZ_4K;
			break;
		case SZ_4K:
		default:
			return -1;
		}
	}

	baser->psz = psz;
	return 0;
}

2592
static int its_alloc_tables(struct its_node *its)
2593 2594
{
	u64 shr = GITS_BASER_InnerShareable;
2595
	u64 cache = GITS_BASER_RaWaWb;
2596
	int err, i;
2597

2598 2599 2600
	if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
		/* erratum 24313: ignore memory access type */
		cache = GITS_BASER_nCnB;
2601

2602 2603 2604 2605 2606
	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) {
		cache = GITS_BASER_nC;
		shr = 0;
	}

2607
	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2608 2609
		struct its_baser *baser = its->tables + i;
		u64 val = its_read_baser(its, baser);
2610
		u64 type = GITS_BASER_TYPE(val);
2611
		bool indirect = false;
2612
		u32 order;
2613

2614
		if (type == GITS_BASER_TYPE_NONE)
2615 2616
			continue;

2617 2618 2619 2620 2621 2622 2623 2624
		if (its_probe_baser_psz(its, baser)) {
			its_free_tables(its);
			return -ENXIO;
		}

		order = get_order(baser->psz);

		switch (type) {
2625
		case GITS_BASER_TYPE_DEVICE:
2626
			indirect = its_parse_indirect_baser(its, baser, &order,
2627
							    device_ids(its));
2628 2629
			break;

2630
		case GITS_BASER_TYPE_VCPU:
2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641
			if (is_v4_1(its)) {
				struct its_node *sibling;

				WARN_ON(i != 2);
				if ((sibling = find_sibling_its(its))) {
					*baser = sibling->tables[2];
					its_write_baser(its, baser, baser->val);
					continue;
				}
			}

2642
			indirect = its_parse_indirect_baser(its, baser, &order,
2643
							    ITS_MAX_VPEID_BITS);
2644 2645
			break;
		}
2646

2647
		err = its_setup_baser(its, baser, cache, shr, order, indirect);
2648 2649 2650
		if (err < 0) {
			its_free_tables(its);
			return err;
2651 2652
		}

2653 2654 2655
		/* Update settings which will be used for next BASERn */
		cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
		shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2656 2657 2658 2659 2660
	}

	return 0;
}

2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687
static u64 inherit_vpe_l1_table_from_its(void)
{
	struct its_node *its;
	u64 val;
	u32 aff;

	val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
	aff = compute_common_aff(val);

	list_for_each_entry(its, &its_nodes, entry) {
		u64 baser, addr;

		if (!is_v4_1(its))
			continue;

		if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
			continue;

		if (aff != compute_its_aff(its))
			continue;

		/* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
		baser = its->tables[2].val;
		if (!(baser & GITS_BASER_VALID))
			continue;

		/* We have a winner! */
2688 2689
		gic_data_rdist()->vpe_l1_base = its->tables[2].base;

2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703
		val  = GICR_VPROPBASER_4_1_VALID;
		if (baser & GITS_BASER_INDIRECT)
			val |= GICR_VPROPBASER_4_1_INDIRECT;
		val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
				  FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
		switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
		case GIC_PAGE_SIZE_64K:
			addr = GITS_BASER_ADDR_48_to_52(baser);
			break;
		default:
			addr = baser & GENMASK_ULL(47, 12);
			break;
		}
		val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2704 2705 2706 2707 2708 2709
		if (rdists_support_shareable()) {
			val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
					  FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
			val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
					  FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
		}
2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733
		val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);

		return val;
	}

	return 0;
}

static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
{
	u32 aff;
	u64 val;
	int cpu;

	val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
	aff = compute_common_aff(val);

	for_each_possible_cpu(cpu) {
		void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;

		if (!base || cpu == smp_processor_id())
			continue;

		val = gic_read_typer(base + GICR_TYPER);
2734
		if (aff != compute_common_aff(val))
2735 2736 2737 2738 2739 2740 2741 2742
			continue;

		/*
		 * At this point, we have a victim. This particular CPU
		 * has already booted, and has an affinity that matches
		 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
		 * Make sure we don't write the Z bit in that case.
		 */
2743
		val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2744 2745
		val &= ~GICR_VPROPBASER_4_1_Z;

2746
		gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2747 2748 2749 2750 2751 2752 2753 2754
		*mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;

		return val;
	}

	return 0;
}

2755 2756 2757
static bool allocate_vpe_l2_table(int cpu, u32 id)
{
	void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2758 2759
	unsigned int psz, esz, idx, npg, gpsz;
	u64 val;
2760 2761 2762 2763 2764 2765
	struct page *page;
	__le64 *table;

	if (!gic_rdists->has_rvpeid)
		return true;

2766 2767 2768 2769
	/* Skip non-present CPUs */
	if (!base)
		return true;

2770
	val  = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2771 2772 2773 2774 2775 2776 2777 2778

	esz  = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
	gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
	npg  = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;

	switch (gpsz) {
	default:
		WARN_ON(1);
2779
		fallthrough;
2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824
	case GIC_PAGE_SIZE_4K:
		psz = SZ_4K;
		break;
	case GIC_PAGE_SIZE_16K:
		psz = SZ_16K;
		break;
	case GIC_PAGE_SIZE_64K:
		psz = SZ_64K;
		break;
	}

	/* Don't allow vpe_id that exceeds single, flat table limit */
	if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
		return (id < (npg * psz / (esz * SZ_8)));

	/* Compute 1st level table index & check if that exceeds table limit */
	idx = id >> ilog2(psz / (esz * SZ_8));
	if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
		return false;

	table = gic_data_rdist_cpu(cpu)->vpe_l1_base;

	/* Allocate memory for 2nd level table */
	if (!table[idx]) {
		page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
		if (!page)
			return false;

		/* Flush Lvl2 table to PoC if hw doesn't support coherency */
		if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
			gic_flush_dcache_to_poc(page_address(page), psz);

		table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);

		/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
		if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
			gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);

		/* Ensure updated table contents are visible to RD hardware */
		dsb(sy);
	}

	return true;
}

2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841
static int allocate_vpe_l1_table(void)
{
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
	u64 val, gpsz, npg, pa;
	unsigned int psz = SZ_64K;
	unsigned int np, epp, esz;
	struct page *page;

	if (!gic_rdists->has_rvpeid)
		return 0;

	/*
	 * if VPENDBASER.Valid is set, disable any previously programmed
	 * VPE by setting PendingLast while clearing Valid. This has the
	 * effect of making sure no doorbell will be generated and we can
	 * then safely clear VPROPBASER.Valid.
	 */
2842 2843
	if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
		gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855
				      vlpi_base + GICR_VPENDBASER);

	/*
	 * If we can inherit the configuration from another RD, let's do
	 * so. Otherwise, we have to go through the allocation process. We
	 * assume that all RDs have the exact same requirements, as
	 * nothing will work otherwise.
	 */
	val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
	if (val & GICR_VPROPBASER_4_1_VALID)
		goto out;

2856
	gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2857 2858 2859 2860 2861 2862 2863 2864 2865
	if (!gic_data_rdist()->vpe_table_mask)
		return -ENOMEM;

	val = inherit_vpe_l1_table_from_its();
	if (val & GICR_VPROPBASER_4_1_VALID)
		goto out;

	/* First probe the page size */
	val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2866 2867
	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
	val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2868 2869 2870 2871 2872 2873
	gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
	esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);

	switch (gpsz) {
	default:
		gpsz = GIC_PAGE_SIZE_4K;
2874
		fallthrough;
2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915
	case GIC_PAGE_SIZE_4K:
		psz = SZ_4K;
		break;
	case GIC_PAGE_SIZE_16K:
		psz = SZ_16K;
		break;
	case GIC_PAGE_SIZE_64K:
		psz = SZ_64K;
		break;
	}

	/*
	 * Start populating the register from scratch, including RO fields
	 * (which we want to print in debug cases...)
	 */
	val = 0;
	val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
	val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);

	/* How many entries per GIC page? */
	esz++;
	epp = psz / (esz * SZ_8);

	/*
	 * If we need more than just a single L1 page, flag the table
	 * as indirect and compute the number of required L1 pages.
	 */
	if (epp < ITS_MAX_VPEID) {
		int nl2;

		val |= GICR_VPROPBASER_4_1_INDIRECT;

		/* Number of L2 pages required to cover the VPEID space */
		nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);

		/* Number of L1 pages to point to the L2 pages */
		npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
	} else {
		npg = 1;
	}

2916
	val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2917 2918 2919 2920 2921 2922

	/* Right, that's the number of CPU pages we need for L1 */
	np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);

	pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
		 np, npg, psz, epp, esz);
2923
	page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2924 2925 2926
	if (!page)
		return -ENOMEM;

2927
	gic_data_rdist()->vpe_l1_base = page_address(page);
2928 2929 2930 2931
	pa = virt_to_phys(page_address(page));
	WARN_ON(!IS_ALIGNED(pa, psz));

	val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2932 2933 2934 2935
	if (rdists_support_shareable()) {
		val |= GICR_VPROPBASER_RaWb;
		val |= GICR_VPROPBASER_InnerShareable;
	}
2936 2937 2938 2939
	val |= GICR_VPROPBASER_4_1_Z;
	val |= GICR_VPROPBASER_4_1_VALID;

out:
2940
	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2941 2942 2943 2944 2945 2946 2947 2948 2949
	cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);

	pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
		 smp_processor_id(), val,
		 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));

	return 0;
}

2950 2951
static int its_alloc_collections(struct its_node *its)
{
2952 2953
	int i;

2954
	its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2955 2956 2957 2958
				   GFP_KERNEL);
	if (!its->collections)
		return -ENOMEM;

2959 2960 2961
	for (i = 0; i < nr_cpu_ids; i++)
		its->collections[i].target_address = ~0ULL;

2962 2963 2964
	return 0;
}

2965 2966 2967
static struct page *its_allocate_pending_table(gfp_t gfp_flags)
{
	struct page *pend_page;
2968

2969
	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2970
				get_order(LPI_PENDBASE_SZ));
2971 2972 2973 2974 2975 2976 2977 2978 2979
	if (!pend_page)
		return NULL;

	/* Make sure the GIC will observe the zero-ed page */
	gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);

	return pend_page;
}

2980 2981
static void its_free_pending_table(struct page *pt)
{
2982
	free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2983 2984
}

2985
/*
2986 2987
 * Booting with kdump and LPIs enabled is generally fine. Any other
 * case is wrong in the absence of firmware/EFI support.
2988
 */
2989 2990
static bool enabled_lpis_allowed(void)
{
2991 2992
	phys_addr_t addr;
	u64 val;
2993

2994 2995 2996 2997 2998
	/* Check whether the property table is in a reserved region */
	val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
	addr = val & GENMASK_ULL(51, 12);

	return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2999 3000
}

3001
static int __init allocate_lpi_tables(void)
3002
{
3003
	u64 val;
3004
	int err, cpu;
3005

3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016
	/*
	 * If LPIs are enabled while we run this from the boot CPU,
	 * flag the RD tables as pre-allocated if the stars do align.
	 */
	val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
	if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
		gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
				      RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
		pr_info("GICv3: Using preallocated redistributor tables\n");
	}

3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027
	err = its_setup_lpi_prop_table();
	if (err)
		return err;

	/*
	 * We allocate all the pending tables anyway, as we may have a
	 * mix of RDs that have had LPIs enabled, and some that
	 * don't. We'll free the unused ones as each CPU comes online.
	 */
	for_each_possible_cpu(cpu) {
		struct page *pend_page;
3028 3029

		pend_page = its_allocate_pending_table(GFP_NOWAIT);
3030
		if (!pend_page) {
3031 3032
			pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
			return -ENOMEM;
3033 3034
		}

3035
		gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3036 3037
	}

3038 3039 3040
	return 0;
}

3041
static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
3042 3043 3044 3045 3046 3047
{
	u32 count = 1000000;	/* 1s! */
	bool clean;
	u64 val;

	do {
3048
		val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3049 3050 3051 3052 3053 3054 3055 3056
		clean = !(val & GICR_VPENDBASER_Dirty);
		if (!clean) {
			count--;
			cpu_relax();
			udelay(1);
		}
	} while (!clean && count);

3057
	if (unlikely(!clean))
3058
		pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075

	return val;
}

static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
{
	u64 val;

	/* Make sure we wait until the RD is done with the initial scan */
	val = read_vpend_dirty_clear(vlpi_base);
	val &= ~GICR_VPENDBASER_Valid;
	val &= ~clr;
	val |= set;
	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);

	val = read_vpend_dirty_clear(vlpi_base);
	if (unlikely(val & GICR_VPENDBASER_Dirty))
3076 3077
		val |= GICR_VPENDBASER_PendingLast;

3078 3079 3080
	return val;
}

3081 3082 3083 3084 3085 3086 3087
static void its_cpu_init_lpis(void)
{
	void __iomem *rbase = gic_data_rdist_rd_base();
	struct page *pend_page;
	phys_addr_t paddr;
	u64 val, tmp;

3088
	if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)
3089 3090
		return;

3091 3092 3093
	val = readl_relaxed(rbase + GICR_CTLR);
	if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
	    (val & GICR_CTLR_ENABLE_LPIS)) {
3094 3095 3096 3097 3098 3099 3100 3101 3102
		/*
		 * Check that we get the same property table on all
		 * RDs. If we don't, this is hopeless.
		 */
		paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
		paddr &= GENMASK_ULL(51, 12);
		if (WARN_ON(gic_rdists->prop_table_pa != paddr))
			add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);

3103 3104 3105
		paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
		paddr &= GENMASK_ULL(51, 16);

3106
		WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3107
		gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED;
3108 3109 3110 3111

		goto out;
	}

3112 3113 3114
	pend_page = gic_data_rdist()->pend_page;
	paddr = page_to_phys(pend_page);

3115
	/* set PROPBASE */
3116
	val = (gic_rdists->prop_table_pa |
3117
	       GICR_PROPBASER_InnerShareable |
3118
	       GICR_PROPBASER_RaWaWb |
3119 3120
	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));

3121 3122
	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3123

3124
	if (!rdists_support_shareable())
3125 3126
		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;

3127
	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3128 3129 3130 3131 3132 3133 3134 3135 3136
		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
			/*
			 * The HW reports non-shareable, we must
			 * remove the cacheability attributes as
			 * well.
			 */
			val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
				 GICR_PROPBASER_CACHEABILITY_MASK);
			val |= GICR_PROPBASER_nC;
3137
			gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3138
		}
3139 3140 3141 3142 3143 3144
		pr_info_once("GIC: using cache flushing for LPI property table\n");
		gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
	}

	/* set PENDBASE */
	val = (page_to_phys(pend_page) |
3145
	       GICR_PENDBASER_InnerShareable |
3146
	       GICR_PENDBASER_RaWaWb);
3147

3148 3149
	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3150

3151
	if (!rdists_support_shareable())
3152 3153
		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;

3154 3155 3156 3157 3158 3159 3160 3161
	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
		/*
		 * The HW reports non-shareable, we must remove the
		 * cacheability attributes as well.
		 */
		val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
			 GICR_PENDBASER_CACHEABILITY_MASK);
		val |= GICR_PENDBASER_nC;
3162
		gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3163
	}
3164 3165 3166 3167 3168 3169

	/* Enable LPIs */
	val = readl_relaxed(rbase + GICR_CTLR);
	val |= GICR_CTLR_ENABLE_LPIS;
	writel_relaxed(val, rbase + GICR_CTLR);

3170
out:
3171
	if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3172 3173 3174 3175
		void __iomem *vlpi_base = gic_data_rdist_vlpi_base();

		/*
		 * It's possible for CPU to receive VLPIs before it is
Ingo Molnar's avatar
Ingo Molnar committed
3176
		 * scheduled as a vPE, especially for the first CPU, and the
3177 3178 3179 3180 3181 3182 3183
		 * VLPI with INTID larger than 2^(IDbits+1) will be considered
		 * as out of range and dropped by GIC.
		 * So we initialize IDbits to known value to avoid VLPI drop.
		 */
		val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
		pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
			smp_processor_id(), val);
3184
		gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3185 3186 3187 3188 3189 3190

		/*
		 * Also clear Valid bit of GICR_VPENDBASER, in case some
		 * ancient programming gets left in and has possibility of
		 * corrupting memory.
		 */
3191
		val = its_clear_vpend_valid(vlpi_base, 0, 0);
3192 3193
	}

3194 3195 3196 3197 3198 3199 3200 3201 3202 3203
	if (allocate_vpe_l1_table()) {
		/*
		 * If the allocation has failed, we're in massive trouble.
		 * Disable direct injection, and pray that no VM was
		 * already running...
		 */
		gic_rdists->has_rvpeid = false;
		gic_rdists->has_vlpis = false;
	}

3204 3205
	/* Make sure the GIC has seen the above */
	dsb(sy);
3206
	gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED;
3207
	pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3208
		smp_processor_id(),
3209 3210
		gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ?
		"reserved" : "allocated",
3211
		&paddr);
3212 3213
}

3214
static void its_cpu_init_collection(struct its_node *its)
3215
{
3216 3217
	int cpu = smp_processor_id();
	u64 target;
3218

3219 3220 3221
	/* avoid cross node collections and its mapping */
	if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
		struct device_node *cpu_node;
3222

3223 3224 3225 3226 3227
		cpu_node = of_get_cpu_node(cpu, NULL);
		if (its->numa_node != NUMA_NO_NODE &&
			its->numa_node != of_node_to_nid(cpu_node))
			return;
	}
3228

3229 3230 3231 3232 3233
	/*
	 * We now have to bind each collection to its target
	 * redistributor.
	 */
	if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3234
		/*
3235
		 * This ITS wants the physical address of the
3236 3237
		 * redistributor.
		 */
3238 3239 3240 3241 3242 3243
		target = gic_data_rdist()->phys_base;
	} else {
		/* This ITS wants a linear CPU number. */
		target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
		target = GICR_TYPER_CPU_NUMBER(target) << 16;
	}
3244

3245 3246 3247
	/* Perform collection mapping */
	its->collections[cpu].target_address = target;
	its->collections[cpu].col_id = cpu;
3248

3249 3250 3251 3252 3253 3254 3255 3256
	its_send_mapc(its, &its->collections[cpu], 1);
	its_send_invall(its, &its->collections[cpu]);
}

static void its_cpu_init_collections(void)
{
	struct its_node *its;

3257
	raw_spin_lock(&its_lock);
3258 3259 3260

	list_for_each_entry(its, &its_nodes, entry)
		its_cpu_init_collection(its);
3261

3262
	raw_spin_unlock(&its_lock);
3263
}
3264 3265 3266 3267

static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
{
	struct its_device *its_dev = NULL, *tmp;
3268
	unsigned long flags;
3269

3270
	raw_spin_lock_irqsave(&its->lock, flags);
3271 3272 3273 3274 3275 3276 3277 3278

	list_for_each_entry(tmp, &its->its_device_list, entry) {
		if (tmp->device_id == dev_id) {
			its_dev = tmp;
			break;
		}
	}

3279
	raw_spin_unlock_irqrestore(&its->lock, flags);
3280 3281 3282 3283

	return its_dev;
}

3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295
static struct its_baser *its_get_baser(struct its_node *its, u32 type)
{
	int i;

	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
		if (GITS_BASER_TYPE(its->tables[i].val) == type)
			return &its->tables[i];
	}

	return NULL;
}

3296 3297
static bool its_alloc_table_entry(struct its_node *its,
				  struct its_baser *baser, u32 id)
3298 3299 3300 3301 3302 3303 3304 3305
{
	struct page *page;
	u32 esz, idx;
	__le64 *table;

	/* Don't allow device id that exceeds single, flat table limit */
	esz = GITS_BASER_ENTRY_SIZE(baser->val);
	if (!(baser->val & GITS_BASER_INDIRECT))
3306
		return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3307 3308

	/* Compute 1st level table index & check if that exceeds table limit */
3309
	idx = id >> ilog2(baser->psz / esz);
3310 3311 3312 3313 3314 3315 3316
	if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
		return false;

	table = baser->base;

	/* Allocate memory for 2nd level table */
	if (!table[idx]) {
3317 3318
		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
					get_order(baser->psz));
3319 3320 3321 3322 3323
		if (!page)
			return false;

		/* Flush Lvl2 table to PoC if hw doesn't support coherency */
		if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3324
			gic_flush_dcache_to_poc(page_address(page), baser->psz);
3325 3326 3327 3328 3329

		table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);

		/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
		if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3330
			gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3331 3332 3333 3334 3335 3336 3337 3338

		/* Ensure updated table contents are visible to ITS hardware */
		dsb(sy);
	}

	return true;
}

3339 3340 3341 3342 3343 3344 3345 3346
static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
{
	struct its_baser *baser;

	baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);

	/* Don't allow device id that exceeds ITS hardware limit */
	if (!baser)
3347
		return (ilog2(dev_id) < device_ids(its));
3348

3349
	return its_alloc_table_entry(its, baser, dev_id);
3350 3351
}

3352 3353 3354
static bool its_alloc_vpe_table(u32 vpe_id)
{
	struct its_node *its;
3355
	int cpu;
3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366

	/*
	 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
	 * could try and only do it on ITSs corresponding to devices
	 * that have interrupts targeted at this VPE, but the
	 * complexity becomes crazy (and you have tons of memory
	 * anyway, right?).
	 */
	list_for_each_entry(its, &its_nodes, entry) {
		struct its_baser *baser;

3367
		if (!is_v4(its))
3368
			continue;
3369

3370 3371 3372
		baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
		if (!baser)
			return false;
3373

3374
		if (!its_alloc_table_entry(its, baser, vpe_id))
3375
			return false;
3376 3377
	}

3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390
	/* Non v4.1? No need to iterate RDs and go back early. */
	if (!gic_rdists->has_rvpeid)
		return true;

	/*
	 * Make sure the L2 tables are allocated for all copies of
	 * the L1 table on *all* v4.1 RDs.
	 */
	for_each_possible_cpu(cpu) {
		if (!allocate_vpe_l2_table(cpu, vpe_id))
			return false;
	}

3391 3392 3393
	return true;
}

3394
static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3395
					    int nvecs, bool alloc_lpis)
3396 3397
{
	struct its_device *dev;
3398
	unsigned long *lpi_map = NULL;
3399
	unsigned long flags;
3400
	u16 *col_map = NULL;
3401 3402 3403
	void *itt;
	int lpi_base;
	int nr_lpis;
3404
	int nr_ites;
3405 3406
	int sz;

3407
	if (!its_alloc_device_table(its, dev_id))
3408 3409
		return NULL;

3410 3411 3412
	if (WARN_ON(!is_power_of_2(nvecs)))
		nvecs = roundup_pow_of_two(nvecs);

3413
	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3414
	/*
3415 3416
	 * Even if the device wants a single LPI, the ITT must be
	 * sized as a power of two (and you need at least one bit...).
3417
	 */
3418
	nr_ites = max(2, nvecs);
3419
	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3420
	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3421
	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3422
	if (alloc_lpis) {
3423
		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3424
		if (lpi_map)
3425
			col_map = kcalloc(nr_lpis, sizeof(*col_map),
3426 3427
					  GFP_KERNEL);
	} else {
3428
		col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3429 3430 3431
		nr_lpis = 0;
		lpi_base = 0;
	}
3432

3433
	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
3434 3435
		kfree(dev);
		kfree(itt);
3436
		bitmap_free(lpi_map);
3437
		kfree(col_map);
3438 3439 3440
		return NULL;
	}

3441
	gic_flush_dcache_to_poc(itt, sz);
3442

3443 3444
	dev->its = its;
	dev->itt = itt;
3445
	dev->nr_ites = nr_ites;
3446 3447 3448 3449
	dev->event_map.lpi_map = lpi_map;
	dev->event_map.col_map = col_map;
	dev->event_map.lpi_base = lpi_base;
	dev->event_map.nr_lpis = nr_lpis;
3450
	raw_spin_lock_init(&dev->event_map.vlpi_lock);
3451 3452 3453
	dev->device_id = dev_id;
	INIT_LIST_HEAD(&dev->entry);

3454
	raw_spin_lock_irqsave(&its->lock, flags);
3455
	list_add(&dev->entry, &its->its_device_list);
3456
	raw_spin_unlock_irqrestore(&its->lock, flags);
3457 3458 3459 3460 3461 3462 3463 3464 3465

	/* Map device to its ITT */
	its_send_mapd(dev, 1);

	return dev;
}

static void its_free_device(struct its_device *its_dev)
{
3466 3467 3468
	unsigned long flags;

	raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3469
	list_del(&its_dev->entry);
3470
	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3471
	kfree(its_dev->event_map.col_map);
3472 3473 3474
	kfree(its_dev->itt);
	kfree(its_dev);
}
3475

3476
static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3477 3478 3479
{
	int idx;

3480
	/* Find a free LPI region in lpi_map and allocate them. */
3481 3482 3483 3484
	idx = bitmap_find_free_region(dev->event_map.lpi_map,
				      dev->event_map.nr_lpis,
				      get_count_order(nvecs));
	if (idx < 0)
3485 3486
		return -ENOSPC;

3487
	*hwirq = dev->event_map.lpi_base + idx;
3488 3489 3490 3491

	return 0;
}

3492 3493
static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
			   int nvec, msi_alloc_info_t *info)
3494
{
3495 3496
	struct its_node *its;
	struct its_device *its_dev;
3497 3498
	struct msi_domain_info *msi_info;
	u32 dev_id;
3499
	int err = 0;
3500 3501

	/*
3502
	 * We ignore "dev" entirely, and rely on the dev_id that has
3503 3504 3505 3506 3507 3508 3509 3510
	 * been passed via the scratchpad. This limits this domain's
	 * usefulness to upper layers that definitely know that they
	 * are built on top of the ITS.
	 */
	dev_id = info->scratchpad[0].ul;

	msi_info = msi_get_domain_info(domain);
	its = msi_info->data;
3511

3512 3513 3514 3515 3516 3517 3518 3519 3520 3521
	if (!gic_rdists->has_direct_lpi &&
	    vpe_proxy.dev &&
	    vpe_proxy.dev->its == its &&
	    dev_id == vpe_proxy.dev->device_id) {
		/* Bad luck. Get yourself a better implementation */
		WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
			  dev_id);
		return -EINVAL;
	}

3522
	mutex_lock(&its->dev_alloc_lock);
3523
	its_dev = its_find_device(its, dev_id);
3524 3525 3526 3527 3528 3529
	if (its_dev) {
		/*
		 * We already have seen this ID, probably through
		 * another alias (PCI bridge of some sort). No need to
		 * create the device.
		 */
3530
		its_dev->shared = true;
3531
		pr_debug("Reusing ITT for devID %x\n", dev_id);
3532 3533
		goto out;
	}
3534

3535
	its_dev = its_create_device(its, dev_id, nvec, true);
3536 3537 3538 3539
	if (!its_dev) {
		err = -ENOMEM;
		goto out;
	}
3540

3541 3542 3543
	if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)
		its_dev->shared = true;

3544
	pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3545
out:
3546
	mutex_unlock(&its->dev_alloc_lock);
3547
	info->scratchpad[0].ptr = its_dev;
3548
	return err;
3549 3550
}

3551 3552 3553 3554
static struct msi_domain_ops its_msi_domain_ops = {
	.msi_prepare	= its_msi_prepare,
};

3555 3556 3557 3558
static int its_irq_gic_domain_alloc(struct irq_domain *domain,
				    unsigned int virq,
				    irq_hw_number_t hwirq)
{
3559 3560 3561 3562 3563 3564 3565 3566
	struct irq_fwspec fwspec;

	if (irq_domain_get_of_node(domain->parent)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 3;
		fwspec.param[0] = GIC_IRQ_TYPE_LPI;
		fwspec.param[1] = hwirq;
		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3567 3568 3569 3570 3571
	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 2;
		fwspec.param[0] = hwirq;
		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3572 3573 3574
	} else {
		return -EINVAL;
	}
3575

3576
	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3577 3578 3579 3580 3581 3582 3583
}

static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				unsigned int nr_irqs, void *args)
{
	msi_alloc_info_t *info = args;
	struct its_device *its_dev = info->scratchpad[0].ptr;
3584
	struct its_node *its = its_dev->its;
3585
	struct irq_data *irqd;
3586 3587 3588 3589
	irq_hw_number_t hwirq;
	int err;
	int i;

3590 3591 3592
	err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
	if (err)
		return err;
3593

3594 3595 3596 3597
	err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
	if (err)
		return err;

3598 3599
	for (i = 0; i < nr_irqs; i++) {
		err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3600 3601 3602 3603
		if (err)
			return err;

		irq_domain_set_hwirq_and_chip(domain, virq + i,
3604
					      hwirq + i, &its_irq_chip, its_dev);
3605 3606 3607
		irqd = irq_get_irq_data(virq + i);
		irqd_set_single_target(irqd);
		irqd_set_affinity_on_activate(irqd);
3608
		irqd_set_resend_when_in_progress(irqd);
3609
		pr_debug("ID:%d pID:%d vID:%d\n",
3610 3611
			 (int)(hwirq + i - its_dev->event_map.lpi_base),
			 (int)(hwirq + i), virq + i);
3612 3613 3614 3615 3616
	}

	return 0;
}

3617
static int its_irq_domain_activate(struct irq_domain *domain,
3618
				   struct irq_data *d, bool reserve)
3619 3620 3621
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);
3622
	int cpu;
3623

3624 3625 3626
	cpu = its_select_cpu(d, cpu_online_mask);
	if (cpu < 0 || cpu >= nr_cpu_ids)
		return -EINVAL;
3627

3628
	its_inc_lpi_count(d, cpu);
3629 3630
	its_dev->event_map.col_map[event] = cpu;
	irq_data_update_effective_affinity(d, cpumask_of(cpu));
3631

3632
	/* Map the GIC IRQ and event to the device */
3633
	its_send_mapti(its_dev, d->hwirq, event);
3634
	return 0;
3635 3636 3637 3638 3639 3640 3641 3642
}

static void its_irq_domain_deactivate(struct irq_domain *domain,
				      struct irq_data *d)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

3643
	its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3644 3645 3646 3647
	/* Stop the delivery of interrupts */
	its_send_discard(its_dev, event);
}

3648 3649 3650 3651 3652
static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
				unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3653
	struct its_node *its = its_dev->its;
3654 3655
	int i;

3656 3657 3658 3659
	bitmap_release_region(its_dev->event_map.lpi_map,
			      its_get_event_id(irq_domain_get_irq_data(domain, virq)),
			      get_count_order(nr_irqs));

3660 3661 3662 3663
	for (i = 0; i < nr_irqs; i++) {
		struct irq_data *data = irq_domain_get_irq_data(domain,
								virq + i);
		/* Nuke the entry in the domain */
3664
		irq_domain_reset_irq_data(data);
3665 3666
	}

3667 3668 3669 3670
	mutex_lock(&its->dev_alloc_lock);

	/*
	 * If all interrupts have been freed, start mopping the
Ingo Molnar's avatar
Ingo Molnar committed
3671
	 * floor. This is conditioned on the device not being shared.
3672 3673 3674
	 */
	if (!its_dev->shared &&
	    bitmap_empty(its_dev->event_map.lpi_map,
3675
			 its_dev->event_map.nr_lpis)) {
3676 3677 3678
		its_lpi_free(its_dev->event_map.lpi_map,
			     its_dev->event_map.lpi_base,
			     its_dev->event_map.nr_lpis);
3679 3680 3681 3682 3683 3684

		/* Unmap device/itt */
		its_send_mapd(its_dev, 0);
		its_free_device(its_dev);
	}

3685 3686
	mutex_unlock(&its->dev_alloc_lock);

3687 3688 3689 3690 3691 3692
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
}

static const struct irq_domain_ops its_domain_ops = {
	.alloc			= its_irq_domain_alloc,
	.free			= its_irq_domain_free,
3693 3694
	.activate		= its_irq_domain_activate,
	.deactivate		= its_irq_domain_deactivate,
3695
};
3696

3697 3698 3699
/*
 * This is insane.
 *
3700
 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3701 3702 3703 3704 3705 3706 3707
 * likely), the only way to perform an invalidate is to use a fake
 * device to issue an INV command, implying that the LPI has first
 * been mapped to some event on that device. Since this is not exactly
 * cheap, we try to keep that mapping around as long as possible, and
 * only issue an UNMAP if we're short on available slots.
 *
 * Broken by design(tm).
3708 3709 3710 3711 3712 3713 3714
 *
 * GICv4.1, on the other hand, mandates that we're able to invalidate
 * by writing to a MMIO register. It doesn't implement the whole of
 * DirectLPI, but that's good enough. And most of the time, we don't
 * even have to invalidate anything, as the redistributor can be told
 * whether to generate a doorbell or not (we thus leave it enabled,
 * always).
3715 3716 3717
 */
static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
{
3718 3719 3720 3721
	/* GICv4.1 doesn't use a proxy, so nothing to do here */
	if (gic_rdists->has_rvpeid)
		return;

3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743
	/* Already unmapped? */
	if (vpe->vpe_proxy_event == -1)
		return;

	its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
	vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;

	/*
	 * We don't track empty slots at all, so let's move the
	 * next_victim pointer if we can quickly reuse that slot
	 * instead of nuking an existing entry. Not clear that this is
	 * always a win though, and this might just generate a ripple
	 * effect... Let's just hope VPEs don't migrate too often.
	 */
	if (vpe_proxy.vpes[vpe_proxy.next_victim])
		vpe_proxy.next_victim = vpe->vpe_proxy_event;

	vpe->vpe_proxy_event = -1;
}

static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
{
3744 3745 3746 3747
	/* GICv4.1 doesn't use a proxy, so nothing to do here */
	if (gic_rdists->has_rvpeid)
		return;

3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758
	if (!gic_rdists->has_direct_lpi) {
		unsigned long flags;

		raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
		its_vpe_db_proxy_unmap_locked(vpe);
		raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
	}
}

static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
{
3759 3760 3761 3762
	/* GICv4.1 doesn't use a proxy, so nothing to do here */
	if (gic_rdists->has_rvpeid)
		return;

3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779
	/* Already mapped? */
	if (vpe->vpe_proxy_event != -1)
		return;

	/* This slot was already allocated. Kick the other VPE out. */
	if (vpe_proxy.vpes[vpe_proxy.next_victim])
		its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);

	/* Map the new VPE instead */
	vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
	vpe->vpe_proxy_event = vpe_proxy.next_victim;
	vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;

	vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
	its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
}

3780 3781 3782 3783 3784
static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
{
	unsigned long flags;
	struct its_collection *target_col;

3785 3786 3787 3788
	/* GICv4.1 doesn't use a proxy, so nothing to do here */
	if (gic_rdists->has_rvpeid)
		return;

3789 3790 3791 3792 3793
	if (gic_rdists->has_direct_lpi) {
		void __iomem *rdbase;

		rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
		gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3794
		wait_for_syncr(rdbase);
3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809

		return;
	}

	raw_spin_lock_irqsave(&vpe_proxy.lock, flags);

	its_vpe_db_proxy_map_locked(vpe);

	target_col = &vpe_proxy.dev->its->collections[to];
	its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
	vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;

	raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
}

3810 3811 3812 3813 3814
static int its_vpe_set_affinity(struct irq_data *d,
				const struct cpumask *mask_val,
				bool force)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3815 3816
	unsigned int from, cpu = nr_cpu_ids;
	struct cpumask *table_mask;
3817
	unsigned long flags;
3818 3819 3820

	/*
	 * Changing affinity is mega expensive, so let's be as lazy as
3821
	 * we can and only do it if we really have to. Also, if mapped
3822 3823
	 * into the proxy device, we need to move the doorbell
	 * interrupt to its new location.
3824 3825 3826 3827 3828 3829 3830
	 *
	 * Another thing is that changing the affinity of a vPE affects
	 * *other interrupts* such as all the vLPIs that are routed to
	 * this vPE. This means that the irq_desc lock is not enough to
	 * protect us, and that we must ensure nobody samples vpe->col_idx
	 * during the update, hence the lock below which must also be
	 * taken on any vLPI handling path that evaluates vpe->col_idx.
3831
	 */
3832
	from = vpe_to_cpuid_lock(vpe, &flags);
3833
	table_mask = gic_data_rdist_cpu(from)->vpe_table_mask;
3834 3835

	/*
3836 3837
	 * If we are offered another CPU in the same GICv4.1 ITS
	 * affinity, pick this one. Otherwise, any CPU will do.
3838
	 */
3839 3840 3841 3842 3843 3844 3845
	if (table_mask)
		cpu = cpumask_any_and(mask_val, table_mask);
	if (cpu < nr_cpu_ids) {
		if (cpumask_test_cpu(from, mask_val) &&
		    cpumask_test_cpu(from, table_mask))
			cpu = from;
	} else {
3846
		cpu = cpumask_first(mask_val);
3847
	}
3848 3849

	if (from == cpu)
3850
		goto out;
3851

3852 3853
	vpe->col_idx = cpu;

3854 3855 3856 3857
	its_send_vmovp(vpe);
	its_vpe_db_proxy_move(vpe, from, cpu);

out:
3858
	irq_data_update_effective_affinity(d, cpumask_of(cpu));
3859
	vpe_to_cpuid_unlock(vpe, flags);
3860

3861 3862 3863
	return IRQ_SET_MASK_OK_DONE;
}

3864 3865 3866 3867 3868 3869 3870 3871
static void its_wait_vpt_parse_complete(void)
{
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
	u64 val;

	if (!gic_rdists->has_vpend_valid_dirty)
		return;

3872 3873 3874
	WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
						       val,
						       !(val & GICR_VPENDBASER_Dirty),
3875
						       1, 500));
3876 3877
}

3878 3879
static void its_vpe_schedule(struct its_vpe *vpe)
{
3880
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3881 3882 3883 3884 3885 3886
	u64 val;

	/* Schedule the VPE */
	val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
		GENMASK_ULL(51, 12);
	val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3887 3888 3889 3890
	if (rdists_support_shareable()) {
		val |= GICR_VPROPBASER_RaWb;
		val |= GICR_VPROPBASER_InnerShareable;
	}
3891
	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3892 3893 3894

	val  = virt_to_phys(page_address(vpe->vpt_page)) &
		GENMASK_ULL(51, 16);
3895 3896 3897 3898
	if (rdists_support_shareable()) {
		val |= GICR_VPENDBASER_RaWaWb;
		val |= GICR_VPENDBASER_InnerShareable;
	}
3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910
	/*
	 * There is no good way of finding out if the pending table is
	 * empty as we can race against the doorbell interrupt very
	 * easily. So in the end, vpe->pending_last is only an
	 * indication that the vcpu has something pending, not one
	 * that the pending table is empty. A good implementation
	 * would be able to read its coarse map pretty quickly anyway,
	 * making this a tolerable issue.
	 */
	val |= GICR_VPENDBASER_PendingLast;
	val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
	val |= GICR_VPENDBASER_Valid;
3911
	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3912 3913 3914 3915
}

static void its_vpe_deschedule(struct its_vpe *vpe)
{
3916
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3917 3918
	u64 val;

3919
	val = its_clear_vpend_valid(vlpi_base, 0, 0);
3920

3921 3922
	vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
	vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3923 3924
}

3925 3926 3927 3928 3929
static void its_vpe_invall(struct its_vpe *vpe)
{
	struct its_node *its;

	list_for_each_entry(its, &its_nodes, entry) {
3930
		if (!is_v4(its))
3931 3932
			continue;

3933 3934 3935
		if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
			continue;

3936 3937 3938 3939
		/*
		 * Sending a VINVALL to a single ITS is enough, as all
		 * we need is to reach the redistributors.
		 */
3940
		its_send_vinvall(its, vpe);
3941
		return;
3942 3943 3944
	}
}

3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958
static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	struct its_cmd_info *info = vcpu_info;

	switch (info->cmd_type) {
	case SCHEDULE_VPE:
		its_vpe_schedule(vpe);
		return 0;

	case DESCHEDULE_VPE:
		its_vpe_deschedule(vpe);
		return 0;

3959 3960 3961 3962
	case COMMIT_VPE:
		its_wait_vpt_parse_complete();
		return 0;

3963
	case INVALL_VPE:
3964
		its_vpe_invall(vpe);
3965 3966
		return 0;

3967 3968 3969 3970 3971
	default:
		return -EINVAL;
	}
}

3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984
static void its_vpe_send_cmd(struct its_vpe *vpe,
			     void (*cmd)(struct its_device *, u32))
{
	unsigned long flags;

	raw_spin_lock_irqsave(&vpe_proxy.lock, flags);

	its_vpe_db_proxy_map_locked(vpe);
	cmd(vpe_proxy.dev, vpe->vpe_proxy_event);

	raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
}

3985 3986 3987 3988
static void its_vpe_send_inv(struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

3989 3990 3991
	if (gic_rdists->has_direct_lpi)
		__direct_lpi_inv(d, d->parent_data->hwirq);
	else
3992
		its_vpe_send_cmd(vpe, its_send_inv);
3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013
}

static void its_vpe_mask_irq(struct irq_data *d)
{
	/*
	 * We need to unmask the LPI, which is described by the parent
	 * irq_data. Instead of calling into the parent (which won't
	 * exactly do the right thing, let's simply use the
	 * parent_data pointer. Yes, I'm naughty.
	 */
	lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
	its_vpe_send_inv(d);
}

static void its_vpe_unmask_irq(struct irq_data *d)
{
	/* Same hack as above... */
	lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
	its_vpe_send_inv(d);
}

4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030
static int its_vpe_set_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which,
				     bool state)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

	if (which != IRQCHIP_STATE_PENDING)
		return -EINVAL;

	if (gic_rdists->has_direct_lpi) {
		void __iomem *rdbase;

		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
		if (state) {
			gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
		} else {
			gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
4031
			wait_for_syncr(rdbase);
4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042
		}
	} else {
		if (state)
			its_vpe_send_cmd(vpe, its_send_int);
		else
			its_vpe_send_cmd(vpe, its_send_clear);
	}

	return 0;
}

4043 4044 4045 4046 4047
static int its_vpe_retrigger(struct irq_data *d)
{
	return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
}

4048 4049
static struct irq_chip its_vpe_irq_chip = {
	.name			= "GICv4-vpe",
4050 4051 4052
	.irq_mask		= its_vpe_mask_irq,
	.irq_unmask		= its_vpe_unmask_irq,
	.irq_eoi		= irq_chip_eoi_parent,
4053
	.irq_set_affinity	= its_vpe_set_affinity,
4054
	.irq_retrigger		= its_vpe_retrigger,
4055
	.irq_set_irqchip_state	= its_vpe_set_irqchip_state,
4056
	.irq_set_vcpu_affinity	= its_vpe_set_vcpu_affinity,
4057 4058
};

4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102
static struct its_node *find_4_1_its(void)
{
	static struct its_node *its = NULL;

	if (!its) {
		list_for_each_entry(its, &its_nodes, entry) {
			if (is_v4_1(its))
				return its;
		}

		/* Oops? */
		its = NULL;
	}

	return its;
}

static void its_vpe_4_1_send_inv(struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	struct its_node *its;

	/*
	 * GICv4.1 wants doorbells to be invalidated using the
	 * INVDB command in order to be broadcast to all RDs. Send
	 * it to the first valid ITS, and let the HW do its magic.
	 */
	its = find_4_1_its();
	if (its)
		its_send_invdb(its, vpe);
}

static void its_vpe_4_1_mask_irq(struct irq_data *d)
{
	lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
	its_vpe_4_1_send_inv(d);
}

static void its_vpe_4_1_unmask_irq(struct irq_data *d)
{
	lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
	its_vpe_4_1_send_inv(d);
}

4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114
static void its_vpe_4_1_schedule(struct its_vpe *vpe,
				 struct its_cmd_info *info)
{
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
	u64 val = 0;

	/* Schedule the VPE */
	val |= GICR_VPENDBASER_Valid;
	val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
	val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
	val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);

4115
	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4116 4117
}

4118 4119 4120 4121 4122 4123 4124
static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
				   struct its_cmd_info *info)
{
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
	u64 val;

	if (info->req_db) {
4125 4126
		unsigned long flags;

4127 4128 4129 4130 4131
		/*
		 * vPE is going to block: make the vPE non-resident with
		 * PendingLast clear and DB set. The GIC guarantees that if
		 * we read-back PendingLast clear, then a doorbell will be
		 * delivered when an interrupt comes.
4132 4133 4134 4135
		 *
		 * Note the locking to deal with the concurrent update of
		 * pending_last from the doorbell interrupt handler that can
		 * run concurrently.
4136
		 */
4137
		raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4138 4139 4140 4141
		val = its_clear_vpend_valid(vlpi_base,
					    GICR_VPENDBASER_PendingLast,
					    GICR_VPENDBASER_4_1_DB);
		vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4142
		raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154
	} else {
		/*
		 * We're not blocking, so just make the vPE non-resident
		 * with PendingLast set, indicating that we'll be back.
		 */
		val = its_clear_vpend_valid(vlpi_base,
					    0,
					    GICR_VPENDBASER_PendingLast);
		vpe->pending_last = true;
	}
}

4155 4156 4157
static void its_vpe_4_1_invall(struct its_vpe *vpe)
{
	void __iomem *rdbase;
4158
	unsigned long flags;
4159
	u64 val;
4160
	int cpu;
4161 4162 4163 4164 4165

	val  = GICR_INVALLR_V;
	val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);

	/* Target the redistributor this vPE is currently known on */
4166 4167 4168
	cpu = vpe_to_cpuid_lock(vpe, &flags);
	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4169
	gic_write_lpir(val, rdbase + GICR_INVALLR);
4170 4171

	wait_for_syncr(rdbase);
4172 4173
	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
	vpe_to_cpuid_unlock(vpe, flags);
4174 4175
}

4176 4177
static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
4178
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4179 4180 4181 4182
	struct its_cmd_info *info = vcpu_info;

	switch (info->cmd_type) {
	case SCHEDULE_VPE:
4183
		its_vpe_4_1_schedule(vpe, info);
4184 4185 4186
		return 0;

	case DESCHEDULE_VPE:
4187
		its_vpe_4_1_deschedule(vpe, info);
4188 4189
		return 0;

4190 4191 4192 4193
	case COMMIT_VPE:
		its_wait_vpt_parse_complete();
		return 0;

4194
	case INVALL_VPE:
4195
		its_vpe_4_1_invall(vpe);
4196 4197 4198 4199 4200 4201 4202 4203 4204
		return 0;

	default:
		return -EINVAL;
	}
}

static struct irq_chip its_vpe_4_1_irq_chip = {
	.name			= "GICv4.1-vpe",
4205 4206
	.irq_mask		= its_vpe_4_1_mask_irq,
	.irq_unmask		= its_vpe_4_1_unmask_irq,
4207 4208 4209 4210 4211
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_affinity	= its_vpe_set_affinity,
	.irq_set_vcpu_affinity	= its_vpe_4_1_set_vcpu_affinity,
};

4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231
static void its_configure_sgi(struct irq_data *d, bool clear)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	struct its_cmd_desc desc;

	desc.its_vsgi_cmd.vpe = vpe;
	desc.its_vsgi_cmd.sgi = d->hwirq;
	desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
	desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
	desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
	desc.its_vsgi_cmd.clear = clear;

	/*
	 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
	 * destination VPE is mapped there. Since we map them eagerly at
	 * activation time, we're pretty sure the first GICv4.1 ITS will do.
	 */
	its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
}

4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247
static void its_sgi_mask_irq(struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

	vpe->sgi_config[d->hwirq].enabled = false;
	its_configure_sgi(d, false);
}

static void its_sgi_unmask_irq(struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

	vpe->sgi_config[d->hwirq].enabled = true;
	its_configure_sgi(d, false);
}

4248 4249 4250 4251 4252 4253
static int its_sgi_set_affinity(struct irq_data *d,
				const struct cpumask *mask_val,
				bool force)
{
	/*
	 * There is no notion of affinity for virtual SGIs, at least
Ingo Molnar's avatar
Ingo Molnar committed
4254
	 * not on the host (since they can only be targeting a vPE).
4255 4256
	 * Tell the kernel we've done whatever it asked for.
	 */
4257
	irq_data_update_effective_affinity(d, mask_val);
4258 4259 4260
	return IRQ_SET_MASK_OK;
}

4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298
static int its_sgi_set_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which,
				     bool state)
{
	if (which != IRQCHIP_STATE_PENDING)
		return -EINVAL;

	if (state) {
		struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
		struct its_node *its = find_4_1_its();
		u64 val;

		val  = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
		val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
		writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
	} else {
		its_configure_sgi(d, true);
	}

	return 0;
}

static int its_sgi_get_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which, bool *val)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	void __iomem *base;
	unsigned long flags;
	u32 count = 1000000;	/* 1s! */
	u32 status;
	int cpu;

	if (which != IRQCHIP_STATE_PENDING)
		return -EINVAL;

	/*
	 * Locking galore! We can race against two different events:
	 *
Ingo Molnar's avatar
Ingo Molnar committed
4299
	 * - Concurrent vPE affinity change: we must make sure it cannot
4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335
	 *   happen, or we'll talk to the wrong redistributor. This is
	 *   identical to what happens with vLPIs.
	 *
	 * - Concurrent VSGIPENDR access: As it involves accessing two
	 *   MMIO registers, this must be made atomic one way or another.
	 */
	cpu = vpe_to_cpuid_lock(vpe, &flags);
	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
	base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
	writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
	do {
		status = readl_relaxed(base + GICR_VSGIPENDR);
		if (!(status & GICR_VSGIPENDR_BUSY))
			goto out;

		count--;
		if (!count) {
			pr_err_ratelimited("Unable to get SGI status\n");
			goto out;
		}
		cpu_relax();
		udelay(1);
	} while (count);

out:
	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
	vpe_to_cpuid_unlock(vpe, flags);

	if (!count)
		return -ENXIO;

	*val = !!(status & (1 << d->hwirq));

	return 0;
}

4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352
static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	struct its_cmd_info *info = vcpu_info;

	switch (info->cmd_type) {
	case PROP_UPDATE_VSGI:
		vpe->sgi_config[d->hwirq].priority = info->priority;
		vpe->sgi_config[d->hwirq].group = info->group;
		its_configure_sgi(d, false);
		return 0;

	default:
		return -EINVAL;
	}
}

4353 4354
static struct irq_chip its_sgi_irq_chip = {
	.name			= "GICv4.1-sgi",
4355 4356
	.irq_mask		= its_sgi_mask_irq,
	.irq_unmask		= its_sgi_unmask_irq,
4357
	.irq_set_affinity	= its_sgi_set_affinity,
4358 4359
	.irq_set_irqchip_state	= its_sgi_set_irqchip_state,
	.irq_get_irqchip_state	= its_sgi_get_irqchip_state,
4360
	.irq_set_vcpu_affinity	= its_sgi_set_vcpu_affinity,
4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395
};

static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
				    unsigned int virq, unsigned int nr_irqs,
				    void *args)
{
	struct its_vpe *vpe = args;
	int i;

	/* Yes, we do want 16 SGIs */
	WARN_ON(nr_irqs != 16);

	for (i = 0; i < 16; i++) {
		vpe->sgi_config[i].priority = 0;
		vpe->sgi_config[i].enabled = false;
		vpe->sgi_config[i].group = false;

		irq_domain_set_hwirq_and_chip(domain, virq + i, i,
					      &its_sgi_irq_chip, vpe);
		irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
	}

	return 0;
}

static void its_sgi_irq_domain_free(struct irq_domain *domain,
				    unsigned int virq,
				    unsigned int nr_irqs)
{
	/* Nothing to do */
}

static int its_sgi_irq_domain_activate(struct irq_domain *domain,
				       struct irq_data *d, bool reserve)
{
4396 4397
	/* Write out the initial SGI configuration */
	its_configure_sgi(d, false);
4398 4399 4400 4401 4402 4403
	return 0;
}

static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
					  struct irq_data *d)
{
4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

	/*
	 * The VSGI command is awkward:
	 *
	 * - To change the configuration, CLEAR must be set to false,
	 *   leaving the pending bit unchanged.
	 * - To clear the pending bit, CLEAR must be set to true, leaving
	 *   the configuration unchanged.
	 *
	 * You just can't do both at once, hence the two commands below.
	 */
	vpe->sgi_config[d->hwirq].enabled = false;
	its_configure_sgi(d, false);
	its_configure_sgi(d, true);
4419 4420 4421 4422 4423 4424 4425 4426 4427
}

static const struct irq_domain_ops its_sgi_domain_ops = {
	.alloc		= its_sgi_irq_domain_alloc,
	.free		= its_sgi_irq_domain_free,
	.activate	= its_sgi_irq_domain_activate,
	.deactivate	= its_sgi_irq_domain_deactivate,
};

4428 4429
static int its_vpe_id_alloc(void)
{
4430
	return ida_alloc_max(&its_vpeid_ida, ITS_MAX_VPEID - 1, GFP_KERNEL);
4431 4432 4433 4434
}

static void its_vpe_id_free(u16 id)
{
4435
	ida_free(&its_vpeid_ida, id);
4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456
}

static int its_vpe_init(struct its_vpe *vpe)
{
	struct page *vpt_page;
	int vpe_id;

	/* Allocate vpe_id */
	vpe_id = its_vpe_id_alloc();
	if (vpe_id < 0)
		return vpe_id;

	/* Allocate VPT */
	vpt_page = its_allocate_pending_table(GFP_KERNEL);
	if (!vpt_page) {
		its_vpe_id_free(vpe_id);
		return -ENOMEM;
	}

	if (!its_alloc_vpe_table(vpe_id)) {
		its_vpe_id_free(vpe_id);
4457
		its_free_pending_table(vpt_page);
4458 4459 4460
		return -ENOMEM;
	}

4461
	raw_spin_lock_init(&vpe->vpe_lock);
4462 4463
	vpe->vpe_id = vpe_id;
	vpe->vpt_page = vpt_page;
4464 4465 4466 4467
	if (gic_rdists->has_rvpeid)
		atomic_set(&vpe->vmapp_count, 0);
	else
		vpe->vpe_proxy_event = -1;
4468 4469 4470 4471 4472 4473

	return 0;
}

static void its_vpe_teardown(struct its_vpe *vpe)
{
4474
	its_vpe_db_proxy_unmap(vpe);
4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500
	its_vpe_id_free(vpe->vpe_id);
	its_free_pending_table(vpe->vpt_page);
}

static void its_vpe_irq_domain_free(struct irq_domain *domain,
				    unsigned int virq,
				    unsigned int nr_irqs)
{
	struct its_vm *vm = domain->host_data;
	int i;

	irq_domain_free_irqs_parent(domain, virq, nr_irqs);

	for (i = 0; i < nr_irqs; i++) {
		struct irq_data *data = irq_domain_get_irq_data(domain,
								virq + i);
		struct its_vpe *vpe = irq_data_get_irq_chip_data(data);

		BUG_ON(vm != vpe->its_vm);

		clear_bit(data->hwirq, vm->db_bitmap);
		its_vpe_teardown(vpe);
		irq_domain_reset_irq_data(data);
	}

	if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4501
		its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4502 4503 4504 4505 4506 4507 4508
		its_free_prop_table(vm->vprop_page);
	}
}

static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				    unsigned int nr_irqs, void *args)
{
4509
	struct irq_chip *irqchip = &its_vpe_irq_chip;
4510 4511 4512 4513 4514
	struct its_vm *vm = args;
	unsigned long *bitmap;
	struct page *vprop_page;
	int base, nr_ids, i, err = 0;

4515
	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4516 4517 4518 4519
	if (!bitmap)
		return -ENOMEM;

	if (nr_ids < nr_irqs) {
4520
		its_lpi_free(bitmap, base, nr_ids);
4521 4522 4523 4524 4525
		return -ENOMEM;
	}

	vprop_page = its_allocate_prop_table(GFP_KERNEL);
	if (!vprop_page) {
4526
		its_lpi_free(bitmap, base, nr_ids);
4527 4528 4529 4530 4531 4532 4533 4534
		return -ENOMEM;
	}

	vm->db_bitmap = bitmap;
	vm->db_lpi_base = base;
	vm->nr_db_lpis = nr_ids;
	vm->vprop_page = vprop_page;

4535 4536 4537
	if (gic_rdists->has_rvpeid)
		irqchip = &its_vpe_4_1_irq_chip;

4538 4539 4540 4541 4542 4543 4544 4545 4546 4547
	for (i = 0; i < nr_irqs; i++) {
		vm->vpes[i]->vpe_db_lpi = base + i;
		err = its_vpe_init(vm->vpes[i]);
		if (err)
			break;
		err = its_irq_gic_domain_alloc(domain, virq + i,
					       vm->vpes[i]->vpe_db_lpi);
		if (err)
			break;
		irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4548
					      irqchip, vm->vpes[i]);
4549
		set_bit(i, bitmap);
4550
		irqd_set_resend_when_in_progress(irq_get_irq_data(virq + i));
4551 4552
	}

4553 4554
	if (err)
		its_vpe_irq_domain_free(domain, virq, i);
4555 4556 4557 4558

	return err;
}

4559
static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4560
				       struct irq_data *d, bool reserve)
4561 4562
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4563
	struct its_node *its;
4564

4565 4566 4567 4568 4569 4570
	/*
	 * If we use the list map, we issue VMAPP on demand... Unless
	 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
	 * so that VSGIs can work.
	 */
	if (!gic_requires_eager_mapping())
4571
		return 0;
4572 4573 4574

	/* Map the VPE to the first possible CPU */
	vpe->col_idx = cpumask_first(cpu_online_mask);
4575 4576

	list_for_each_entry(its, &its_nodes, entry) {
4577
		if (!is_v4(its))
4578 4579
			continue;

4580
		its_send_vmapp(its, vpe, true);
4581 4582 4583
		its_send_vinvall(its, vpe);
	}

4584 4585
	irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));

4586
	return 0;
4587 4588 4589 4590 4591 4592
}

static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
					  struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4593 4594
	struct its_node *its;

4595
	/*
4596 4597
	 * If we use the list map on GICv4.0, we unmap the VPE once no
	 * VLPIs are associated with the VM.
4598
	 */
4599
	if (!gic_requires_eager_mapping())
4600
		return;
4601

4602
	list_for_each_entry(its, &its_nodes, entry) {
4603
		if (!is_v4(its))
4604
			continue;
4605

4606 4607
		its_send_vmapp(its, vpe, false);
	}
4608 4609 4610 4611 4612 4613 4614 4615 4616

	/*
	 * There may be a direct read to the VPT after unmapping the
	 * vPE, to guarantee the validity of this, we make the VPT
	 * memory coherent with the CPU caches here.
	 */
	if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))
		gic_flush_dcache_to_poc(page_address(vpe->vpt_page),
					LPI_PENDBASE_SZ);
4617 4618
}

4619
static const struct irq_domain_ops its_vpe_domain_ops = {
4620 4621
	.alloc			= its_vpe_irq_domain_alloc,
	.free			= its_vpe_irq_domain_free,
4622 4623
	.activate		= its_vpe_irq_domain_activate,
	.deactivate		= its_vpe_irq_domain_deactivate,
4624 4625
};

4626 4627 4628 4629 4630 4631
static int its_force_quiescent(void __iomem *base)
{
	u32 count = 1000000;	/* 1s */
	u32 val;

	val = readl_relaxed(base + GITS_CTLR);
4632 4633 4634 4635 4636 4637
	/*
	 * GIC architecture specification requires the ITS to be both
	 * disabled and quiescent for writes to GITS_BASER<n> or
	 * GITS_CBASER to not have UNPREDICTABLE results.
	 */
	if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4638 4639 4640
		return 0;

	/* Disable the generation of all interrupts to this ITS */
4641
	val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658
	writel_relaxed(val, base + GITS_CTLR);

	/* Poll GITS_CTLR and wait until ITS becomes quiescent */
	while (1) {
		val = readl_relaxed(base + GITS_CTLR);
		if (val & GITS_CTLR_QUIESCENT)
			return 0;

		count--;
		if (!count)
			return -EBUSY;

		cpu_relax();
		udelay(1);
	}
}

4659
static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4660 4661 4662
{
	struct its_node *its = data;

4663 4664 4665
	/* erratum 22375: only alloc 8MB table size (20 bits) */
	its->typer &= ~GITS_TYPER_DEVBITS;
	its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4666
	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4667 4668

	return true;
4669 4670
}

4671
static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4672 4673 4674 4675
{
	struct its_node *its = data;

	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4676 4677

	return true;
4678 4679
}

4680
static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4681 4682 4683 4684
{
	struct its_node *its = data;

	/* On QDF2400, the size of the ITE is 16Bytes */
4685 4686
	its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
	its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4687 4688

	return true;
4689 4690
}

4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719
static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
{
	struct its_node *its = its_dev->its;

	/*
	 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
	 * which maps 32-bit writes targeted at a separate window of
	 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
	 * with device ID taken from bits [device_id_bits + 1:2] of
	 * the window offset.
	 */
	return its->pre_its_base + (its_dev->device_id << 2);
}

static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
{
	struct its_node *its = data;
	u32 pre_its_window[2];
	u32 ids;

	if (!fwnode_property_read_u32_array(its->fwnode_handle,
					   "socionext,synquacer-pre-its",
					   pre_its_window,
					   ARRAY_SIZE(pre_its_window))) {

		its->pre_its_base = pre_its_window[0];
		its->get_msi_base = its_irq_get_msi_base_pre_its;

		ids = ilog2(pre_its_window[1]) - 2;
4720 4721 4722 4723
		if (device_ids(its) > ids) {
			its->typer &= ~GITS_TYPER_DEVBITS;
			its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
		}
4724 4725

		/* the pre-ITS breaks isolation, so disable MSI remapping */
4726
		its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI;
4727 4728 4729 4730 4731
		return true;
	}
	return false;
}

4732 4733 4734 4735 4736 4737 4738 4739 4740 4741
static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
{
	struct its_node *its = data;

	/*
	 * Hip07 insists on using the wrong address for the VLPI
	 * page. Trick it into doing the right thing...
	 */
	its->vlpi_redist_offset = SZ_128K;
	return true;
4742 4743
}

4744 4745 4746 4747
static bool __maybe_unused its_enable_rk3588001(void *data)
{
	struct its_node *its = data;

4748 4749
	if (!of_machine_is_compatible("rockchip,rk3588") &&
	    !of_machine_is_compatible("rockchip,rk3588s"))
4750 4751 4752 4753 4754 4755 4756 4757
		return false;

	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
	gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;

	return true;
}

4758 4759 4760 4761 4762 4763 4764 4765
static bool its_set_non_coherent(void *data)
{
	struct its_node *its = data;

	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
	return true;
}

4766
static const struct gic_quirk its_quirks[] = {
4767 4768 4769 4770 4771 4772 4773
#ifdef CONFIG_CAVIUM_ERRATUM_22375
	{
		.desc	= "ITS: Cavium errata 22375, 24313",
		.iidr	= 0xa100034c,	/* ThunderX pass 1.x */
		.mask	= 0xffff0fff,
		.init	= its_enable_quirk_cavium_22375,
	},
4774 4775 4776 4777 4778 4779 4780 4781
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23144
	{
		.desc	= "ITS: Cavium erratum 23144",
		.iidr	= 0xa100034c,	/* ThunderX pass 1.x */
		.mask	= 0xffff0fff,
		.init	= its_enable_quirk_cavium_23144,
	},
4782 4783 4784 4785 4786 4787 4788 4789
#endif
#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
	{
		.desc	= "ITS: QDF2400 erratum 0065",
		.iidr	= 0x00001070, /* QDF2400 ITS rev 1.x */
		.mask	= 0xffffffff,
		.init	= its_enable_quirk_qdf2400_e0065,
	},
4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802
#endif
#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
	{
		/*
		 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
		 * implementation, but with a 'pre-ITS' added that requires
		 * special handling in software.
		 */
		.desc	= "ITS: Socionext Synquacer pre-ITS",
		.iidr	= 0x0001143b,
		.mask	= 0xffffffff,
		.init	= its_enable_quirk_socionext_synquacer,
	},
4803 4804 4805 4806 4807 4808 4809 4810
#endif
#ifdef CONFIG_HISILICON_ERRATUM_161600802
	{
		.desc	= "ITS: Hip07 erratum 161600802",
		.iidr	= 0x00000004,
		.mask	= 0xffffffff,
		.init	= its_enable_quirk_hip07_161600802,
	},
4811 4812 4813 4814 4815 4816 4817 4818
#endif
#ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
	{
		.desc   = "ITS: Rockchip erratum RK3588001",
		.iidr   = 0x0201743b,
		.mask   = 0xffffffff,
		.init   = its_enable_rk3588001,
	},
4819
#endif
4820 4821 4822 4823 4824
	{
		.desc   = "ITS: non-coherent attribute",
		.property = "dma-noncoherent",
		.init   = its_set_non_coherent,
	},
4825 4826 4827 4828 4829 4830 4831 4832 4833
	{
	}
};

static void its_enable_quirks(struct its_node *its)
{
	u32 iidr = readl_relaxed(its->base + GITS_IIDR);

	gic_enable_quirks(iidr, its_quirks, its);
4834 4835 4836 4837

	if (is_of_node(its->fwnode_handle))
		gic_enable_of_quirks(to_of_node(its->fwnode_handle),
				     its_quirks, its);
4838 4839
}

4840 4841 4842 4843 4844
static int its_save_disable(void)
{
	struct its_node *its;
	int err = 0;

4845
	raw_spin_lock(&its_lock);
4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870
	list_for_each_entry(its, &its_nodes, entry) {
		void __iomem *base;

		base = its->base;
		its->ctlr_save = readl_relaxed(base + GITS_CTLR);
		err = its_force_quiescent(base);
		if (err) {
			pr_err("ITS@%pa: failed to quiesce: %d\n",
			       &its->phys_base, err);
			writel_relaxed(its->ctlr_save, base + GITS_CTLR);
			goto err;
		}

		its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
	}

err:
	if (err) {
		list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
			void __iomem *base;

			base = its->base;
			writel_relaxed(its->ctlr_save, base + GITS_CTLR);
		}
	}
4871
	raw_spin_unlock(&its_lock);
4872 4873 4874 4875 4876 4877 4878 4879 4880

	return err;
}

static void its_restore_enable(void)
{
	struct its_node *its;
	int ret;

4881
	raw_spin_lock(&its_lock);
4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892
	list_for_each_entry(its, &its_nodes, entry) {
		void __iomem *base;
		int i;

		base = its->base;

		/*
		 * Make sure that the ITS is disabled. If it fails to quiesce,
		 * don't restore it since writing to CBASER or BASER<n>
		 * registers is undefined according to the GIC v3 ITS
		 * Specification.
4893 4894
		 *
		 * Firmware resuming with the ITS enabled is terminally broken.
4895
		 */
4896
		WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922
		ret = its_force_quiescent(base);
		if (ret) {
			pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
			       &its->phys_base, ret);
			continue;
		}

		gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);

		/*
		 * Writing CBASER resets CREADR to 0, so make CWRITER and
		 * cmd_write line up with it.
		 */
		its->cmd_write = its->cmd_base;
		gits_write_cwriter(0, base + GITS_CWRITER);

		/* Restore GITS_BASER from the value cache. */
		for (i = 0; i < GITS_BASER_NR_REGS; i++) {
			struct its_baser *baser = &its->tables[i];

			if (!(baser->val & GITS_BASER_VALID))
				continue;

			its_write_baser(its, baser, baser->val);
		}
		writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4923 4924 4925 4926 4927 4928 4929 4930 4931

		/*
		 * Reinit the collection if it's stored in the ITS. This is
		 * indicated by the col_id being less than the HCC field.
		 * CID < HCC as specified in the GIC v3 Documentation.
		 */
		if (its->collections[smp_processor_id()].col_id <
		    GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
			its_cpu_init_collection(its);
4932
	}
4933
	raw_spin_unlock(&its_lock);
4934 4935 4936 4937 4938 4939 4940
}

static struct syscore_ops its_syscore_ops = {
	.suspend = its_save_disable,
	.resume = its_restore_enable,
};

4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972
static void __init __iomem *its_map_one(struct resource *res, int *err)
{
	void __iomem *its_base;
	u32 val;

	its_base = ioremap(res->start, SZ_64K);
	if (!its_base) {
		pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
		*err = -ENOMEM;
		return NULL;
	}

	val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
	if (val != 0x30 && val != 0x40) {
		pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
		*err = -ENODEV;
		goto out_unmap;
	}

	*err = its_force_quiescent(its_base);
	if (*err) {
		pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
		goto out_unmap;
	}

	return its_base;

out_unmap:
	iounmap(its_base);
	return NULL;
}

4973
static int its_init_domain(struct its_node *its)
4974 4975 4976 4977 4978 4979 4980 4981
{
	struct irq_domain *inner_domain;
	struct msi_domain_info *info;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

4982 4983 4984 4985 4986
	info->ops = &its_msi_domain_ops;
	info->data = its;

	inner_domain = irq_domain_create_hierarchy(its_parent,
						   its->msi_domain_flags, 0,
4987
						   its->fwnode_handle, &its_domain_ops,
4988
						   info);
4989 4990 4991 4992 4993
	if (!inner_domain) {
		kfree(info);
		return -ENOMEM;
	}

4994
	irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4995 4996 4997 4998

	return 0;
}

4999 5000
static int its_init_vpe_domain(void)
{
5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013
	struct its_node *its;
	u32 devid;
	int entries;

	if (gic_rdists->has_direct_lpi) {
		pr_info("ITS: Using DirectLPI for VPE invalidation\n");
		return 0;
	}

	/* Any ITS will do, even if not v4 */
	its = list_first_entry(&its_nodes, struct its_node, entry);

	entries = roundup_pow_of_two(nr_cpu_ids);
5014
	vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
5015
				 GFP_KERNEL);
5016
	if (!vpe_proxy.vpes)
5017 5018 5019
		return -ENOMEM;

	/* Use the last possible DevID */
5020
	devid = GENMASK(device_ids(its) - 1, 0);
5021 5022 5023 5024 5025 5026 5027
	vpe_proxy.dev = its_create_device(its, devid, entries, false);
	if (!vpe_proxy.dev) {
		kfree(vpe_proxy.vpes);
		pr_err("ITS: Can't allocate GICv4 proxy device\n");
		return -ENOMEM;
	}

5028
	BUG_ON(entries > vpe_proxy.dev->nr_ites);
5029 5030 5031 5032 5033 5034

	raw_spin_lock_init(&vpe_proxy.lock);
	vpe_proxy.next_victim = 0;
	pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
		devid, vpe_proxy.dev->nr_ites);

5035 5036 5037
	return 0;
}

5038
static int __init its_compute_its_list_map(struct its_node *its)
5039 5040 5041 5042 5043 5044 5045 5046 5047 5048
{
	int its_number;
	u32 ctlr;

	/*
	 * This is assumed to be done early enough that we're
	 * guaranteed to be single-threaded, hence no
	 * locking. Should this change, we should address
	 * this.
	 */
5049 5050
	its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
	if (its_number >= GICv4_ITS_LIST_MAX) {
5051
		pr_err("ITS@%pa: No ITSList entry available!\n",
5052
		       &its->phys_base);
5053 5054 5055
		return -EINVAL;
	}

5056
	ctlr = readl_relaxed(its->base + GITS_CTLR);
5057 5058
	ctlr &= ~GITS_CTLR_ITS_NUMBER;
	ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
5059 5060
	writel_relaxed(ctlr, its->base + GITS_CTLR);
	ctlr = readl_relaxed(its->base + GITS_CTLR);
5061 5062 5063 5064 5065 5066 5067
	if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
		its_number = ctlr & GITS_CTLR_ITS_NUMBER;
		its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
	}

	if (test_and_set_bit(its_number, &its_list_map)) {
		pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
5068
		       &its->phys_base, its_number);
5069 5070 5071 5072 5073 5074
		return -EINVAL;
	}

	return its_number;
}

5075
static int __init its_probe_one(struct its_node *its)
5076
{
5077
	u64 baser, tmp;
5078
	struct page *page;
5079
	u32 ctlr;
5080 5081
	int err;

5082 5083
	its_enable_quirks(its);

5084
	if (is_v4(its)) {
5085 5086
		if (!(its->typer & GITS_TYPER_VMOVP)) {
			err = its_compute_its_list_map(its);
5087
			if (err < 0)
5088
				goto out;
5089

5090 5091
			its->list_nr = err;

5092
			pr_info("ITS@%pa: Using ITS number %d\n",
5093
				&its->phys_base, err);
5094
		} else {
5095
			pr_info("ITS@%pa: Single VMOVP capable\n", &its->phys_base);
5096
		}
5097 5098

		if (is_v4_1(its)) {
5099
			u32 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
5100

5101
			its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K);
5102 5103
			if (!its->sgir_base) {
				err = -ENOMEM;
5104
				goto out;
5105 5106
			}

5107
			its->mpidr = readl_relaxed(its->base + GITS_MPIDR);
5108 5109

			pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5110
				&its->phys_base, its->mpidr, svpet);
5111
		}
5112 5113
	}

5114 5115 5116
	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
				get_order(ITS_CMD_QUEUE_SZ));
	if (!page) {
5117
		err = -ENOMEM;
5118
		goto out_unmap_sgir;
5119
	}
5120
	its->cmd_base = (void *)page_address(page);
5121 5122
	its->cmd_write = its->cmd_base;

5123
	err = its_alloc_tables(its);
5124 5125 5126 5127 5128 5129 5130 5131
	if (err)
		goto out_free_cmd;

	err = its_alloc_collections(its);
	if (err)
		goto out_free_tables;

	baser = (virt_to_phys(its->cmd_base)	|
5132
		 GITS_CBASER_RaWaWb		|
5133 5134 5135 5136
		 GITS_CBASER_InnerShareable	|
		 (ITS_CMD_QUEUE_SZ / SZ_4K - 1)	|
		 GITS_CBASER_VALID);

5137 5138
	gits_write_cbaser(baser, its->base + GITS_CBASER);
	tmp = gits_read_cbaser(its->base + GITS_CBASER);
5139

5140 5141 5142
	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;

5143
	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5144 5145 5146 5147 5148 5149 5150 5151 5152
		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
			/*
			 * The HW reports non-shareable, we must
			 * remove the cacheability attributes as
			 * well.
			 */
			baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
				   GITS_CBASER_CACHEABILITY_MASK);
			baser |= GITS_CBASER_nC;
5153
			gits_write_cbaser(baser, its->base + GITS_CBASER);
5154
		}
5155 5156 5157 5158
		pr_info("ITS: using cache flushing for cmd queue\n");
		its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
	}

5159
	gits_write_cwriter(0, its->base + GITS_CWRITER);
5160
	ctlr = readl_relaxed(its->base + GITS_CTLR);
5161
	ctlr |= GITS_CTLR_ENABLE;
5162
	if (is_v4(its))
5163 5164
		ctlr |= GITS_CTLR_ImDe;
	writel_relaxed(ctlr, its->base + GITS_CTLR);
5165

5166
	err = its_init_domain(its);
5167 5168
	if (err)
		goto out_free_tables;
5169

5170
	raw_spin_lock(&its_lock);
5171
	list_add(&its->entry, &its_nodes);
5172
	raw_spin_unlock(&its_lock);
5173 5174 5175 5176 5177 5178

	return 0;

out_free_tables:
	its_free_tables(its);
out_free_cmd:
5179
	free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5180 5181 5182
out_unmap_sgir:
	if (its->sgir_base)
		iounmap(its->sgir_base);
5183 5184
out:
	pr_err("ITS@%pa: failed probing (%d)\n", &its->phys_base, err);
5185 5186 5187 5188 5189
	return err;
}

static bool gic_rdists_supports_plpis(void)
{
5190
	return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5191 5192
}

5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207
static int redist_disable_lpis(void)
{
	void __iomem *rbase = gic_data_rdist_rd_base();
	u64 timeout = USEC_PER_SEC;
	u64 val;

	if (!gic_rdists_supports_plpis()) {
		pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
		return -ENXIO;
	}

	val = readl_relaxed(rbase + GICR_CTLR);
	if (!(val & GICR_CTLR_ENABLE_LPIS))
		return 0;

5208 5209 5210 5211
	/*
	 * If coming via a CPU hotplug event, we don't need to disable
	 * LPIs before trying to re-enable them. They are already
	 * configured and all is well in the world.
5212 5213
	 *
	 * If running with preallocated tables, there is nothing to do.
5214
	 */
5215
	if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||
5216
	    (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5217 5218 5219 5220 5221 5222
		return 0;

	/*
	 * From that point on, we only try to do some damage control.
	 */
	pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260
		smp_processor_id());
	add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);

	/* Disable LPIs */
	val &= ~GICR_CTLR_ENABLE_LPIS;
	writel_relaxed(val, rbase + GICR_CTLR);

	/* Make sure any change to GICR_CTLR is observable by the GIC */
	dsb(sy);

	/*
	 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
	 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
	 * Error out if we time out waiting for RWP to clear.
	 */
	while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
		if (!timeout) {
			pr_err("CPU%d: Timeout while disabling LPIs\n",
			       smp_processor_id());
			return -ETIMEDOUT;
		}
		udelay(1);
		timeout--;
	}

	/*
	 * After it has been written to 1, it is IMPLEMENTATION
	 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
	 * cleared to 0. Error out if clearing the bit failed.
	 */
	if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
		pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
		return -EBUSY;
	}

	return 0;
}

5261 5262 5263
int its_cpu_init(void)
{
	if (!list_empty(&its_nodes)) {
5264 5265 5266 5267 5268 5269
		int ret;

		ret = redist_disable_lpis();
		if (ret)
			return ret;

5270
		its_cpu_init_lpis();
5271
		its_cpu_init_collections();
5272 5273 5274 5275 5276
	}

	return 0;
}

5277 5278 5279 5280 5281 5282 5283 5284 5285
static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)
{
	cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state);
	gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
}

static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,
		    rdist_memreserve_cpuhp_cleanup_workfn);

5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313
static int its_cpu_memreserve_lpi(unsigned int cpu)
{
	struct page *pend_page;
	int ret = 0;

	/* This gets to run exactly once per CPU */
	if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)
		return 0;

	pend_page = gic_data_rdist()->pend_page;
	if (WARN_ON(!pend_page)) {
		ret = -ENOMEM;
		goto out;
	}
	/*
	 * If the pending table was pre-programmed, free the memory we
	 * preemptively allocated. Otherwise, reserve that memory for
	 * later kexecs.
	 */
	if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {
		its_free_pending_table(pend_page);
		gic_data_rdist()->pend_page = NULL;
	} else {
		phys_addr_t paddr = page_to_phys(pend_page);
		WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
	}

out:
5314
	/* Last CPU being brought up gets to issue the cleanup */
5315 5316
	if (!IS_ENABLED(CONFIG_SMP) ||
	    cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5317 5318
		schedule_work(&rdist_memreserve_cpuhp_cleanup_work);

5319 5320 5321 5322
	gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
	return ret;
}

5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339
/* Mark all the BASER registers as invalid before they get reprogrammed */
static int __init its_reset_one(struct resource *res)
{
	void __iomem *its_base;
	int err, i;

	its_base = its_map_one(res, &err);
	if (!its_base)
		return err;

	for (i = 0; i < GITS_BASER_NR_REGS; i++)
		gits_write_baser(0, its_base + GITS_BASER + (i << 3));

	iounmap(its_base);
	return 0;
}

5340
static const struct of_device_id its_device_id[] = {
5341 5342 5343 5344
	{	.compatible	= "arm,gic-v3-its",	},
	{},
};

5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369
static struct its_node __init *its_node_init(struct resource *res,
					     struct fwnode_handle *handle, int numa_node)
{
	void __iomem *its_base;
	struct its_node *its;
	int err;

	its_base = its_map_one(res, &err);
	if (!its_base)
		return NULL;

	pr_info("ITS %pR\n", res);

	its = kzalloc(sizeof(*its), GFP_KERNEL);
	if (!its)
		goto out_unmap;

	raw_spin_lock_init(&its->lock);
	mutex_init(&its->dev_alloc_lock);
	INIT_LIST_HEAD(&its->entry);
	INIT_LIST_HEAD(&its->its_device_list);

	its->typer = gic_read_typer(its_base + GITS_TYPER);
	its->base = its_base;
	its->phys_base = res->start;
5370 5371
	its->get_msi_base = its_irq_get_msi_base;
	its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI;
5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388

	its->numa_node = numa_node;
	its->fwnode_handle = handle;

	return its;

out_unmap:
	iounmap(its_base);
	return NULL;
}

static void its_node_destroy(struct its_node *its)
{
	iounmap(its->base);
	kfree(its);
}

5389
static int __init its_of_probe(struct device_node *node)
5390 5391
{
	struct device_node *np;
5392
	struct resource res;
5393
	int err;
5394

5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412
	/*
	 * Make sure *all* the ITS are reset before we probe any, as
	 * they may be sharing memory. If any of the ITS fails to
	 * reset, don't even try to go any further, as this could
	 * result in something even worse.
	 */
	for (np = of_find_matching_node(node, its_device_id); np;
	     np = of_find_matching_node(np, its_device_id)) {
		if (!of_device_is_available(np) ||
		    !of_property_read_bool(np, "msi-controller") ||
		    of_address_to_resource(np, 0, &res))
			continue;

		err = its_reset_one(&res);
		if (err)
			return err;
	}

5413 5414
	for (np = of_find_matching_node(node, its_device_id); np;
	     np = of_find_matching_node(np, its_device_id)) {
5415 5416
		struct its_node *its;

5417 5418
		if (!of_device_is_available(np))
			continue;
5419
		if (!of_property_read_bool(np, "msi-controller")) {
5420 5421
			pr_warn("%pOF: no msi-controller property, ITS ignored\n",
				np);
5422 5423 5424
			continue;
		}

5425
		if (of_address_to_resource(np, 0, &res)) {
5426
			pr_warn("%pOF: no regs?\n", np);
5427 5428 5429
			continue;
		}

5430 5431 5432 5433 5434 5435 5436 5437 5438 5439

		its = its_node_init(&res, &np->fwnode, of_node_to_nid(np));
		if (!its)
			return -ENOMEM;

		err = its_probe_one(its);
		if (err)  {
			its_node_destroy(its);
			return err;
		}
5440
	}
5441 5442 5443
	return 0;
}

5444 5445 5446 5447
#ifdef CONFIG_ACPI

#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)

5448
#ifdef CONFIG_ACPI_NUMA
5449 5450 5451 5452 5453 5454 5455
struct its_srat_map {
	/* numa node id */
	u32	numa_node;
	/* GIC ITS ID */
	u32	its_id;
};

5456
static struct its_srat_map *its_srat_maps __initdata;
5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469
static int its_in_srat __initdata;

static int __init acpi_get_its_numa_node(u32 its_id)
{
	int i;

	for (i = 0; i < its_in_srat; i++) {
		if (its_id == its_srat_maps[i].its_id)
			return its_srat_maps[i].numa_node;
	}
	return NUMA_NO_NODE;
}

5470
static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5471 5472 5473 5474 5475
					  const unsigned long end)
{
	return 0;
}

5476
static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491
			 const unsigned long end)
{
	int node;
	struct acpi_srat_gic_its_affinity *its_affinity;

	its_affinity = (struct acpi_srat_gic_its_affinity *)header;
	if (!its_affinity)
		return -EINVAL;

	if (its_affinity->header.length < sizeof(*its_affinity)) {
		pr_err("SRAT: Invalid header length %d in ITS affinity\n",
			its_affinity->header.length);
		return -EINVAL;
	}

5492 5493 5494 5495 5496 5497
	/*
	 * Note that in theory a new proximity node could be created by this
	 * entry as it is an SRAT resource allocation structure.
	 * We do not currently support doing so.
	 */
	node = pxm_to_node(its_affinity->proximity_domain);
5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514

	if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
		pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
		return 0;
	}

	its_srat_maps[its_in_srat].numa_node = node;
	its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
	its_in_srat++;
	pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
		its_affinity->proximity_domain, its_affinity->its_id, node);

	return 0;
}

static void __init acpi_table_parse_srat_its(void)
{
5515 5516 5517 5518 5519 5520 5521 5522 5523
	int count;

	count = acpi_table_parse_entries(ACPI_SIG_SRAT,
			sizeof(struct acpi_table_srat),
			ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
			gic_acpi_match_srat_its, 0);
	if (count <= 0)
		return;

5524 5525
	its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
				      GFP_KERNEL);
5526
	if (!its_srat_maps)
5527 5528
		return;

5529 5530 5531 5532 5533
	acpi_table_parse_entries(ACPI_SIG_SRAT,
			sizeof(struct acpi_table_srat),
			ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
			gic_acpi_parse_srat_its, 0);
}
5534 5535 5536 5537 5538 5539

/* free the its_srat_maps after ITS probing */
static void __init acpi_its_srat_maps_free(void)
{
	kfree(its_srat_maps);
}
5540 5541 5542
#else
static void __init acpi_table_parse_srat_its(void)	{ }
static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5543
static void __init acpi_its_srat_maps_free(void) { }
5544 5545
#endif

5546
static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5547 5548 5549 5550
					  const unsigned long end)
{
	struct acpi_madt_generic_translator *its_entry;
	struct fwnode_handle *dom_handle;
5551
	struct its_node *its;
5552 5553 5554 5555 5556 5557 5558 5559 5560
	struct resource res;
	int err;

	its_entry = (struct acpi_madt_generic_translator *)header;
	memset(&res, 0, sizeof(res));
	res.start = its_entry->base_address;
	res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
	res.flags = IORESOURCE_MEM;

5561
	dom_handle = irq_domain_alloc_fwnode(&res.start);
5562 5563 5564 5565 5566 5567
	if (!dom_handle) {
		pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
		       &res.start);
		return -ENOMEM;
	}

5568 5569
	err = iort_register_domain_token(its_entry->translation_id, res.start,
					 dom_handle);
5570 5571 5572 5573 5574 5575
	if (err) {
		pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
		       &res.start, its_entry->translation_id);
		goto dom_err;
	}

5576 5577 5578 5579 5580 5581 5582 5583
	its = its_node_init(&res, dom_handle,
			    acpi_get_its_numa_node(its_entry->translation_id));
	if (!its) {
		err = -ENOMEM;
		goto node_err;
	}

	err = its_probe_one(its);
5584 5585 5586
	if (!err)
		return 0;

5587
node_err:
5588 5589 5590 5591 5592 5593
	iort_deregister_domain_token(its_entry->translation_id);
dom_err:
	irq_domain_free_fwnode(dom_handle);
	return err;
}

5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609
static int __init its_acpi_reset(union acpi_subtable_headers *header,
				 const unsigned long end)
{
	struct acpi_madt_generic_translator *its_entry;
	struct resource res;

	its_entry = (struct acpi_madt_generic_translator *)header;
	res = (struct resource) {
		.start	= its_entry->base_address,
		.end	= its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	};

	return its_reset_one(&res);
}

5610 5611
static void __init its_acpi_probe(void)
{
5612
	acpi_table_parse_srat_its();
5613 5614 5615 5616 5617 5618 5619 5620 5621 5622
	/*
	 * Make sure *all* the ITS are reset before we probe any, as
	 * they may be sharing memory. If any of the ITS fails to
	 * reset, don't even try to go any further, as this could
	 * result in something even worse.
	 */
	if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
				  its_acpi_reset, 0) > 0)
		acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
				      gic_acpi_parse_madt_its, 0);
5623
	acpi_its_srat_maps_free();
5624 5625 5626 5627 5628
}
#else
static void __init its_acpi_probe(void) { }
#endif

5629 5630 5631 5632 5633 5634 5635
int __init its_lpi_memreserve_init(void)
{
	int state;

	if (!efi_enabled(EFI_CONFIG_TABLES))
		return 0;

5636 5637 5638
	if (list_empty(&its_nodes))
		return 0;

5639
	gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5640 5641 5642 5643 5644 5645 5646
	state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
				  "irqchip/arm/gicv3/memreserve:online",
				  its_cpu_memreserve_lpi,
				  NULL);
	if (state < 0)
		return state;

5647 5648
	gic_rdists->cpuhp_memreserve_state = state;

5649 5650 5651
	return 0;
}

5652
int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5653
		    struct irq_domain *parent_domain, u8 irq_prio)
5654 5655
{
	struct device_node *of_node;
5656 5657
	struct its_node *its;
	bool has_v4 = false;
5658
	bool has_v4_1 = false;
5659
	int err;
5660

5661 5662
	gic_rdists = rdists;

5663
	lpi_prop_prio = irq_prio;
5664 5665 5666 5667 5668
	its_parent = parent_domain;
	of_node = to_of_node(handle);
	if (of_node)
		its_of_probe(of_node);
	else
5669
		its_acpi_probe();
5670 5671 5672 5673 5674 5675

	if (list_empty(&its_nodes)) {
		pr_warn("ITS: No ITS available, not enabling LPIs\n");
		return -ENXIO;
	}

5676
	err = allocate_lpi_tables();
5677 5678 5679
	if (err)
		return err;

5680
	list_for_each_entry(its, &its_nodes, entry) {
5681
		has_v4 |= is_v4(its);
5682 5683 5684 5685 5686 5687
		has_v4_1 |= is_v4_1(its);
	}

	/* Don't bother with inconsistent systems */
	if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
		rdists->has_rvpeid = false;
5688 5689

	if (has_v4 & rdists->has_vlpis) {
5690 5691 5692 5693 5694 5695 5696
		const struct irq_domain_ops *sgi_ops;

		if (has_v4_1)
			sgi_ops = &its_sgi_domain_ops;
		else
			sgi_ops = NULL;

5697
		if (its_init_vpe_domain() ||
5698
		    its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5699 5700 5701 5702 5703
			rdists->has_vlpis = false;
			pr_err("ITS: Disabling GICv4 support\n");
		}
	}

5704 5705
	register_syscore_ops(&its_syscore_ops);

5706
	return 0;
5707
}