ohci.c 106 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
 * Driver for OHCI 1394 controllers
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 *
 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
 */

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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/firewire.h>
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#include <linux/firewire-constants.h>
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#include <linux/init.h>
#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/time.h>
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#include <linux/vmalloc.h>
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#include <linux/workqueue.h>
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#include <asm/byteorder.h>
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#include <asm/page.h>
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#ifdef CONFIG_PPC_PMAC
#include <asm/pmac_feature.h>
#endif

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#include "core.h"
#include "ohci.h"
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#include "packet-header-definitions.h"
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#define ohci_info(ohci, f, args...)	dev_info(ohci->card.device, f, ##args)
#define ohci_notice(ohci, f, args...)	dev_notice(ohci->card.device, f, ##args)
#define ohci_err(ohci, f, args...)	dev_err(ohci->card.device, f, ##args)

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#define DESCRIPTOR_OUTPUT_MORE		0
#define DESCRIPTOR_OUTPUT_LAST		(1 << 12)
#define DESCRIPTOR_INPUT_MORE		(2 << 12)
#define DESCRIPTOR_INPUT_LAST		(3 << 12)
#define DESCRIPTOR_STATUS		(1 << 11)
#define DESCRIPTOR_KEY_IMMEDIATE	(2 << 8)
#define DESCRIPTOR_PING			(1 << 7)
#define DESCRIPTOR_YY			(1 << 6)
#define DESCRIPTOR_NO_IRQ		(0 << 4)
#define DESCRIPTOR_IRQ_ERROR		(1 << 4)
#define DESCRIPTOR_IRQ_ALWAYS		(3 << 4)
#define DESCRIPTOR_BRANCH_ALWAYS	(3 << 2)
#define DESCRIPTOR_WAIT			(3 << 0)
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#define DESCRIPTOR_CMD			(0xf << 12)

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struct descriptor {
	__le16 req_count;
	__le16 control;
	__le32 data_address;
	__le32 branch_address;
	__le16 res_count;
	__le16 transfer_status;
} __attribute__((aligned(16)));

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#define CONTROL_SET(regs)	(regs)
#define CONTROL_CLEAR(regs)	((regs) + 4)
#define COMMAND_PTR(regs)	((regs) + 12)
#define CONTEXT_MATCH(regs)	((regs) + 16)
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#define AR_BUFFER_SIZE	(32*1024)
#define AR_BUFFERS_MIN	DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
/* we need at least two pages for proper list management */
#define AR_BUFFERS	(AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)

#define MAX_ASYNC_PAYLOAD	4096
#define MAX_AR_PACKET_SIZE	(16 + MAX_ASYNC_PAYLOAD + 4)
#define AR_WRAPAROUND_PAGES	DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
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struct ar_context {
	struct fw_ohci *ohci;
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	struct page *pages[AR_BUFFERS];
	void *buffer;
	struct descriptor *descriptors;
	dma_addr_t descriptors_bus;
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	void *pointer;
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	unsigned int last_buffer_index;
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	u32 regs;
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	struct tasklet_struct tasklet;
};

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struct context;

typedef int (*descriptor_callback_t)(struct context *ctx,
				     struct descriptor *d,
				     struct descriptor *last);
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/*
 * A buffer that contains a block of DMA-able coherent memory used for
 * storing a portion of a DMA descriptor program.
 */
struct descriptor_buffer {
	struct list_head list;
	dma_addr_t buffer_bus;
	size_t buffer_size;
	size_t used;
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	struct descriptor buffer[];
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};

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struct context {
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	struct fw_ohci *ohci;
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	u32 regs;
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	int total_allocation;
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	u32 current_bus;
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	bool running;
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	bool flushing;
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	/*
	 * List of page-sized buffers for storing DMA descriptors.
	 * Head of list contains buffers in use and tail of list contains
	 * free buffers.
	 */
	struct list_head buffer_list;

	/*
	 * Pointer to a buffer inside buffer_list that contains the tail
	 * end of the current DMA program.
	 */
	struct descriptor_buffer *buffer_tail;

	/*
	 * The descriptor containing the branch address of the first
	 * descriptor that has not yet been filled by the device.
	 */
	struct descriptor *last;

	/*
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	 * The last descriptor block in the DMA program. It contains the branch
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	 * address that must be updated upon appending a new descriptor.
	 */
	struct descriptor *prev;
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	int prev_z;
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	descriptor_callback_t callback;

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	struct tasklet_struct tasklet;
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};

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#define IT_HEADER_SY(v)          ((v) <<  0)
#define IT_HEADER_TCODE(v)       ((v) <<  4)
#define IT_HEADER_CHANNEL(v)     ((v) <<  8)
#define IT_HEADER_TAG(v)         ((v) << 14)
#define IT_HEADER_SPEED(v)       ((v) << 16)
#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
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struct iso_context {
	struct fw_iso_context base;
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	struct context context;
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	void *header;
	size_t header_length;
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	unsigned long flushing_completions;
	u32 mc_buffer_bus;
	u16 mc_completed;
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	u16 last_timestamp;
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	u8 sync;
	u8 tags;
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};

#define CONFIG_ROM_SIZE 1024

struct fw_ohci {
	struct fw_card card;

	__iomem char *registers;
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	int node_id;
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	int generation;
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	int request_generation;	/* for timestamping incoming requests */
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	unsigned quirks;
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	unsigned int pri_req_max;
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	u32 bus_time;
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	bool bus_time_running;
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	bool is_root;
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	bool csr_state_setclear_abdicate;
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	int n_ir;
	int n_it;
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	/*
	 * Spinlock for accessing fw_ohci data.  Never call out of
	 * this driver with this lock held.
	 */
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	spinlock_t lock;

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	struct mutex phy_reg_mutex;

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	void *misc_buffer;
	dma_addr_t misc_buffer_bus;

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	struct ar_context ar_request_ctx;
	struct ar_context ar_response_ctx;
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	struct context at_request_ctx;
	struct context at_response_ctx;
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	u32 it_context_support;
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	u32 it_context_mask;     /* unoccupied IT contexts */
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	struct iso_context *it_context_list;
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	u64 ir_context_channels; /* unoccupied channels */
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	u32 ir_context_support;
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	u32 ir_context_mask;     /* unoccupied IR contexts */
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	struct iso_context *ir_context_list;
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	u64 mc_channels; /* channels in use by the multichannel IR context */
	bool mc_allocated;
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	__be32    *config_rom;
	dma_addr_t config_rom_bus;
	__be32    *next_config_rom;
	dma_addr_t next_config_rom_bus;
	__be32     next_header;

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	__le32    *self_id;
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	dma_addr_t self_id_bus;
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	struct work_struct bus_reset_work;
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	u32 self_id_buffer[512];
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};

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static struct workqueue_struct *selfid_workqueue;

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static inline struct fw_ohci *fw_ohci(struct fw_card *card)
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{
	return container_of(card, struct fw_ohci, card);
}

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#define IT_CONTEXT_CYCLE_MATCH_ENABLE	0x80000000
#define IR_CONTEXT_BUFFER_FILL		0x80000000
#define IR_CONTEXT_ISOCH_HEADER		0x40000000
#define IR_CONTEXT_CYCLE_MATCH_ENABLE	0x20000000
#define IR_CONTEXT_MULTI_CHANNEL_MODE	0x10000000
#define IR_CONTEXT_DUAL_BUFFER_MODE	0x08000000
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#define CONTEXT_RUN	0x8000
#define CONTEXT_WAKE	0x1000
#define CONTEXT_DEAD	0x0800
#define CONTEXT_ACTIVE	0x0400

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#define OHCI1394_MAX_AT_REQ_RETRIES	0xf
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#define OHCI1394_MAX_AT_RESP_RETRIES	0x2
#define OHCI1394_MAX_PHYS_RESP_RETRIES	0x8

#define OHCI1394_REGISTER_SIZE		0x800
#define OHCI1394_PCI_HCI_Control	0x40
#define SELF_ID_BUF_SIZE		0x800
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#define OHCI_TCODE_PHY_PACKET		0x0e
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#define OHCI_VERSION_1_1		0x010010
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static char ohci_driver_name[] = KBUILD_MODNAME;

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#define PCI_VENDOR_ID_PINNACLE_SYSTEMS	0x11bd
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#define PCI_DEVICE_ID_AGERE_FW643	0x5901
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#define PCI_DEVICE_ID_CREATIVE_SB1394	0x4001
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#define PCI_DEVICE_ID_JMICRON_JMB38X_FW	0x2380
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#define PCI_DEVICE_ID_TI_TSB12LV22	0x8009
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#define PCI_DEVICE_ID_TI_TSB12LV26	0x8020
#define PCI_DEVICE_ID_TI_TSB82AA2	0x8025
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#define PCI_DEVICE_ID_VIA_VT630X	0x3044
#define PCI_REV_ID_VIA_VT6306		0x46
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#define PCI_DEVICE_ID_VIA_VT6315	0x3403
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#define QUIRK_CYCLE_TIMER		0x1
#define QUIRK_RESET_PACKET		0x2
#define QUIRK_BE_HEADERS		0x4
#define QUIRK_NO_1394A			0x8
#define QUIRK_NO_MSI			0x10
#define QUIRK_TI_SLLZ059		0x20
#define QUIRK_IR_WAKE			0x40
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// On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia
// ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register
// (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not
// clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register,
// while it is probable due to detection of any type of PCIe error.
#define QUIRK_REBOOT_BY_CYCLE_TIMER_READ	0x80000000

#if IS_ENABLED(CONFIG_X86)

static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci)
{
	return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ);
}

#define PCI_DEVICE_ID_ASMEDIA_ASM108X	0x1080

static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev)
{
	const struct pci_dev *pcie_to_pci_bridge;

	// Detect any type of AMD Ryzen machine.
	if (!static_cpu_has(X86_FEATURE_ZEN))
		return false;

	// Detect VIA VT6306/6307/6308.
	if (pdev->vendor != PCI_VENDOR_ID_VIA)
		return false;
	if (pdev->device != PCI_DEVICE_ID_VIA_VT630X)
		return false;

	// Detect Asmedia ASM1083/1085.
	pcie_to_pci_bridge = pdev->bus->self;
	if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA)
		return false;
	if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X)
		return false;

	return true;
}

#else
#define has_reboot_by_cycle_timer_read_quirk(ohci) false
#define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev)	false
#endif

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/* In case of multiple matches in ohci_quirks[], only the first one is used. */
static const struct {
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	unsigned short vendor, device, revision, flags;
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} ohci_quirks[] = {
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	{PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER},

	{PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
		QUIRK_BE_HEADERS},

	{PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
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		QUIRK_NO_MSI},
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	{PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
		QUIRK_RESET_PACKET},

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	{PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
		QUIRK_NO_MSI},

	{PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER},

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	{PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_NO_MSI},

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	{PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
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		QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
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	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},

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	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
		QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},

	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
		QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},

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	{PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_RESET_PACKET},

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	{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
		QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},

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	{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
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		QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
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	{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
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		QUIRK_NO_MSI},
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	{PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
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};

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/* This overrides anything that was found in ohci_quirks[]. */
static int param_quirks;
module_param_named(quirks, param_quirks, int, 0644);
MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
	", nonatomic cycle timer = "	__stringify(QUIRK_CYCLE_TIMER)
	", reset packet generation = "	__stringify(QUIRK_RESET_PACKET)
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	", AR/selfID endianness = "	__stringify(QUIRK_BE_HEADERS)
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	", no 1394a enhancements = "	__stringify(QUIRK_NO_1394A)
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	", disable MSI = "		__stringify(QUIRK_NO_MSI)
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	", TI SLLZ059 erratum = "	__stringify(QUIRK_TI_SLLZ059)
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	", IR wake unreliable = "	__stringify(QUIRK_IR_WAKE)
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	")");

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#define OHCI_PARAM_DEBUG_AT_AR		1
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#define OHCI_PARAM_DEBUG_SELFIDS	2
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#define OHCI_PARAM_DEBUG_IRQS		4
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static int param_debug;
module_param_named(debug, param_debug, int, 0644);
MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
	", AT/AR events = "	__stringify(OHCI_PARAM_DEBUG_AT_AR)
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	", self-IDs = "		__stringify(OHCI_PARAM_DEBUG_SELFIDS)
	", IRQs = "		__stringify(OHCI_PARAM_DEBUG_IRQS)
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	", or a combination, or all = -1)");

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static bool param_remote_dma;
module_param_named(remote_dma, param_remote_dma, bool, 0444);
MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");

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static void log_irqs(struct fw_ohci *ohci, u32 evt)
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{
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	if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS)))
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		return;

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	ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
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	    evt & OHCI1394_selfIDComplete	? " selfID"		: "",
	    evt & OHCI1394_RQPkt		? " AR_req"		: "",
	    evt & OHCI1394_RSPkt		? " AR_resp"		: "",
	    evt & OHCI1394_reqTxComplete	? " AT_req"		: "",
	    evt & OHCI1394_respTxComplete	? " AT_resp"		: "",
	    evt & OHCI1394_isochRx		? " IR"			: "",
	    evt & OHCI1394_isochTx		? " IT"			: "",
	    evt & OHCI1394_postedWriteErr	? " postedWriteErr"	: "",
	    evt & OHCI1394_cycleTooLong		? " cycleTooLong"	: "",
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	    evt & OHCI1394_cycle64Seconds	? " cycle64Seconds"	: "",
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	    evt & OHCI1394_cycleInconsistent	? " cycleInconsistent"	: "",
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	    evt & OHCI1394_regAccessFail	? " regAccessFail"	: "",
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	    evt & OHCI1394_unrecoverableError	? " unrecoverableError"	: "",
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	    evt & OHCI1394_busReset		? " busReset"		: "",
	    evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
		    OHCI1394_RSPkt | OHCI1394_reqTxComplete |
		    OHCI1394_respTxComplete | OHCI1394_isochRx |
		    OHCI1394_isochTx | OHCI1394_postedWriteErr |
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		    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
		    OHCI1394_cycleInconsistent |
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		    OHCI1394_regAccessFail | OHCI1394_busReset)
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						? " ?"			: "");
}

static const char *speed[] = {
	[0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
};
static const char *power[] = {
	[0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
	[4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
};
static const char port[] = { '.', '-', 'p', 'c', };

static char _p(u32 *s, int shift)
{
	return port[*s >> shift & 3];
}

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static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
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{
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	u32 *s;

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	if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
		return;

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	ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
		    self_id_count, generation, ohci->node_id);
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	for (s = ohci->self_id_buffer; self_id_count--; ++s)
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		if ((*s & 1 << 23) == 0)
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			ohci_notice(ohci,
			    "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
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			    *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
			    speed[*s >> 14 & 3], *s >> 16 & 63,
			    power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
			    *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
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		else
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			ohci_notice(ohci,
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			    "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
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			    *s, *s >> 24 & 63,
			    _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
			    _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
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}

static const char *evts[] = {
	[0x00] = "evt_no_status",	[0x01] = "-reserved-",
	[0x02] = "evt_long_packet",	[0x03] = "evt_missing_ack",
	[0x04] = "evt_underrun",	[0x05] = "evt_overrun",
	[0x06] = "evt_descriptor_read",	[0x07] = "evt_data_read",
	[0x08] = "evt_data_write",	[0x09] = "evt_bus_reset",
	[0x0a] = "evt_timeout",		[0x0b] = "evt_tcode_err",
	[0x0c] = "-reserved-",		[0x0d] = "-reserved-",
	[0x0e] = "evt_unknown",		[0x0f] = "evt_flushed",
	[0x10] = "-reserved-",		[0x11] = "ack_complete",
	[0x12] = "ack_pending ",	[0x13] = "-reserved-",
	[0x14] = "ack_busy_X",		[0x15] = "ack_busy_A",
	[0x16] = "ack_busy_B",		[0x17] = "-reserved-",
	[0x18] = "-reserved-",		[0x19] = "-reserved-",
	[0x1a] = "-reserved-",		[0x1b] = "ack_tardy",
	[0x1c] = "-reserved-",		[0x1d] = "ack_data_error",
	[0x1e] = "ack_type_error",	[0x1f] = "-reserved-",
	[0x20] = "pending/cancelled",
};
static const char *tcodes[] = {
	[0x0] = "QW req",		[0x1] = "BW req",
	[0x2] = "W resp",		[0x3] = "-reserved-",
	[0x4] = "QR req",		[0x5] = "BR req",
	[0x6] = "QR resp",		[0x7] = "BR resp",
	[0x8] = "cycle start",		[0x9] = "Lk req",
	[0xa] = "async stream packet",	[0xb] = "Lk resp",
	[0xc] = "-reserved-",		[0xd] = "-reserved-",
	[0xe] = "link internal",	[0xf] = "-reserved-",
};

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static void log_ar_at_event(struct fw_ohci *ohci,
			    char dir, int speed, u32 *header, int evt)
512
{
513
	int tcode = async_header_get_tcode(header);
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	char specific[12];

	if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
		return;

	if (unlikely(evt >= ARRAY_SIZE(evts)))
520
		evt = 0x1f;
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522
	if (evt == OHCI1394_evt_bus_reset) {
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		ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
			    dir, (header[2] >> 16) & 0xff);
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		return;
	}

528
	switch (tcode) {
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	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_READ_QUADLET_RESPONSE:
	case TCODE_CYCLE_START:
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		snprintf(specific, sizeof(specific), " = %08x",
			 be32_to_cpu((__force __be32)header[3]));
		break;
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	case TCODE_WRITE_BLOCK_REQUEST:
	case TCODE_READ_BLOCK_REQUEST:
	case TCODE_READ_BLOCK_RESPONSE:
	case TCODE_LOCK_REQUEST:
	case TCODE_LOCK_RESPONSE:
540
		snprintf(specific, sizeof(specific), " %x,%x",
541 542
			 async_header_get_data_length(header),
			 async_header_get_extended_tcode(header));
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		break;
	default:
		specific[0] = '\0';
	}

	switch (tcode) {
549
	case TCODE_STREAM_DATA:
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		ohci_notice(ohci, "A%c %s, %s\n",
			    dir, evts[evt], tcodes[tcode]);
552
		break;
553
	case 0xe:
554 555
		ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
			    dir, evts[evt], header[1], header[2]);
556
		break;
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	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_WRITE_BLOCK_REQUEST:
	case TCODE_READ_QUADLET_REQUEST:
	case TCODE_READ_BLOCK_REQUEST:
	case TCODE_LOCK_REQUEST:
562
		ohci_notice(ohci,
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			    "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n",
			    dir, speed, async_header_get_tlabel(header),
			    async_header_get_source(header), async_header_get_destination(header),
			    evts[evt], tcodes[tcode], async_header_get_offset(header), specific);
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		break;
	default:
569 570
		ohci_notice(ohci,
			    "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
571 572 573
			    dir, speed, async_header_get_tlabel(header),
			    async_header_get_source(header), async_header_get_destination(header),
			    evts[evt], tcodes[tcode], specific);
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	}
}

Adrian Bunk's avatar
Adrian Bunk committed
577
static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
578 579 580 581
{
	writel(data, ohci->registers + offset);
}

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Adrian Bunk committed
582
static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
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{
	return readl(ohci->registers + offset);
}

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Adrian Bunk committed
587
static inline void flush_writes(const struct fw_ohci *ohci)
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{
	/* Do a dummy read to flush writes. */
	reg_read(ohci, OHCI1394_Version);
}

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/*
 * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 */
599
static int read_phy_reg(struct fw_ohci *ohci, int addr)
600
{
601
	u32 val;
602
	int i;
603 604

	reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
605
	for (i = 0; i < 3 + 100; i++) {
606
		val = reg_read(ohci, OHCI1394_PhyControl);
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		if (!~val)
			return -ENODEV; /* Card was ejected. */

610 611 612
		if (val & OHCI1394_PhyControl_ReadDone)
			return OHCI1394_PhyControl_ReadData(val);

613 614 615 616 617 618
		/*
		 * Try a few times without waiting.  Sleeping is necessary
		 * only when the link/PHY interface is busy.
		 */
		if (i >= 3)
			msleep(1);
619
	}
620 621
	ohci_err(ohci, "failed to read phy reg %d\n", addr);
	dump_stack();
622

623 624
	return -EBUSY;
}
625

626 627 628
static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
{
	int i;
629 630

	reg_write(ohci, OHCI1394_PhyControl,
631
		  OHCI1394_PhyControl_Write(addr, val));
632
	for (i = 0; i < 3 + 100; i++) {
633
		val = reg_read(ohci, OHCI1394_PhyControl);
634 635 636
		if (!~val)
			return -ENODEV; /* Card was ejected. */

637 638
		if (!(val & OHCI1394_PhyControl_WritePending))
			return 0;
639

640 641
		if (i >= 3)
			msleep(1);
642
	}
643 644
	ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
	dump_stack();
645 646

	return -EBUSY;
647 648
}

649 650
static int update_phy_reg(struct fw_ohci *ohci, int addr,
			  int clear_bits, int set_bits)
651
{
652
	int ret = read_phy_reg(ohci, addr);
653 654
	if (ret < 0)
		return ret;
655

656 657 658 659 660 661 662
	/*
	 * The interrupt status bits are cleared by writing a one bit.
	 * Avoid clearing them unless explicitly requested in set_bits.
	 */
	if (addr == 5)
		clear_bits |= PHY_INT_STATUS_BITS;

663
	return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
664 665
}

666
static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
667
{
668
	int ret;
669

670
	ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
671 672
	if (ret < 0)
		return ret;
673

674
	return read_phy_reg(ohci, addr);
675 676
}

677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699
static int ohci_read_phy_reg(struct fw_card *card, int addr)
{
	struct fw_ohci *ohci = fw_ohci(card);
	int ret;

	mutex_lock(&ohci->phy_reg_mutex);
	ret = read_phy_reg(ohci, addr);
	mutex_unlock(&ohci->phy_reg_mutex);

	return ret;
}

static int ohci_update_phy_reg(struct fw_card *card, int addr,
			       int clear_bits, int set_bits)
{
	struct fw_ohci *ohci = fw_ohci(card);
	int ret;

	mutex_lock(&ohci->phy_reg_mutex);
	ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
	mutex_unlock(&ohci->phy_reg_mutex);

	return ret;
700 701
}

702 703 704 705 706 707
static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
{
	return page_private(ctx->pages[i]);
}

static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
708
{
709
	struct descriptor *d;
710

711 712 713 714
	d = &ctx->descriptors[index];
	d->branch_address  &= cpu_to_le32(~0xf);
	d->res_count       =  cpu_to_le16(PAGE_SIZE);
	d->transfer_status =  0;
715

716
	wmb(); /* finish init of new descriptors before branch_address update */
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	d = &ctx->descriptors[ctx->last_buffer_index];
	d->branch_address  |= cpu_to_le32(1);

	ctx->last_buffer_index = index;
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722
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
723 724
}

725
static void ar_context_release(struct ar_context *ctx)
726
{
727
	struct device *dev = ctx->ohci->card.device;
728
	unsigned int i;
729

730 731 732
	if (!ctx->buffer)
		return;

733
	vunmap(ctx->buffer);
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735 736 737 738 739
	for (i = 0; i < AR_BUFFERS; i++) {
		if (ctx->pages[i])
			dma_free_pages(dev, PAGE_SIZE, ctx->pages[i],
				       ar_buffer_bus(ctx, i), DMA_FROM_DEVICE);
	}
740 741
}

742
static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
743
{
744
	struct fw_ohci *ohci = ctx->ohci;
745

746 747 748
	if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
		reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
		flush_writes(ohci);
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750
		ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
751
	}
752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
	/* FIXME: restart? */
}

static inline unsigned int ar_next_buffer_index(unsigned int index)
{
	return (index + 1) % AR_BUFFERS;
}

static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
{
	return ar_next_buffer_index(ctx->last_buffer_index);
}

/*
 * We search for the buffer that contains the last AR packet DMA data written
 * by the controller.
 */
static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
						 unsigned int *buffer_offset)
{
	unsigned int i, next_i, last = ctx->last_buffer_index;
	__le16 res_count, next_res_count;

	i = ar_first_buffer_index(ctx);
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	res_count = READ_ONCE(ctx->descriptors[i].res_count);
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	/* A buffer that is not yet completely filled must be the last one. */
	while (i != last && res_count == 0) {

		/* Peek at the next descriptor. */
		next_i = ar_next_buffer_index(i);
		rmb(); /* read descriptors in order */
784
		next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
		/*
		 * If the next descriptor is still empty, we must stop at this
		 * descriptor.
		 */
		if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
			/*
			 * The exception is when the DMA data for one packet is
			 * split over three buffers; in this case, the middle
			 * buffer's descriptor might be never updated by the
			 * controller and look still empty, and we have to peek
			 * at the third one.
			 */
			if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
				next_i = ar_next_buffer_index(next_i);
				rmb();
800
				next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
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				if (next_res_count != cpu_to_le16(PAGE_SIZE))
					goto next_buffer_is_active;
			}

			break;
		}

next_buffer_is_active:
		i = next_i;
		res_count = next_res_count;
	}

	rmb(); /* read res_count before the DMA data */

	*buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
	if (*buffer_offset > PAGE_SIZE) {
		*buffer_offset = 0;
		ar_context_abort(ctx, "corrupted descriptor");
	}

	return i;
}

static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
				    unsigned int end_buffer_index,
				    unsigned int end_buffer_offset)
{
	unsigned int i;

	i = ar_first_buffer_index(ctx);
	while (i != end_buffer_index) {
		dma_sync_single_for_cpu(ctx->ohci->card.device,
					ar_buffer_bus(ctx, i),
					PAGE_SIZE, DMA_FROM_DEVICE);
		i = ar_next_buffer_index(i);
	}
	if (end_buffer_offset > 0)
		dma_sync_single_for_cpu(ctx->ohci->card.device,
					ar_buffer_bus(ctx, i),
					end_buffer_offset, DMA_FROM_DEVICE);
841 842
}

843 844
#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
#define cond_le32_to_cpu(v) \
845
	(ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
846 847 848 849
#else
#define cond_le32_to_cpu(v) le32_to_cpu(v)
#endif

850
static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
851 852
{
	struct fw_ohci *ohci = ctx->ohci;
853 854
	struct fw_packet p;
	u32 status, length, tcode;
855
	int evt;
856

857 858 859
	p.header[0] = cond_le32_to_cpu(buffer[0]);
	p.header[1] = cond_le32_to_cpu(buffer[1]);
	p.header[2] = cond_le32_to_cpu(buffer[2]);
860

861
	tcode = async_header_get_tcode(p.header);
862 863 864
	switch (tcode) {
	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_READ_QUADLET_RESPONSE:
865
		p.header[3] = (__force __u32) buffer[3];
866
		p.header_length = 16;
867
		p.payload_length = 0;
868 869 870
		break;

	case TCODE_READ_BLOCK_REQUEST :
871
		p.header[3] = cond_le32_to_cpu(buffer[3]);
872 873 874 875 876
		p.header_length = 16;
		p.payload_length = 0;
		break;

	case TCODE_WRITE_BLOCK_REQUEST:
877 878 879
	case TCODE_READ_BLOCK_RESPONSE:
	case TCODE_LOCK_REQUEST:
	case TCODE_LOCK_RESPONSE:
880
		p.header[3] = cond_le32_to_cpu(buffer[3]);
881
		p.header_length = 16;
882
		p.payload_length = async_header_get_data_length(p.header);
883 884 885 886
		if (p.payload_length > MAX_ASYNC_PAYLOAD) {
			ar_context_abort(ctx, "invalid packet length");
			return NULL;
		}
887 888 889 890
		break;

	case TCODE_WRITE_RESPONSE:
	case TCODE_READ_QUADLET_REQUEST:
891
	case OHCI_TCODE_PHY_PACKET:
892
		p.header_length = 12;
893
		p.payload_length = 0;
894
		break;
895 896

	default:
897 898
		ar_context_abort(ctx, "invalid tcode");
		return NULL;
899
	}
900

901 902 903 904
	p.payload = (void *) buffer + p.header_length;

	/* FIXME: What to do about evt_* errors? */
	length = (p.header_length + p.payload_length + 3) / 4;
905
	status = cond_le32_to_cpu(buffer[length]);
906
	evt    = (status >> 16) & 0x1f;
907

908
	p.ack        = evt - 16;
909 910 911
	p.speed      = (status >> 21) & 0x7;
	p.timestamp  = status & 0xffff;
	p.generation = ohci->request_generation;
912

913
	log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
914

915
	/*
916 917 918
	 * Several controllers, notably from NEC and VIA, forget to
	 * write ack_complete status at PHY packet reception.
	 */
919
	if (evt == OHCI1394_evt_no_status && tcode == OHCI1394_phy_tcode)
920 921 922 923
		p.ack = ACK_COMPLETE;

	/*
	 * The OHCI bus reset handler synthesizes a PHY packet with
924 925 926 927 928
	 * the new generation number when a bus reset happens (see
	 * section 8.4.2.3).  This helps us determine when a request
	 * was received and make sure we send the response in the same
	 * generation.  We only need this for requests; for responses
	 * we use the unique tlabel for finding the matching
929
	 * request.
930 931 932
	 *
	 * Alas some chips sometimes emit bus reset packets with a
	 * wrong generation.  We set the correct generation for these
933
	 * at a slightly incorrect time (in bus_reset_work).
934
	 */
935
	if (evt == OHCI1394_evt_bus_reset) {
936
		if (!(ohci->quirks & QUIRK_RESET_PACKET))
937 938
			ohci->request_generation = (p.header[2] >> 16) & 0xff;
	} else if (ctx == &ohci->ar_request_ctx) {
939
		fw_core_handle_request(&ohci->card, &p);
940
	} else {
941
		fw_core_handle_response(&ohci->card, &p);
942
	}
943

944 945
	return buffer + length + 1;
}
946

947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974
static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
{
	void *next;

	while (p < end) {
		next = handle_ar_packet(ctx, p);
		if (!next)
			return p;
		p = next;
	}

	return p;
}

static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
{
	unsigned int i;

	i = ar_first_buffer_index(ctx);
	while (i != end_buffer) {
		dma_sync_single_for_device(ctx->ohci->card.device,
					   ar_buffer_bus(ctx, i),
					   PAGE_SIZE, DMA_FROM_DEVICE);
		ar_context_link_page(ctx, i);
		i = ar_next_buffer_index(i);
	}
}

975 976 977
static void ar_context_tasklet(unsigned long data)
{
	struct ar_context *ctx = (struct ar_context *)data;
978 979
	unsigned int end_buffer_index, end_buffer_offset;
	void *p, *end;
980

981 982 983
	p = ctx->pointer;
	if (!p)
		return;
984

985 986 987 988
	end_buffer_index = ar_search_last_active_buffer(ctx,
							&end_buffer_offset);
	ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
	end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
989

990
	if (end_buffer_index < ar_first_buffer_index(ctx)) {
991
		/*
992 993 994 995
		 * The filled part of the overall buffer wraps around; handle
		 * all packets up to the buffer end here.  If the last packet
		 * wraps around, its tail will be visible after the buffer end
		 * because the buffer start pages are mapped there again.
996
		 */
997 998 999 1000 1001 1002 1003
		void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
		p = handle_ar_packets(ctx, p, buffer_end);
		if (p < buffer_end)
			goto error;
		/* adjust p to point back into the actual buffer */
		p -= AR_BUFFERS * PAGE_SIZE;
	}
1004

1005 1006 1007 1008 1009 1010
	p = handle_ar_packets(ctx, p, end);
	if (p != end) {
		if (p > end)
			ar_context_abort(ctx, "inconsistent descriptor");
		goto error;
	}
1011

1012 1013
	ctx->pointer = p;
	ar_recycle_buffers(ctx, end_buffer_index);
1014

1015
	return;
1016

1017 1018
error:
	ctx->pointer = NULL;
1019 1020
}

1021 1022
static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
			   unsigned int descriptors_offset, u32 regs)
1023
{
1024
	struct device *dev = ohci->card.device;
1025 1026 1027 1028
	unsigned int i;
	dma_addr_t dma_addr;
	struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
	struct descriptor *d;
1029

1030 1031
	ctx->regs        = regs;
	ctx->ohci        = ohci;
1032 1033
	tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);

1034
	for (i = 0; i < AR_BUFFERS; i++) {
1035 1036
		ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr,
						DMA_FROM_DEVICE, GFP_KERNEL);
1037 1038 1039
		if (!ctx->pages[i])
			goto out_of_memory;
		set_page_private(ctx->pages[i], dma_addr);
1040 1041
		dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE,
					   DMA_FROM_DEVICE);
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	}

	for (i = 0; i < AR_BUFFERS; i++)
		pages[i]              = ctx->pages[i];
	for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
		pages[AR_BUFFERS + i] = ctx->pages[i];
1048
	ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1049 1050 1051
	if (!ctx->buffer)
		goto out_of_memory;

1052 1053
	ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
	ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064

	for (i = 0; i < AR_BUFFERS; i++) {
		d = &ctx->descriptors[i];
		d->req_count      = cpu_to_le16(PAGE_SIZE);
		d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
						DESCRIPTOR_STATUS |
						DESCRIPTOR_BRANCH_ALWAYS);
		d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
		d->branch_address = cpu_to_le32(ctx->descriptors_bus +
			ar_next_buffer_index(i) * sizeof(struct descriptor));
	}
1065

1066
	return 0;
1067 1068 1069 1070 1071

out_of_memory:
	ar_context_release(ctx);

	return -ENOMEM;
1072 1073 1074 1075
}

static void ar_context_run(struct ar_context *ctx)
{
1076 1077 1078 1079
	unsigned int i;

	for (i = 0; i < AR_BUFFERS; i++)
		ar_context_link_page(ctx, i);
1080

1081
	ctx->pointer = ctx->buffer;
1082

1083
	reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1084
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1085
}
Stefan Richter's avatar
Stefan Richter committed
1086

1087
static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1088
{
1089
	__le16 branch;
1090

1091
	branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1092 1093

	/* figure out which descriptor the branch address goes in */
1094
	if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1095 1096 1097 1098 1099
		return d;
	else
		return d + z - 1;
}

1100 1101 1102 1103 1104 1105
static void context_tasklet(unsigned long data)
{
	struct context *ctx = (struct context *) data;
	struct descriptor *d, *last;
	u32 address;
	int z;
1106
	struct descriptor_buffer *desc;
1107

1108 1109 1110
	desc = list_entry(ctx->buffer_list.next,
			struct descriptor_buffer, list);
	last = ctx->last;
1111
	while (last->branch_address != 0) {
1112
		struct descriptor_buffer *old_desc = desc;
1113 1114
		address = le32_to_cpu(last->branch_address);
		z = address & 0xf;
1115
		address &= ~0xf;
1116
		ctx->current_bus = address;
1117 1118 1119 1120 1121 1122 1123 1124

		/* If the branch address points to a buffer outside of the
		 * current buffer, advance to the next buffer. */
		if (address < desc->buffer_bus ||
				address >= desc->buffer_bus + desc->used)
			desc = list_entry(desc->list.next,
					struct descriptor_buffer, list);
		d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1125
		last = find_branch_descriptor(d, z);
1126 1127 1128 1129

		if (!ctx->callback(ctx, d, last))
			break;

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
		if (old_desc != desc) {
			/* If we've advanced to the next buffer, move the
			 * previous buffer to the free list. */
			unsigned long flags;
			old_desc->used = 0;
			spin_lock_irqsave(&ctx->ohci->lock, flags);
			list_move_tail(&old_desc->list, &ctx->buffer_list);
			spin_unlock_irqrestore(&ctx->ohci->lock, flags);
		}
		ctx->last = last;
1140 1141 1142
	}
}

1143 1144 1145 1146
/*
 * Allocate a new buffer and add it to the list of free buffers for this
 * context.  Must be called with ohci->lock held.
 */
1147
static int context_add_buffer(struct context *ctx)
1148 1149
{
	struct descriptor_buffer *desc;
1150
	dma_addr_t bus_addr;
1151 1152 1153 1154 1155 1156 1157 1158 1159
	int offset;

	/*
	 * 16MB of descriptors should be far more than enough for any DMA
	 * program.  This will catch run-away userspace or DoS attacks.
	 */
	if (ctx->total_allocation >= 16*1024*1024)
		return -ENOMEM;

1160
	desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC);
1161 1162 1163 1164
	if (!desc)
		return -ENOMEM;

	offset = (void *)&desc->buffer - (void *)desc;
1165 1166 1167 1168 1169 1170 1171
	/*
	 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
	 * for descriptors, even 0x10-byte ones. This can cause page faults when
	 * an IOMMU is in use and the oversized read crosses a page boundary.
	 * Work around this by always leaving at least 0x10 bytes of padding.
	 */
	desc->buffer_size = PAGE_SIZE - offset - 0x10;
1172 1173 1174 1175 1176 1177 1178 1179 1180
	desc->buffer_bus = bus_addr + offset;
	desc->used = 0;

	list_add_tail(&desc->list, &ctx->buffer_list);
	ctx->total_allocation += PAGE_SIZE;

	return 0;
}

1181 1182
static int context_init(struct context *ctx, struct fw_ohci *ohci,
			u32 regs, descriptor_callback_t callback)
1183 1184 1185
{
	ctx->ohci = ohci;
	ctx->regs = regs;
1186 1187 1188 1189
	ctx->total_allocation = 0;

	INIT_LIST_HEAD(&ctx->buffer_list);
	if (context_add_buffer(ctx) < 0)
1190 1191
		return -ENOMEM;

1192 1193 1194
	ctx->buffer_tail = list_entry(ctx->buffer_list.next,
			struct descriptor_buffer, list);

1195 1196 1197
	tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
	ctx->callback = callback;

1198 1199
	/*
	 * We put a dummy descriptor in the buffer that has a NULL
1200
	 * branch address and looks like it's been sent.  That way we
1201
	 * have a descriptor to append DMA programs to.
1202
	 */
1203 1204 1205 1206 1207 1208
	memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
	ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
	ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
	ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
	ctx->last = ctx->buffer_tail->buffer;
	ctx->prev = ctx->buffer_tail->buffer;
1209
	ctx->prev_z = 1;
1210 1211 1212 1213

	return 0;
}

1214
static void context_release(struct context *ctx)
1215 1216
{
	struct fw_card *card = &ctx->ohci->card;
1217
	struct descriptor_buffer *desc, *tmp;
1218

1219 1220 1221 1222
	list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) {
		dmam_free_coherent(card->device, PAGE_SIZE, desc,
				   desc->buffer_bus - ((void *)&desc->buffer - (void *)desc));
	}
1223 1224
}

1225
/* Must be called with ohci->lock held */
1226 1227
static struct descriptor *context_get_descriptors(struct context *ctx,
						  int z, dma_addr_t *d_bus)
1228
{
1229 1230 1231 1232 1233 1234 1235 1236 1237
	struct descriptor *d = NULL;
	struct descriptor_buffer *desc = ctx->buffer_tail;

	if (z * sizeof(*d) > desc->buffer_size)
		return NULL;

	if (z * sizeof(*d) > desc->buffer_size - desc->used) {
		/* No room for the descriptor in this buffer, so advance to the
		 * next one. */
1238

1239 1240 1241 1242 1243 1244 1245 1246 1247 1248
		if (desc->list.next == &ctx->buffer_list) {
			/* If there is no free buffer next in the list,
			 * allocate one. */
			if (context_add_buffer(ctx) < 0)
				return NULL;
		}
		desc = list_entry(desc->list.next,
				struct descriptor_buffer, list);
		ctx->buffer_tail = desc;
	}
1249

1250
	d = desc->buffer + desc->used / sizeof(*d);
1251
	memset(d, 0, z * sizeof(*d));
1252
	*d_bus = desc->buffer_bus + desc->used;
1253 1254 1255 1256

	return d;
}

1257
static void context_run(struct context *ctx, u32 extra)
1258 1259 1260
{
	struct fw_ohci *ohci = ctx->ohci;

1261
	reg_write(ohci, COMMAND_PTR(ctx->regs),
1262
		  le32_to_cpu(ctx->last->branch_address));
1263 1264
	reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
	reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1265
	ctx->running = true;
1266 1267 1268 1269 1270 1271 1272
	flush_writes(ohci);
}

static void context_append(struct context *ctx,
			   struct descriptor *d, int z, int extra)
{
	dma_addr_t d_bus;
1273
	struct descriptor_buffer *desc = ctx->buffer_tail;
1274
	struct descriptor *d_branch;
1275

1276
	d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1277

1278
	desc->used += (z + extra) * sizeof(*d);
1279 1280

	wmb(); /* finish init of new descriptors before branch_address update */
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302

	d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
	d_branch->branch_address = cpu_to_le32(d_bus | z);

	/*
	 * VT6306 incorrectly checks only the single descriptor at the
	 * CommandPtr when the wake bit is written, so if it's a
	 * multi-descriptor block starting with an INPUT_MORE, put a copy of
	 * the branch address in the first descriptor.
	 *
	 * Not doing this for transmit contexts since not sure how it interacts
	 * with skip addresses.
	 */
	if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
	    d_branch != ctx->prev &&
	    (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
	     cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
		ctx->prev->branch_address = cpu_to_le32(d_bus | z);
	}

	ctx->prev = d;
	ctx->prev_z = z;
1303 1304 1305 1306
}

static void context_stop(struct context *ctx)
{
1307
	struct fw_ohci *ohci = ctx->ohci;
1308
	u32 reg;
1309
	int i;
1310

1311
	reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1312
	ctx->running = false;
1313

1314
	for (i = 0; i < 1000; i++) {
1315
		reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1316
		if ((reg & CONTEXT_ACTIVE) == 0)
1317
			return;
1318

1319 1320
		if (i)
			udelay(10);
1321
	}
1322
	ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1323
}
1324

1325
struct driver_data {
1326
	u8 inline_data[8];
1327 1328
	struct fw_packet *packet;
};
1329

1330 1331
/*
 * This function apppends a packet to the DMA queue for transmission.
1332
 * Must always be called with the ochi->lock held to ensure proper
1333 1334
 * generation handling and locking around packet queue manipulation.
 */
1335 1336
static int at_context_queue_packet(struct context *ctx,
				   struct fw_packet *packet)
1337 1338
{
	struct fw_ohci *ohci = ctx->ohci;
1339
	dma_addr_t d_bus, payload_bus;
1340 1341 1342
	struct driver_data *driver_data;
	struct descriptor *d, *last;
	__le32 *header;
1343 1344
	int z, tcode;

1345 1346 1347 1348
	d = context_get_descriptors(ctx, 4, &d_bus);
	if (d == NULL) {
		packet->ack = RCODE_SEND_ERROR;
		return -1;
1349 1350
	}

1351
	d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1352 1353
	d[0].res_count = cpu_to_le16(packet->timestamp);

1354
	/*
1355
	 * The DMA format for asynchronous link packets is different
1356
	 * from the IEEE1394 layout, so shift the fields around
1357
	 * accordingly.
1358
	 */
1359

1360
	tcode = async_header_get_tcode(packet->header);
1361
	header = (__le32 *) &d[1];
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	switch (tcode) {
	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_WRITE_BLOCK_REQUEST:
	case TCODE_WRITE_RESPONSE:
	case TCODE_READ_QUADLET_REQUEST:
	case TCODE_READ_BLOCK_REQUEST:
	case TCODE_READ_QUADLET_RESPONSE:
	case TCODE_READ_BLOCK_RESPONSE:
	case TCODE_LOCK_REQUEST:
	case TCODE_LOCK_RESPONSE:
1372 1373 1374 1375 1376
		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
					(packet->speed << 16));
		header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
					(packet->header[0] & 0xffff0000));
		header[2] = cpu_to_le32(packet->header[2]);
1377

1378
		if (tcode_is_block_packet(tcode))
1379
			header[3] = cpu_to_le32(packet->header[3]);
1380
		else
1381 1382 1383
			header[3] = (__force __le32) packet->header[3];

		d[0].req_count = cpu_to_le16(packet->header_length);
1384 1385
		break;

1386
	case TCODE_LINK_INTERNAL:
1387 1388
		header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
					(packet->speed << 16));
1389 1390
		header[1] = cpu_to_le32(packet->header[1]);
		header[2] = cpu_to_le32(packet->header[2]);
1391
		d[0].req_count = cpu_to_le16(12);
1392

1393
		if (is_ping_packet(&packet->header[1]))
1394
			d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1395 1396
		break;

1397
	case TCODE_STREAM_DATA:
1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
					(packet->speed << 16));
		header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
		d[0].req_count = cpu_to_le16(8);
		break;

	default:
		/* BUG(); */
		packet->ack = RCODE_SEND_ERROR;
		return -1;
1408 1409
	}

1410
	BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1411 1412
	driver_data = (struct driver_data *) &d[3];
	driver_data->packet = packet;
1413
	packet->driver_data = driver_data;
1414

1415
	if (packet->payload_length > 0) {
1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430
		if (packet->payload_length > sizeof(driver_data->inline_data)) {
			payload_bus = dma_map_single(ohci->card.device,
						     packet->payload,
						     packet->payload_length,
						     DMA_TO_DEVICE);
			if (dma_mapping_error(ohci->card.device, payload_bus)) {
				packet->ack = RCODE_SEND_ERROR;
				return -1;
			}
			packet->payload_bus	= payload_bus;
			packet->payload_mapped	= true;
		} else {
			memcpy(driver_data->inline_data, packet->payload,
			       packet->payload_length);
			payload_bus = d_bus + 3 * sizeof(*d);
1431 1432 1433 1434 1435 1436
		}

		d[2].req_count    = cpu_to_le16(packet->payload_length);
		d[2].data_address = cpu_to_le32(payload_bus);
		last = &d[2];
		z = 3;
1437
	} else {
1438 1439
		last = &d[0];
		z = 2;
1440 1441
	}

1442 1443 1444
	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
				     DESCRIPTOR_IRQ_ALWAYS |
				     DESCRIPTOR_BRANCH_ALWAYS);
1445

1446 1447
	/* FIXME: Document how the locking works. */
	if (ohci->generation != packet->generation) {
1448
		if (packet->payload_mapped)
1449 1450
			dma_unmap_single(ohci->card.device, payload_bus,
					 packet->payload_length, DMA_TO_DEVICE);
1451 1452 1453 1454 1455
		packet->ack = RCODE_GENERATION;
		return -1;
	}

	context_append(ctx, d, z, 4 - z);
1456

1457
	if (ctx->running)
1458
		reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1459
	else
1460 1461 1462
		context_run(ctx, 0);

	return 0;
1463 1464
}

1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475
static void at_context_flush(struct context *ctx)
{
	tasklet_disable(&ctx->tasklet);

	ctx->flushing = true;
	context_tasklet((unsigned long)ctx);
	ctx->flushing = false;

	tasklet_enable(&ctx->tasklet);
}

1476 1477 1478
static int handle_at_packet(struct context *context,
			    struct descriptor *d,
			    struct descriptor *last)
1479
{
1480
	struct driver_data *driver_data;
1481
	struct fw_packet *packet;
1482
	struct fw_ohci *ohci = context->ohci;
1483 1484
	int evt;

1485
	if (last->transfer_status == 0 && !context->flushing)
1486 1487
		/* This descriptor isn't done yet, stop iteration. */
		return 0;
1488

1489 1490 1491 1492 1493
	driver_data = (struct driver_data *) &d[3];
	packet = driver_data->packet;
	if (packet == NULL)
		/* This packet was cancelled, just continue. */
		return 1;
1494

1495
	if (packet->payload_mapped)
1496
		dma_unmap_single(ohci->card.device, packet->payload_bus,
1497 1498
				 packet->payload_length, DMA_TO_DEVICE);

1499 1500
	evt = le16_to_cpu(last->transfer_status) & 0x1f;
	packet->timestamp = le16_to_cpu(last->res_count);
1501

1502
	log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1503

1504 1505 1506 1507 1508
	switch (evt) {
	case OHCI1394_evt_timeout:
		/* Async response transmit timed out. */
		packet->ack = RCODE_CANCELLED;
		break;
1509

1510
	case OHCI1394_evt_flushed:
1511 1512 1513 1514
		/*
		 * The packet was flushed should give same error as
		 * when we try to use a stale generation count.
		 */
1515 1516
		packet->ack = RCODE_GENERATION;
		break;
1517

1518
	case OHCI1394_evt_missing_ack:
1519 1520 1521 1522 1523 1524 1525 1526 1527
		if (context->flushing)
			packet->ack = RCODE_GENERATION;
		else {
			/*
			 * Using a valid (current) generation count, but the
			 * node is not on the bus or not sending acks.
			 */
			packet->ack = RCODE_NO_ACK;
		}
1528
		break;
1529

1530 1531 1532 1533 1534 1535 1536 1537 1538
	case ACK_COMPLETE + 0x10:
	case ACK_PENDING + 0x10:
	case ACK_BUSY_X + 0x10:
	case ACK_BUSY_A + 0x10:
	case ACK_BUSY_B + 0x10:
	case ACK_DATA_ERROR + 0x10:
	case ACK_TYPE_ERROR + 0x10:
		packet->ack = evt - 0x10;
		break;
1539

1540 1541 1542 1543 1544
	case OHCI1394_evt_no_status:
		if (context->flushing) {
			packet->ack = RCODE_GENERATION;
			break;
		}
1545
		fallthrough;
1546

1547 1548 1549 1550
	default:
		packet->ack = RCODE_SEND_ERROR;
		break;
	}
1551

1552
	packet->callback(packet, &ohci->card, packet->ack);
1553

1554
	return 1;
1555 1556
}

1557 1558
static u32 get_cycle_time(struct fw_ohci *ohci);

1559 1560
static void handle_local_rom(struct fw_ohci *ohci,
			     struct fw_packet *packet, u32 csr)
1561 1562 1563 1564
{
	struct fw_packet response;
	int tcode, length, i;

1565
	tcode = async_header_get_tcode(packet->header);
1566
	if (tcode_is_block_packet(tcode))
1567
		length = async_header_get_data_length(packet->header);
1568 1569 1570 1571 1572 1573 1574
	else
		length = 4;

	i = csr - CSR_CONFIG_ROM;
	if (i + length > CONFIG_ROM_SIZE) {
		fw_fill_response(&response, packet->header,
				 RCODE_ADDRESS_ERROR, NULL, 0);
1575
	} else if (!tcode_is_read_request(tcode)) {
1576 1577 1578 1579 1580 1581 1582
		fw_fill_response(&response, packet->header,
				 RCODE_TYPE_ERROR, NULL, 0);
	} else {
		fw_fill_response(&response, packet->header, RCODE_COMPLETE,
				 (void *) ohci->config_rom + i, length);
	}

1583 1584
	// Timestamping on behalf of the hardware.
	response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci));
1585 1586 1587
	fw_core_handle_response(&ohci->card, &response);
}

1588 1589
static void handle_local_lock(struct fw_ohci *ohci,
			      struct fw_packet *packet, u32 csr)
1590 1591
{
	struct fw_packet response;
1592
	int tcode, length, ext_tcode, sel, try;
1593 1594 1595
	__be32 *payload, lock_old;
	u32 lock_arg, lock_data;

1596 1597
	tcode = async_header_get_tcode(packet->header);
	length = async_header_get_data_length(packet->header);
1598
	payload = packet->payload;
1599
	ext_tcode = async_header_get_extended_tcode(packet->header);
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618

	if (tcode == TCODE_LOCK_REQUEST &&
	    ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
		lock_arg = be32_to_cpu(payload[0]);
		lock_data = be32_to_cpu(payload[1]);
	} else if (tcode == TCODE_READ_QUADLET_REQUEST) {
		lock_arg = 0;
		lock_data = 0;
	} else {
		fw_fill_response(&response, packet->header,
				 RCODE_TYPE_ERROR, NULL, 0);
		goto out;
	}

	sel = (csr - CSR_BUS_MANAGER_ID) / 4;
	reg_write(ohci, OHCI1394_CSRData, lock_data);
	reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
	reg_write(ohci, OHCI1394_CSRControl, sel);

1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
	for (try = 0; try < 20; try++)
		if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
			lock_old = cpu_to_be32(reg_read(ohci,
							OHCI1394_CSRData));
			fw_fill_response(&response, packet->header,
					 RCODE_COMPLETE,
					 &lock_old, sizeof(lock_old));
			goto out;
		}

1629
	ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1630
	fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1631 1632

 out:
1633 1634
	// Timestamping on behalf of the hardware.
	response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci));
1635 1636 1637
	fw_core_handle_response(&ohci->card, &response);
}

1638
static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1639
{
1640
	u64 offset, csr;
1641

1642 1643 1644 1645
	if (ctx == &ctx->ohci->at_request_ctx) {
		packet->ack = ACK_PENDING;
		packet->callback(packet, &ctx->ohci->card, packet->ack);
	}
1646

1647
	offset = async_header_get_offset(packet->header);
1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
	csr = offset - CSR_REGISTER_BASE;

	/* Handle config rom reads. */
	if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
		handle_local_rom(ctx->ohci, packet, csr);
	else switch (csr) {
	case CSR_BUS_MANAGER_ID:
	case CSR_BANDWIDTH_AVAILABLE:
	case CSR_CHANNELS_AVAILABLE_HI:
	case CSR_CHANNELS_AVAILABLE_LO:
		handle_local_lock(ctx->ohci, packet, csr);
		break;
	default:
		if (ctx == &ctx->ohci->at_request_ctx)
			fw_core_handle_request(&ctx->ohci->card, packet);
		else
			fw_core_handle_response(&ctx->ohci->card, packet);
		break;
	}
1667 1668 1669 1670 1671

	if (ctx == &ctx->ohci->at_response_ctx) {
		packet->ack = ACK_COMPLETE;
		packet->callback(packet, &ctx->ohci->card, packet->ack);
	}
1672
}
1673

1674
static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1675 1676
{
	unsigned long flags;
1677
	int ret;
1678 1679 1680

	spin_lock_irqsave(&ctx->ohci->lock, flags);

1681
	if (async_header_get_destination(packet->header) == ctx->ohci->node_id &&
1682
	    ctx->ohci->generation == packet->generation) {
1683
		spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1684 1685 1686 1687

		// Timestamping on behalf of the hardware.
		packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci));

1688 1689
		handle_local_request(ctx, packet);
		return;
1690
	}
1691

1692
	ret = at_context_queue_packet(ctx, packet);
1693 1694
	spin_unlock_irqrestore(&ctx->ohci->lock, flags);

1695 1696 1697
	if (ret < 0) {
		// Timestamping on behalf of the hardware.
		packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci));
1698

1699 1700
		packet->callback(packet, &ctx->ohci->card, packet->ack);
	}
1701 1702
}

1703 1704 1705 1706 1707 1708
static void detect_dead_context(struct fw_ohci *ohci,
				const char *name, unsigned int regs)
{
	u32 ctl;

	ctl = reg_read(ohci, CONTROL_SET(regs));
1709
	if (ctl & CONTEXT_DEAD)
1710
		ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1711
			name, evts[ctl & 0x1f]);
1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737
}

static void handle_dead_contexts(struct fw_ohci *ohci)
{
	unsigned int i;
	char name[8];

	detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
	detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
	detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
	detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
	for (i = 0; i < 32; ++i) {
		if (!(ohci->it_context_support & (1 << i)))
			continue;
		sprintf(name, "IT%u", i);
		detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
	}
	for (i = 0; i < 32; ++i) {
		if (!(ohci->ir_context_support & (1 << i)))
			continue;
		sprintf(name, "IR%u", i);
		detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
	}
	/* TODO: maybe try to flush and restart the dead contexts */
}

1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770
static u32 cycle_timer_ticks(u32 cycle_timer)
{
	u32 ticks;

	ticks = cycle_timer & 0xfff;
	ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
	ticks += (3072 * 8000) * (cycle_timer >> 25);

	return ticks;
}

/*
 * Some controllers exhibit one or more of the following bugs when updating the
 * iso cycle timer register:
 *  - When the lowest six bits are wrapping around to zero, a read that happens
 *    at the same time will return garbage in the lowest ten bits.
 *  - When the cycleOffset field wraps around to zero, the cycleCount field is
 *    not incremented for about 60 ns.
 *  - Occasionally, the entire register reads zero.
 *
 * To catch these, we read the register three times and ensure that the
 * difference between each two consecutive reads is approximately the same, i.e.
 * less than twice the other.  Furthermore, any negative difference indicates an
 * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
 * execute, so we have enough precision to compute the ratio of the differences.)
 */
static u32 get_cycle_time(struct fw_ohci *ohci)
{
	u32 c0, c1, c2;
	u32 t0, t1, t2;
	s32 diff01, diff12;
	int i;

1771 1772 1773
	if (has_reboot_by_cycle_timer_read_quirk(ohci))
		return 0;

1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806
	c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);

	if (ohci->quirks & QUIRK_CYCLE_TIMER) {
		i = 0;
		c1 = c2;
		c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
		do {
			c0 = c1;
			c1 = c2;
			c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
			t0 = cycle_timer_ticks(c0);
			t1 = cycle_timer_ticks(c1);
			t2 = cycle_timer_ticks(c2);
			diff01 = t1 - t0;
			diff12 = t2 - t1;
		} while ((diff01 <= 0 || diff12 <= 0 ||
			  diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
			 && i++ < 20);
	}

	return c2;
}

/*
 * This function has to be called at least every 64 seconds.  The bus_time
 * field stores not only the upper 25 bits of the BUS_TIME register but also
 * the most significant bit of the cycle timer in bit 6 so that we can detect
 * changes in this bit.
 */
static u32 update_bus_time(struct fw_ohci *ohci)
{
	u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;

1807 1808
	if (unlikely(!ohci->bus_time_running)) {
		reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1809
		ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) |
1810 1811 1812 1813
		                 (cycle_time_seconds & 0x40);
		ohci->bus_time_running = true;
	}

1814 1815 1816 1817 1818 1819
	if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
		ohci->bus_time += 0x40;

	return ohci->bus_time | cycle_time_seconds;
}

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static int get_status_for_port(struct fw_ohci *ohci, int port_index)
{
	int reg;

	mutex_lock(&ohci->phy_reg_mutex);
	reg = write_phy_reg(ohci, 7, port_index);
1826 1827
	if (reg >= 0)
		reg = read_phy_reg(ohci, 8);
1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
	mutex_unlock(&ohci->phy_reg_mutex);
	if (reg < 0)
		return reg;

	switch (reg & 0x0f) {
	case 0x06:
		return 2;	/* is child node (connected to parent node) */
	case 0x0e:
		return 3;	/* is parent node (connected to child node) */
	}
	return 1;		/* not connected */
}

static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
	int self_id_count)
{
	int i;
	u32 entry;
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1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
	for (i = 0; i < self_id_count; i++) {
		entry = ohci->self_id_buffer[i];
		if ((self_id & 0xff000000) == (entry & 0xff000000))
			return -1;
		if ((self_id & 0xff000000) < (entry & 0xff000000))
			return i;
	}
	return i;
}

1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881
static int initiated_reset(struct fw_ohci *ohci)
{
	int reg;
	int ret = 0;

	mutex_lock(&ohci->phy_reg_mutex);
	reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
	if (reg >= 0) {
		reg = read_phy_reg(ohci, 8);
		reg |= 0x40;
		reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
		if (reg >= 0) {
			reg = read_phy_reg(ohci, 12); /* read register 12 */
			if (reg >= 0) {
				if ((reg & 0x08) == 0x08) {
					/* bit 3 indicates "initiated reset" */
					ret = 0x2;
				}
			}
		}
	}
	mutex_unlock(&ohci->phy_reg_mutex);
	return ret;
}

1882
/*
1883 1884 1885
 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
 * Construct the selfID from phy register contents.
1886 1887 1888
 */
static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
{
1889 1890 1891
	int reg, i, pos, status;
	/* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
	u32 self_id = 0x8040c800;
1892 1893 1894

	reg = reg_read(ohci, OHCI1394_NodeID);
	if (!(reg & OHCI1394_NodeID_idValid)) {
1895 1896
		ohci_notice(ohci,
			    "node ID not valid, new bus reset in progress\n");
1897 1898 1899 1900
		return -EBUSY;
	}
	self_id |= ((reg & 0x3f) << 24); /* phy ID */

1901
	reg = ohci_read_phy_reg(&ohci->card, 4);
1902 1903 1904 1905
	if (reg < 0)
		return reg;
	self_id |= ((reg & 0x07) << 8); /* power class */

1906
	reg = ohci_read_phy_reg(&ohci->card, 1);
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917
	if (reg < 0)
		return reg;
	self_id |= ((reg & 0x3f) << 16); /* gap count */

	for (i = 0; i < 3; i++) {
		status = get_status_for_port(ohci, i);
		if (status < 0)
			return status;
		self_id |= ((status & 0x3) << (6 - (i * 2)));
	}

1918 1919
	self_id |= initiated_reset(ohci);

1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930
	pos = get_self_id_pos(ohci, self_id, self_id_count);
	if (pos >= 0) {
		memmove(&(ohci->self_id_buffer[pos+1]),
			&(ohci->self_id_buffer[pos]),
			(self_id_count - pos) * sizeof(*ohci->self_id_buffer));
		ohci->self_id_buffer[pos] = self_id;
		self_id_count++;
	}
	return self_id_count;
}

1931
static void bus_reset_work(struct work_struct *work)
1932
{
1933 1934
	struct fw_ohci *ohci =
		container_of(work, struct fw_ohci, bus_reset_work);
1935 1936
	int self_id_count, generation, new_generation, i, j;
	u32 reg;
1937 1938
	void *free_rom = NULL;
	dma_addr_t free_rom_bus = 0;
1939
	bool is_new_root;
1940 1941 1942

	reg = reg_read(ohci, OHCI1394_NodeID);
	if (!(reg & OHCI1394_NodeID_idValid)) {
1943 1944
		ohci_notice(ohci,
			    "node ID not valid, new bus reset in progress\n");
1945 1946
		return;
	}
1947
	if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1948
		ohci_notice(ohci, "malconfigured bus\n");
1949 1950 1951 1952
		return;
	}
	ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
			       OHCI1394_NodeID_nodeNumber);
1953

1954 1955 1956 1957 1958 1959
	is_new_root = (reg & OHCI1394_NodeID_root) != 0;
	if (!(ohci->is_root && is_new_root))
		reg_write(ohci, OHCI1394_LinkControlSet,
			  OHCI1394_LinkControl_cycleMaster);
	ohci->is_root = is_new_root;

1960 1961
	reg = reg_read(ohci, OHCI1394_SelfIDCount);
	if (reg & OHCI1394_SelfIDCount_selfIDError) {
1962
		ohci_notice(ohci, "self ID receive error\n");
1963 1964
		return;
	}
1965 1966
	/*
	 * The count in the SelfIDCount register is the number of
1967 1968
	 * bytes in the self ID receive buffer.  Since we also receive
	 * the inverted quadlets and a header quadlet, we shift one
1969 1970
	 * bit extra to get the actual number of self IDs.
	 */
1971
	self_id_count = (reg >> 3) & 0xff;
1972 1973

	if (self_id_count > 252) {
1974
		ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1975 1976
		return;
	}
1977

1978
	generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1979
	rmb();
1980 1981

	for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1982 1983
		u32 id  = cond_le32_to_cpu(ohci->self_id[i]);
		u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1984 1985

		if (id != ~id2) {
1986 1987 1988 1989 1990 1991 1992
			/*
			 * If the invalid data looks like a cycle start packet,
			 * it's likely to be the result of the cycle master
			 * having a wrong gap count.  In this case, the self IDs
			 * so far are valid and should be processed so that the
			 * bus manager can then correct the gap count.
			 */
1993 1994
			if (id == 0xffff008f) {
				ohci_notice(ohci, "ignoring spurious self IDs\n");
1995 1996 1997
				self_id_count = j;
				break;
			}
1998 1999 2000 2001

			ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
				    j, self_id_count, id, id2);
			return;
2002
		}
2003
		ohci->self_id_buffer[j] = id;
2004
	}
2005 2006 2007 2008

	if (ohci->quirks & QUIRK_TI_SLLZ059) {
		self_id_count = find_and_insert_self_id(ohci, self_id_count);
		if (self_id_count < 0) {
2009 2010
			ohci_notice(ohci,
				    "could not construct local self ID\n");
2011 2012 2013 2014 2015
			return;
		}
	}

	if (self_id_count == 0) {
2016
		ohci_notice(ohci, "no self IDs\n");
2017 2018
		return;
	}
2019
	rmb();
2020

2021 2022
	/*
	 * Check the consistency of the self IDs we just read.  The
2023 2024 2025 2026 2027 2028 2029 2030 2031
	 * problem we face is that a new bus reset can start while we
	 * read out the self IDs from the DMA buffer. If this happens,
	 * the DMA buffer will be overwritten with new self IDs and we
	 * will read out inconsistent data.  The OHCI specification
	 * (section 11.2) recommends a technique similar to
	 * linux/seqlock.h, where we remember the generation of the
	 * self IDs in the buffer before reading them out and compare
	 * it to the current generation after reading them out.  If
	 * the two generations match we know we have a consistent set
2032 2033
	 * of self IDs.
	 */
2034 2035 2036

	new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
	if (new_generation != generation) {
2037
		ohci_notice(ohci, "new bus reset, discarding self ids\n");
2038 2039 2040 2041
		return;
	}

	/* FIXME: Document how the locking works. */
2042
	spin_lock_irq(&ohci->lock);
2043

2044
	ohci->generation = -1; /* prevent AT packet queueing */
2045 2046
	context_stop(&ohci->at_request_ctx);
	context_stop(&ohci->at_response_ctx);
2047

2048
	spin_unlock_irq(&ohci->lock);
2049

2050 2051 2052 2053 2054
	/*
	 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
	 * packets in the AT queues and software needs to drain them.
	 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
	 */
2055 2056 2057
	at_context_flush(&ohci->at_request_ctx);
	at_context_flush(&ohci->at_response_ctx);

2058
	spin_lock_irq(&ohci->lock);
2059 2060

	ohci->generation = generation;
2061
	reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2062
	reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2063

2064
	if (ohci->quirks & QUIRK_RESET_PACKET)
2065 2066
		ohci->request_generation = generation;

2067 2068
	/*
	 * This next bit is unrelated to the AT context stuff but we
2069 2070 2071 2072
	 * have to do it under the spinlock also.  If a new config rom
	 * was set up before this reset, the old one is now no longer
	 * in use and we can free it. Update the config rom pointers
	 * to point to the current config rom and clear the
Thomas Weber's avatar
Thomas Weber committed
2073
	 * next_config_rom pointer so a new update can take place.
2074
	 */
2075 2076

	if (ohci->next_config_rom != NULL) {
2077 2078 2079 2080
		if (ohci->next_config_rom != ohci->config_rom) {
			free_rom      = ohci->config_rom;
			free_rom_bus  = ohci->config_rom_bus;
		}
2081 2082 2083 2084
		ohci->config_rom      = ohci->next_config_rom;
		ohci->config_rom_bus  = ohci->next_config_rom_bus;
		ohci->next_config_rom = NULL;

2085 2086
		/*
		 * Restore config_rom image and manually update
2087 2088
		 * config_rom registers.  Writing the header quadlet
		 * will indicate that the config rom is ready, so we
2089 2090
		 * do that last.
		 */
2091 2092
		reg_write(ohci, OHCI1394_BusOptions,
			  be32_to_cpu(ohci->config_rom[2]));
2093 2094 2095
		ohci->config_rom[0] = ohci->next_header;
		reg_write(ohci, OHCI1394_ConfigROMhdr,
			  be32_to_cpu(ohci->next_header));
2096 2097
	}

2098 2099 2100 2101
	if (param_remote_dma) {
		reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
		reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
	}
2102

2103
	spin_unlock_irq(&ohci->lock);
2104

2105
	if (free_rom)
2106
		dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus);
2107

2108
	log_selfids(ohci, generation, self_id_count);
2109

2110
	fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2111 2112 2113
				 self_id_count, ohci->self_id_buffer,
				 ohci->csr_state_setclear_abdicate);
	ohci->csr_state_setclear_abdicate = false;
2114 2115 2116 2117 2118
}

static irqreturn_t irq_handler(int irq, void *data)
{
	struct fw_ohci *ohci = data;
2119
	u32 event, iso_event;
2120 2121 2122 2123
	int i;

	event = reg_read(ohci, OHCI1394_IntEventClear);

2124
	if (!event || !~event)
2125 2126
		return IRQ_NONE;

2127
	/*
2128
	 * busReset and postedWriteErr events must not be cleared yet
2129 2130 2131 2132
	 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
	 */
	reg_write(ohci, OHCI1394_IntEventClear,
		  event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2133
	log_irqs(ohci, event);
2134
	// The flag is masked again at bus_reset_work() scheduled by selfID event.
2135 2136
	if (event & OHCI1394_busReset)
		reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2137 2138

	if (event & OHCI1394_selfIDComplete)
2139
		queue_work(selfid_workqueue, &ohci->bus_reset_work);
2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152

	if (event & OHCI1394_RQPkt)
		tasklet_schedule(&ohci->ar_request_ctx.tasklet);

	if (event & OHCI1394_RSPkt)
		tasklet_schedule(&ohci->ar_response_ctx.tasklet);

	if (event & OHCI1394_reqTxComplete)
		tasklet_schedule(&ohci->at_request_ctx.tasklet);

	if (event & OHCI1394_respTxComplete)
		tasklet_schedule(&ohci->at_response_ctx.tasklet);

2153 2154 2155 2156 2157 2158 2159 2160 2161 2162
	if (event & OHCI1394_isochRx) {
		iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);

		while (iso_event) {
			i = ffs(iso_event) - 1;
			tasklet_schedule(
				&ohci->ir_context_list[i].context.tasklet);
			iso_event &= ~(1 << i);
		}
2163 2164
	}

2165 2166 2167
	if (event & OHCI1394_isochTx) {
		iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2168

2169 2170 2171 2172 2173 2174
		while (iso_event) {
			i = ffs(iso_event) - 1;
			tasklet_schedule(
				&ohci->it_context_list[i].context.tasklet);
			iso_event &= ~(1 << i);
		}
2175 2176
	}

2177
	if (unlikely(event & OHCI1394_regAccessFail))
2178
		ohci_err(ohci, "register access failure\n");
2179

2180 2181 2182 2183 2184
	if (unlikely(event & OHCI1394_postedWriteErr)) {
		reg_read(ohci, OHCI1394_PostedWriteAddressHi);
		reg_read(ohci, OHCI1394_PostedWriteAddressLo);
		reg_write(ohci, OHCI1394_IntEventClear,
			  OHCI1394_postedWriteErr);
2185
		if (printk_ratelimit())
2186
			ohci_err(ohci, "PCI posted write error\n");
2187
	}
2188

2189 2190
	if (unlikely(event & OHCI1394_cycleTooLong)) {
		if (printk_ratelimit())
2191
			ohci_notice(ohci, "isochronous cycle too long\n");
2192 2193 2194 2195
		reg_write(ohci, OHCI1394_LinkControlSet,
			  OHCI1394_LinkControl_cycleMaster);
	}

2196 2197 2198 2199 2200 2201 2202 2203
	if (unlikely(event & OHCI1394_cycleInconsistent)) {
		/*
		 * We need to clear this event bit in order to make
		 * cycleMatch isochronous I/O work.  In theory we should
		 * stop active cycleMatch iso contexts now and restart
		 * them at least two cycles later.  (FIXME?)
		 */
		if (printk_ratelimit())
2204
			ohci_notice(ohci, "isochronous cycle inconsistent\n");
2205 2206
	}

2207 2208 2209
	if (unlikely(event & OHCI1394_unrecoverableError))
		handle_dead_contexts(ohci);

2210 2211 2212 2213
	if (event & OHCI1394_cycle64Seconds) {
		spin_lock(&ohci->lock);
		update_bus_time(ohci);
		spin_unlock(&ohci->lock);
2214 2215
	} else
		flush_writes(ohci);
2216

2217 2218 2219
	return IRQ_HANDLED;
}

2220 2221
static int software_reset(struct fw_ohci *ohci)
{
2222
	u32 val;
2223 2224 2225
	int i;

	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2226 2227 2228 2229
	for (i = 0; i < 500; i++) {
		val = reg_read(ohci, OHCI1394_HCControlSet);
		if (!~val)
			return -ENODEV; /* Card was ejected. */
2230

2231
		if (!(val & OHCI1394_HCControl_softReset))
2232
			return 0;
2233

2234 2235 2236 2237 2238 2239
		msleep(1);
	}

	return -EBUSY;
}

2240 2241 2242 2243 2244 2245 2246 2247 2248
static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
{
	size_t size = length * 4;

	memcpy(dest, src, size);
	if (size < CONFIG_ROM_SIZE)
		memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
}

2249 2250 2251
static int configure_1394a_enhancements(struct fw_ohci *ohci)
{
	bool enable_1394a;
2252
	int ret, clear, set, offset;
2253 2254 2255 2256 2257 2258 2259 2260

	/* Check if the driver should configure link and PHY. */
	if (!(reg_read(ohci, OHCI1394_HCControlSet) &
	      OHCI1394_HCControl_programPhyEnable))
		return 0;

	/* Paranoia: check whether the PHY supports 1394a, too. */
	enable_1394a = false;
2261 2262 2263 2264 2265 2266 2267 2268
	ret = read_phy_reg(ohci, 2);
	if (ret < 0)
		return ret;
	if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
		ret = read_paged_phy_reg(ohci, 1, 8);
		if (ret < 0)
			return ret;
		if (ret >= 1)
2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282
			enable_1394a = true;
	}

	if (ohci->quirks & QUIRK_NO_1394A)
		enable_1394a = false;

	/* Configure PHY and link consistently. */
	if (enable_1394a) {
		clear = 0;
		set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
	} else {
		clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
		set = 0;
	}
2283
	ret = update_phy_reg(ohci, 5, clear, set);
2284 2285
	if (ret < 0)
		return ret;
2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299

	if (enable_1394a)
		offset = OHCI1394_HCControlSet;
	else
		offset = OHCI1394_HCControlClear;
	reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);

	/* Clean up: configuration has been taken care of. */
	reg_write(ohci, OHCI1394_HCControlClear,
		  OHCI1394_HCControl_programPhyEnable);

	return 0;
}

2300 2301
static int probe_tsb41ba3d(struct fw_ohci *ohci)
{
2302 2303 2304
	/* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
	static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
	int reg, i;
2305 2306 2307 2308

	reg = read_phy_reg(ohci, 2);
	if (reg < 0)
		return reg;
2309 2310
	if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
		return 0;
2311

2312 2313 2314 2315 2316 2317
	for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
		reg = read_paged_phy_reg(ohci, 1, i + 10);
		if (reg < 0)
			return reg;
		if (reg != id[i])
			return 0;
2318
	}
2319
	return 1;
2320 2321
}

2322 2323
static int ohci_enable(struct fw_card *card,
		       const __be32 *config_rom, size_t length)
2324 2325
{
	struct fw_ohci *ohci = fw_ohci(card);
2326
	u32 lps, version, irqs;
2327
	int i, ret;
2328

2329 2330
	ret = software_reset(ohci);
	if (ret < 0) {
2331
		ohci_err(ohci, "failed to reset ohci card\n");
2332
		return ret;
2333 2334 2335 2336 2337 2338 2339
	}

	/*
	 * Now enable LPS, which we need in order to start accessing
	 * most of the registers.  In fact, on some cards (ALI M5251),
	 * accessing registers in the SClk domain without LPS enabled
	 * will lock up the machine.  Wait 50msec to make sure we have
2340 2341
	 * full link enabled.  However, with some cards (well, at least
	 * a JMicron PCIe card), we have to try again sometimes.
2342 2343 2344 2345
	 *
	 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
	 * cannot actually use the phy at that time.  These need tens of
	 * millisecods pause between LPS write and first phy access too.
2346
	 */
2347

2348 2349 2350 2351
	reg_write(ohci, OHCI1394_HCControlSet,
		  OHCI1394_HCControl_LPS |
		  OHCI1394_HCControl_postedWriteEnable);
	flush_writes(ohci);
2352

2353
	for (lps = 0, i = 0; !lps && i < 3; i++) {
2354 2355 2356 2357 2358 2359
		msleep(50);
		lps = reg_read(ohci, OHCI1394_HCControlSet) &
		      OHCI1394_HCControl_LPS;
	}

	if (!lps) {
2360
		ohci_err(ohci, "failed to set Link Power Status\n");
2361 2362
		return -EIO;
	}
2363

2364
	if (ohci->quirks & QUIRK_TI_SLLZ059) {
2365 2366 2367 2368
		ret = probe_tsb41ba3d(ohci);
		if (ret < 0)
			return ret;
		if (ret)
2369
			ohci_notice(ohci, "local TSB41BA3D phy\n");
2370
		else
2371 2372 2373
			ohci->quirks &= ~QUIRK_TI_SLLZ059;
	}

2374 2375 2376
	reg_write(ohci, OHCI1394_HCControlClear,
		  OHCI1394_HCControl_noByteSwapData);

2377
	reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2378 2379 2380 2381 2382 2383 2384
	reg_write(ohci, OHCI1394_LinkControlSet,
		  OHCI1394_LinkControl_cycleTimerEnable |
		  OHCI1394_LinkControl_cycleMaster);

	reg_write(ohci, OHCI1394_ATRetries,
		  OHCI1394_MAX_AT_REQ_RETRIES |
		  (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2385 2386
		  (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
		  (200 << 16));
2387

2388
	ohci->bus_time_running = false;
2389

2390 2391 2392 2393 2394
	for (i = 0; i < 32; i++)
		if (ohci->ir_context_support & (1 << i))
			reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
				  IR_CONTEXT_MULTI_CHANNEL_MODE);

2395 2396 2397 2398
	version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
	if (version >= OHCI_VERSION_1_1) {
		reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
			  0xfffffffe);
2399
		card->broadcast_channel_auto_allocated = true;
2400 2401
	}

2402 2403 2404 2405
	/* Get implemented bits of the priority arbitration request counter. */
	reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
	ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
	reg_write(ohci, OHCI1394_FairnessControl, 0);
2406
	card->priority_budget_implemented = ohci->pri_req_max != 0;
2407

2408
	reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2409 2410 2411
	reg_write(ohci, OHCI1394_IntEventClear, ~0);
	reg_write(ohci, OHCI1394_IntMaskClear, ~0);

2412 2413 2414
	ret = configure_1394a_enhancements(ohci);
	if (ret < 0)
		return ret;
2415

2416
	/* Activate link_on bit and contender bit in our self ID packets.*/
2417 2418 2419
	ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
	if (ret < 0)
		return ret;
2420

2421 2422
	/*
	 * When the link is not yet enabled, the atomic config rom
2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439
	 * update mechanism described below in ohci_set_config_rom()
	 * is not active.  We have to update ConfigRomHeader and
	 * BusOptions manually, and the write to ConfigROMmap takes
	 * effect immediately.  We tie this to the enabling of the
	 * link, so we have a valid config rom before enabling - the
	 * OHCI requires that ConfigROMhdr and BusOptions have valid
	 * values before enabling.
	 *
	 * However, when the ConfigROMmap is written, some controllers
	 * always read back quadlets 0 and 2 from the config rom to
	 * the ConfigRomHeader and BusOptions registers on bus reset.
	 * They shouldn't do that in this initial case where the link
	 * isn't enabled.  This means we have to use the same
	 * workaround here, setting the bus header to 0 and then write
	 * the right values in the bus reset tasklet.
	 */

2440
	if (config_rom) {
2441 2442
		ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
							    &ohci->next_config_rom_bus, GFP_KERNEL);
2443 2444
		if (ohci->next_config_rom == NULL)
			return -ENOMEM;
2445

2446
		copy_config_rom(ohci->next_config_rom, config_rom, length);
2447 2448 2449 2450 2451 2452 2453 2454
	} else {
		/*
		 * In the suspend case, config_rom is NULL, which
		 * means that we just reuse the old config rom.
		 */
		ohci->next_config_rom = ohci->config_rom;
		ohci->next_config_rom_bus = ohci->config_rom_bus;
	}
2455

2456
	ohci->next_header = ohci->next_config_rom[0];
2457 2458
	ohci->next_config_rom[0] = 0;
	reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2459 2460
	reg_write(ohci, OHCI1394_BusOptions,
		  be32_to_cpu(ohci->next_config_rom[2]));
2461 2462 2463 2464
	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);

	reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);

2465 2466 2467 2468 2469 2470
	irqs =	OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
		OHCI1394_RQPkt | OHCI1394_RSPkt |
		OHCI1394_isochTx | OHCI1394_isochRx |
		OHCI1394_postedWriteErr |
		OHCI1394_selfIDComplete |
		OHCI1394_regAccessFail |
2471 2472 2473
		OHCI1394_cycleInconsistent |
		OHCI1394_unrecoverableError |
		OHCI1394_cycleTooLong |
2474 2475
		OHCI1394_masterIntEnable |
		OHCI1394_busReset;
2476 2477
	reg_write(ohci, OHCI1394_IntMaskSet, irqs);

2478 2479 2480
	reg_write(ohci, OHCI1394_HCControlSet,
		  OHCI1394_HCControl_linkEnable |
		  OHCI1394_HCControl_BIBimageValid);
2481 2482 2483 2484 2485 2486

	reg_write(ohci, OHCI1394_LinkControlSet,
		  OHCI1394_LinkControl_rcvSelfID |
		  OHCI1394_LinkControl_rcvPhyPkt);

	ar_context_run(&ohci->ar_request_ctx);
2487 2488 2489
	ar_context_run(&ohci->ar_response_ctx);

	flush_writes(ohci);
2490

2491 2492
	/* We are ready to go, reset bus to finish initialization. */
	fw_schedule_bus_reset(&ohci->card, false, true);
2493 2494 2495 2496

	return 0;
}

2497
static int ohci_set_config_rom(struct fw_card *card,
2498
			       const __be32 *config_rom, size_t length)
2499 2500 2501
{
	struct fw_ohci *ohci;
	__be32 *next_config_rom;
2502
	dma_addr_t next_config_rom_bus;
2503 2504 2505

	ohci = fw_ohci(card);

2506 2507
	/*
	 * When the OHCI controller is enabled, the config rom update
2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529
	 * mechanism is a bit tricky, but easy enough to use.  See
	 * section 5.5.6 in the OHCI specification.
	 *
	 * The OHCI controller caches the new config rom address in a
	 * shadow register (ConfigROMmapNext) and needs a bus reset
	 * for the changes to take place.  When the bus reset is
	 * detected, the controller loads the new values for the
	 * ConfigRomHeader and BusOptions registers from the specified
	 * config rom and loads ConfigROMmap from the ConfigROMmapNext
	 * shadow register. All automatically and atomically.
	 *
	 * Now, there's a twist to this story.  The automatic load of
	 * ConfigRomHeader and BusOptions doesn't honor the
	 * noByteSwapData bit, so with a be32 config rom, the
	 * controller will load be32 values in to these registers
	 * during the atomic update, even on litte endian
	 * architectures.  The workaround we use is to put a 0 in the
	 * header quadlet; 0 is endian agnostic and means that the
	 * config rom isn't ready yet.  In the bus reset tasklet we
	 * then set up the real values for the two registers.
	 *
	 * We use ohci->lock to avoid racing with the code that sets
2530
	 * ohci->next_config_rom to NULL (see bus_reset_work).
2531 2532
	 */

2533 2534
	next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
					      &next_config_rom_bus, GFP_KERNEL);
2535 2536 2537
	if (next_config_rom == NULL)
		return -ENOMEM;

2538
	spin_lock_irq(&ohci->lock);
2539

2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550
	/*
	 * If there is not an already pending config_rom update,
	 * push our new allocation into the ohci->next_config_rom
	 * and then mark the local variable as null so that we
	 * won't deallocate the new buffer.
	 *
	 * OTOH, if there is a pending config_rom update, just
	 * use that buffer with the new config_rom data, and
	 * let this routine free the unused DMA allocation.
	 */

2551 2552 2553
	if (ohci->next_config_rom == NULL) {
		ohci->next_config_rom = next_config_rom;
		ohci->next_config_rom_bus = next_config_rom_bus;
2554 2555
		next_config_rom = NULL;
	}
2556

2557
	copy_config_rom(ohci->next_config_rom, config_rom, length);
2558

2559 2560
	ohci->next_header = config_rom[0];
	ohci->next_config_rom[0] = 0;
2561

2562
	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2563

2564
	spin_unlock_irq(&ohci->lock);
2565

2566
	/* If we didn't use the DMA allocation, delete it. */
2567 2568 2569 2570
	if (next_config_rom != NULL) {
		dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom,
				   next_config_rom_bus);
	}
2571

2572 2573
	/*
	 * Now initiate a bus reset to have the changes take
2574 2575 2576
	 * effect. We clean up the old config rom memory and DMA
	 * mappings in the bus reset tasklet, since the OHCI
	 * controller could need to access it before the bus reset
2577 2578
	 * takes effect.
	 */
2579

2580 2581 2582
	fw_schedule_bus_reset(&ohci->card, true, true);

	return 0;
2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598
}

static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
{
	struct fw_ohci *ohci = fw_ohci(card);

	at_context_transmit(&ohci->at_request_ctx, packet);
}

static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
{
	struct fw_ohci *ohci = fw_ohci(card);

	at_context_transmit(&ohci->at_response_ctx, packet);
}

2599 2600 2601
static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
{
	struct fw_ohci *ohci = fw_ohci(card);
2602 2603
	struct context *ctx = &ohci->at_request_ctx;
	struct driver_data *driver_data = packet->driver_data;
2604
	int ret = -ENOENT;
2605

2606
	tasklet_disable_in_atomic(&ctx->tasklet);
2607

2608 2609
	if (packet->ack != 0)
		goto out;
2610

2611
	if (packet->payload_mapped)
2612 2613 2614
		dma_unmap_single(ohci->card.device, packet->payload_bus,
				 packet->payload_length, DMA_TO_DEVICE);

2615
	log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2616 2617
	driver_data->packet = NULL;
	packet->ack = RCODE_CANCELLED;
2618 2619 2620 2621

	// Timestamping on behalf of the hardware.
	packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci));

2622
	packet->callback(packet, &ohci->card, packet->ack);
2623
	ret = 0;
2624 2625
 out:
	tasklet_enable(&ctx->tasklet);
2626

2627
	return ret;
2628 2629
}

2630 2631
static int ohci_enable_phys_dma(struct fw_card *card,
				int node_id, int generation)
2632 2633 2634
{
	struct fw_ohci *ohci = fw_ohci(card);
	unsigned long flags;
2635
	int n, ret = 0;
2636

2637 2638 2639
	if (param_remote_dma)
		return 0;

2640 2641 2642 2643
	/*
	 * FIXME:  Make sure this bitmask is cleared when we clear the busReset
	 * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
	 */
2644 2645 2646 2647

	spin_lock_irqsave(&ohci->lock, flags);

	if (ohci->generation != generation) {
2648
		ret = -ESTALE;
2649 2650 2651
		goto out;
	}

2652 2653 2654 2655
	/*
	 * Note, if the node ID contains a non-local bus ID, physical DMA is
	 * enabled for _all_ nodes on remote buses.
	 */
2656 2657 2658 2659 2660 2661 2662

	n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
	if (n < 32)
		reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
	else
		reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));

2663 2664
	flush_writes(ohci);
 out:
2665
	spin_unlock_irqrestore(&ohci->lock, flags);
2666 2667

	return ret;
2668
}
Stefan Richter's avatar
Stefan Richter committed
2669

2670
static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2671
{
2672
	struct fw_ohci *ohci = fw_ohci(card);
2673 2674
	unsigned long flags;
	u32 value;
2675 2676

	switch (csr_offset) {
2677 2678 2679 2680 2681
	case CSR_STATE_CLEAR:
	case CSR_STATE_SET:
		if (ohci->is_root &&
		    (reg_read(ohci, OHCI1394_LinkControlSet) &
		     OHCI1394_LinkControl_cycleMaster))
2682
			value = CSR_STATE_BIT_CMSTR;
2683
		else
2684 2685 2686
			value = 0;
		if (ohci->csr_state_setclear_abdicate)
			value |= CSR_STATE_BIT_ABDICATE;
2687

2688
		return value;
2689

2690 2691 2692
	case CSR_NODE_IDS:
		return reg_read(ohci, OHCI1394_NodeID) << 16;

2693 2694 2695
	case CSR_CYCLE_TIME:
		return get_cycle_time(ohci);

2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706
	case CSR_BUS_TIME:
		/*
		 * We might be called just after the cycle timer has wrapped
		 * around but just before the cycle64Seconds handler, so we
		 * better check here, too, if the bus time needs to be updated.
		 */
		spin_lock_irqsave(&ohci->lock, flags);
		value = update_bus_time(ohci);
		spin_unlock_irqrestore(&ohci->lock, flags);
		return value;

2707 2708 2709 2710
	case CSR_BUSY_TIMEOUT:
		value = reg_read(ohci, OHCI1394_ATRetries);
		return (value >> 4) & 0x0ffff00f;

2711 2712 2713 2714
	case CSR_PRIORITY_BUDGET:
		return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
			(ohci->pri_req_max << 8);

2715 2716 2717 2718
	default:
		WARN_ON(1);
		return 0;
	}
2719 2720
}

2721
static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2722 2723
{
	struct fw_ohci *ohci = fw_ohci(card);
2724
	unsigned long flags;
2725

2726
	switch (csr_offset) {
2727 2728 2729 2730 2731 2732
	case CSR_STATE_CLEAR:
		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
			reg_write(ohci, OHCI1394_LinkControlClear,
				  OHCI1394_LinkControl_cycleMaster);
			flush_writes(ohci);
		}
2733 2734
		if (value & CSR_STATE_BIT_ABDICATE)
			ohci->csr_state_setclear_abdicate = false;
2735
		break;
2736

2737 2738 2739 2740 2741 2742
	case CSR_STATE_SET:
		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
			reg_write(ohci, OHCI1394_LinkControlSet,
				  OHCI1394_LinkControl_cycleMaster);
			flush_writes(ohci);
		}
2743 2744
		if (value & CSR_STATE_BIT_ABDICATE)
			ohci->csr_state_setclear_abdicate = true;
2745
		break;
2746

2747 2748 2749 2750 2751
	case CSR_NODE_IDS:
		reg_write(ohci, OHCI1394_NodeID, value >> 16);
		flush_writes(ohci);
		break;

2752 2753 2754 2755 2756 2757 2758
	case CSR_CYCLE_TIME:
		reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
		reg_write(ohci, OHCI1394_IntEventSet,
			  OHCI1394_cycleInconsistent);
		flush_writes(ohci);
		break;

2759 2760
	case CSR_BUS_TIME:
		spin_lock_irqsave(&ohci->lock, flags);
2761 2762
		ohci->bus_time = (update_bus_time(ohci) & 0x40) |
		                 (value & ~0x7f);
2763 2764 2765
		spin_unlock_irqrestore(&ohci->lock, flags);
		break;

2766 2767 2768 2769 2770 2771 2772
	case CSR_BUSY_TIMEOUT:
		value = (value & 0xf) | ((value & 0xf) << 4) |
			((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
		reg_write(ohci, OHCI1394_ATRetries, value);
		flush_writes(ohci);
		break;

2773 2774 2775 2776 2777
	case CSR_PRIORITY_BUDGET:
		reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
		flush_writes(ohci);
		break;

2778 2779 2780 2781
	default:
		WARN_ON(1);
		break;
	}
2782 2783
}

2784
static void flush_iso_completions(struct iso_context *ctx)
2785
{
2786 2787 2788 2789 2790
	ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
			      ctx->header_length, ctx->header,
			      ctx->base.callback_data);
	ctx->header_length = 0;
}
2791

2792
static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2793
{
2794
	u32 *ctx_hdr;
2795

2796 2797 2798
	if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
		if (ctx->base.drop_overflow_headers)
			return;
2799
		flush_iso_completions(ctx);
2800
	}
2801

2802
	ctx_hdr = ctx->header + ctx->header_length;
2803
	ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2804 2805

	/*
2806 2807 2808
	 * The two iso header quadlets are byteswapped to little
	 * endian by the controller, but we want to present them
	 * as big endian for consistency with the bus endianness.
2809 2810
	 */
	if (ctx->base.header_size > 0)
2811
		ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2812
	if (ctx->base.header_size > 4)
2813
		ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2814
	if (ctx->base.header_size > 8)
2815
		memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2816 2817 2818
	ctx->header_length += ctx->base.header_size;
}

2819 2820 2821 2822 2823 2824
static int handle_ir_packet_per_buffer(struct context *context,
				       struct descriptor *d,
				       struct descriptor *last)
{
	struct iso_context *ctx =
		container_of(context, struct iso_context, context);
2825
	struct descriptor *pd;
2826
	u32 buffer_dma;
2827

2828
	for (pd = d; pd <= last; pd++)
2829 2830 2831
		if (pd->transfer_status)
			break;
	if (pd > last)
2832 2833 2834
		/* Descriptor(s) not done yet, stop iteration */
		return 0;

2835 2836 2837 2838 2839 2840 2841 2842 2843 2844
	while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
		d++;
		buffer_dma = le32_to_cpu(d->data_address);
		dma_sync_single_range_for_cpu(context->ohci->card.device,
					      buffer_dma & PAGE_MASK,
					      buffer_dma & ~PAGE_MASK,
					      le16_to_cpu(d->req_count),
					      DMA_FROM_DEVICE);
	}

2845
	copy_iso_headers(ctx, (u32 *) (last + 1));
2846

2847 2848
	if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
		flush_iso_completions(ctx);
2849 2850 2851 2852

	return 1;
}

2853 2854 2855 2856 2857 2858 2859
/* d == last because each descriptor block is only a single descriptor. */
static int handle_ir_buffer_fill(struct context *context,
				 struct descriptor *d,
				 struct descriptor *last)
{
	struct iso_context *ctx =
		container_of(context, struct iso_context, context);
2860
	unsigned int req_count, res_count, completed;
2861
	u32 buffer_dma;
2862

2863
	req_count = le16_to_cpu(last->req_count);
2864
	res_count = le16_to_cpu(READ_ONCE(last->res_count));
2865 2866 2867 2868 2869 2870 2871 2872 2873
	completed = req_count - res_count;
	buffer_dma = le32_to_cpu(last->data_address);

	if (completed > 0) {
		ctx->mc_buffer_bus = buffer_dma;
		ctx->mc_completed = completed;
	}

	if (res_count != 0)
2874 2875 2876
		/* Descriptor(s) not done yet, stop iteration */
		return 0;

2877 2878 2879
	dma_sync_single_range_for_cpu(context->ohci->card.device,
				      buffer_dma & PAGE_MASK,
				      buffer_dma & ~PAGE_MASK,
2880
				      completed, DMA_FROM_DEVICE);
2881

2882
	if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2883
		ctx->base.callback.mc(&ctx->base,
2884
				      buffer_dma + completed,
2885
				      ctx->base.callback_data);
2886 2887
		ctx->mc_completed = 0;
	}
2888 2889 2890 2891

	return 1;
}

2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904
static void flush_ir_buffer_fill(struct iso_context *ctx)
{
	dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
				      ctx->mc_buffer_bus & PAGE_MASK,
				      ctx->mc_buffer_bus & ~PAGE_MASK,
				      ctx->mc_completed, DMA_FROM_DEVICE);

	ctx->base.callback.mc(&ctx->base,
			      ctx->mc_buffer_bus + ctx->mc_completed,
			      ctx->base.callback_data);
	ctx->mc_completed = 0;
}

2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941
static inline void sync_it_packet_for_cpu(struct context *context,
					  struct descriptor *pd)
{
	__le16 control;
	u32 buffer_dma;

	/* only packets beginning with OUTPUT_MORE* have data buffers */
	if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
		return;

	/* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
	pd += 2;

	/*
	 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
	 * data buffer is in the context program's coherent page and must not
	 * be synced.
	 */
	if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
	    (context->current_bus          & PAGE_MASK)) {
		if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
			return;
		pd++;
	}

	do {
		buffer_dma = le32_to_cpu(pd->data_address);
		dma_sync_single_range_for_cpu(context->ohci->card.device,
					      buffer_dma & PAGE_MASK,
					      buffer_dma & ~PAGE_MASK,
					      le16_to_cpu(pd->req_count),
					      DMA_TO_DEVICE);
		control = pd->control;
		pd++;
	} while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
}

2942 2943 2944
static int handle_it_packet(struct context *context,
			    struct descriptor *d,
			    struct descriptor *last)
2945
{
2946 2947
	struct iso_context *ctx =
		container_of(context, struct iso_context, context);
2948
	struct descriptor *pd;
2949
	__be32 *ctx_hdr;
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Stefan Richter committed
2950

2951 2952 2953 2954 2955
	for (pd = d; pd <= last; pd++)
		if (pd->transfer_status)
			break;
	if (pd > last)
		/* Descriptor(s) not done yet, stop iteration */
2956 2957
		return 0;

2958 2959
	sync_it_packet_for_cpu(context, d);

2960 2961 2962
	if (ctx->header_length + 4 > PAGE_SIZE) {
		if (ctx->base.drop_overflow_headers)
			return 1;
2963
		flush_iso_completions(ctx);
2964
	}
2965

2966
	ctx_hdr = ctx->header + ctx->header_length;
2967
	ctx->last_timestamp = le16_to_cpu(last->res_count);
2968 2969 2970 2971 2972
	/* Present this value as big-endian to match the receive code */
	*ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
			       le16_to_cpu(pd->res_count));
	ctx->header_length += 4;

2973 2974 2975
	if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
		flush_iso_completions(ctx);

2976
	return 1;
2977 2978
}

2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989
static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
{
	u32 hi = channels >> 32, lo = channels;

	reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
	reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
	reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
	reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
	ohci->mc_channels = channels;
}

2990
static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2991
				int type, int channel, size_t header_size)
2992 2993
{
	struct fw_ohci *ohci = fw_ohci(card);
2994 2995 2996 2997
	struct iso_context *ctx;
	descriptor_callback_t callback;
	u64 *channels;
	u32 *mask, regs;
2998
	int index, ret = -EBUSY;
2999

3000
	spin_lock_irq(&ohci->lock);
3001

3002 3003 3004
	switch (type) {
	case FW_ISO_CONTEXT_TRANSMIT:
		mask     = &ohci->it_context_mask;
3005
		callback = handle_it_packet;
3006 3007 3008 3009 3010 3011 3012 3013 3014
		index    = ffs(*mask) - 1;
		if (index >= 0) {
			*mask &= ~(1 << index);
			regs = OHCI1394_IsoXmitContextBase(index);
			ctx  = &ohci->it_context_list[index];
		}
		break;

	case FW_ISO_CONTEXT_RECEIVE:
3015
		channels = &ohci->ir_context_channels;
3016
		mask     = &ohci->ir_context_mask;
3017
		callback = handle_ir_packet_per_buffer;
3018 3019 3020 3021 3022 3023 3024 3025
		index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
		if (index >= 0) {
			*channels &= ~(1ULL << channel);
			*mask     &= ~(1 << index);
			regs = OHCI1394_IsoRcvContextBase(index);
			ctx  = &ohci->ir_context_list[index];
		}
		break;
3026

3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		mask     = &ohci->ir_context_mask;
		callback = handle_ir_buffer_fill;
		index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
		if (index >= 0) {
			ohci->mc_allocated = true;
			*mask &= ~(1 << index);
			regs = OHCI1394_IsoRcvContextBase(index);
			ctx  = &ohci->ir_context_list[index];
		}
		break;

	default:
		index = -1;
		ret = -ENOSYS;
3042
	}
3043

3044
	spin_unlock_irq(&ohci->lock);
3045 3046

	if (index < 0)
3047
		return ERR_PTR(ret);
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3048

3049
	memset(ctx, 0, sizeof(*ctx));
3050 3051
	ctx->header_length = 0;
	ctx->header = (void *) __get_free_page(GFP_KERNEL);
3052 3053
	if (ctx->header == NULL) {
		ret = -ENOMEM;
3054
		goto out;
3055
	}
3056 3057
	ret = context_init(&ctx->context, ohci, regs, callback);
	if (ret < 0)
3058
		goto out_with_header;
3059

3060
	if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3061
		set_multichannel_mask(ohci, 0);
3062 3063
		ctx->mc_completed = 0;
	}
3064

3065
	return &ctx->base;
3066 3067 3068 3069

 out_with_header:
	free_page((unsigned long)ctx->header);
 out:
3070
	spin_lock_irq(&ohci->lock);
3071 3072 3073 3074 3075 3076 3077 3078 3079 3080

	switch (type) {
	case FW_ISO_CONTEXT_RECEIVE:
		*channels |= 1ULL << channel;
		break;

	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		ohci->mc_allocated = false;
		break;
	}
3081
	*mask |= 1 << index;
3082

3083
	spin_unlock_irq(&ohci->lock);
3084

3085
	return ERR_PTR(ret);
3086 3087
}

3088 3089
static int ohci_start_iso(struct fw_iso_context *base,
			  s32 cycle, u32 sync, u32 tags)
3090
{
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3091
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3092
	struct fw_ohci *ohci = ctx->context.ohci;
3093
	u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3094 3095
	int index;

3096 3097 3098 3099
	/* the controller cannot start without any queued packets */
	if (ctx->context.last->branch_address == 0)
		return -ENODATA;

3100 3101
	switch (ctx->base.type) {
	case FW_ISO_CONTEXT_TRANSMIT:
3102
		index = ctx - ohci->it_context_list;
3103 3104 3105
		match = 0;
		if (cycle >= 0)
			match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3106
				(cycle & 0x7fff) << 16;
3107

3108 3109
		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
		reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3110
		context_run(&ctx->context, match);
3111 3112 3113 3114
		break;

	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3115
		fallthrough;
3116
	case FW_ISO_CONTEXT_RECEIVE:
3117
		index = ctx - ohci->ir_context_list;
3118 3119 3120 3121 3122
		match = (tags << 28) | (sync << 8) | ctx->base.channel;
		if (cycle >= 0) {
			match |= (cycle & 0x07fff) << 12;
			control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
		}
3123

3124 3125
		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
		reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3126
		reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3127
		context_run(&ctx->context, control);
3128 3129 3130 3131

		ctx->sync = sync;
		ctx->tags = tags;

3132
		break;
3133
	}
3134 3135 3136 3137

	return 0;
}

3138 3139 3140
static int ohci_stop_iso(struct fw_iso_context *base)
{
	struct fw_ohci *ohci = fw_ohci(base->card);
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3141
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3142 3143
	int index;

3144 3145
	switch (ctx->base.type) {
	case FW_ISO_CONTEXT_TRANSMIT:
3146 3147
		index = ctx - ohci->it_context_list;
		reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3148 3149 3150 3151
		break;

	case FW_ISO_CONTEXT_RECEIVE:
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3152 3153
		index = ctx - ohci->ir_context_list;
		reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3154
		break;
3155 3156 3157
	}
	flush_writes(ohci);
	context_stop(&ctx->context);
3158
	tasklet_kill(&ctx->context.tasklet);
3159 3160 3161 3162

	return 0;
}

3163 3164 3165
static void ohci_free_iso_context(struct fw_iso_context *base)
{
	struct fw_ohci *ohci = fw_ohci(base->card);
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3166
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3167 3168 3169
	unsigned long flags;
	int index;

3170 3171
	ohci_stop_iso(base);
	context_release(&ctx->context);
3172
	free_page((unsigned long)ctx->header);
3173

3174 3175
	spin_lock_irqsave(&ohci->lock, flags);

3176 3177
	switch (base->type) {
	case FW_ISO_CONTEXT_TRANSMIT:
3178 3179
		index = ctx - ohci->it_context_list;
		ohci->it_context_mask |= 1 << index;
3180 3181 3182
		break;

	case FW_ISO_CONTEXT_RECEIVE:
3183 3184
		index = ctx - ohci->ir_context_list;
		ohci->ir_context_mask |= 1 << index;
3185
		ohci->ir_context_channels |= 1ULL << base->channel;
3186 3187 3188 3189 3190 3191 3192 3193 3194
		break;

	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		index = ctx - ohci->ir_context_list;
		ohci->ir_context_mask |= 1 << index;
		ohci->ir_context_channels |= ohci->mc_channels;
		ohci->mc_channels = 0;
		ohci->mc_allocated = false;
		break;
3195 3196 3197 3198 3199
	}

	spin_unlock_irqrestore(&ohci->lock, flags);
}

3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229
static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
{
	struct fw_ohci *ohci = fw_ohci(base->card);
	unsigned long flags;
	int ret;

	switch (base->type) {
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:

		spin_lock_irqsave(&ohci->lock, flags);

		/* Don't allow multichannel to grab other contexts' channels. */
		if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
			*channels = ohci->ir_context_channels;
			ret = -EBUSY;
		} else {
			set_multichannel_mask(ohci, *channels);
			ret = 0;
		}

		spin_unlock_irqrestore(&ohci->lock, flags);

		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

3230 3231 3232 3233 3234 3235 3236 3237
#ifdef CONFIG_PM
static void ohci_resume_iso_dma(struct fw_ohci *ohci)
{
	int i;
	struct iso_context *ctx;

	for (i = 0 ; i < ohci->n_ir ; i++) {
		ctx = &ohci->ir_context_list[i];
3238
		if (ctx->context.running)
3239 3240 3241 3242 3243
			ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
	}

	for (i = 0 ; i < ohci->n_it ; i++) {
		ctx = &ohci->it_context_list[i];
3244
		if (ctx->context.running)
3245 3246 3247 3248 3249
			ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
	}
}
#endif

3250 3251 3252 3253
static int queue_iso_transmit(struct iso_context *ctx,
			      struct fw_iso_packet *packet,
			      struct fw_iso_buffer *buffer,
			      unsigned long payload)
3254
{
3255
	struct descriptor *d, *last, *pd;
3256 3257
	struct fw_iso_packet *p;
	__le32 *header;
3258
	dma_addr_t d_bus, page_bus;
3259 3260
	u32 z, header_z, payload_z, irq;
	u32 payload_index, payload_end_index, next_page_index;
3261
	int page, end_page, i, length, offset;
3262 3263

	p = packet;
3264
	payload_index = payload;
3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282

	if (p->skip)
		z = 1;
	else
		z = 2;
	if (p->header_length > 0)
		z++;

	/* Determine the first page the payload isn't contained in. */
	end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
	if (p->payload_length > 0)
		payload_z = end_page - (payload_index >> PAGE_SHIFT);
	else
		payload_z = 0;

	z += payload_z;

	/* Get header size in number of descriptors. */
3283
	header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3284

3285 3286 3287
	d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
	if (d == NULL)
		return -ENOMEM;
3288 3289

	if (!p->skip) {
3290
		d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3291
		d[0].req_count = cpu_to_le16(8);
3292 3293 3294 3295 3296 3297 3298 3299
		/*
		 * Link the skip address to this descriptor itself.  This causes
		 * a context to skip a cycle whenever lost cycles or FIFO
		 * overruns occur, without dropping the data.  The application
		 * should then decide whether this is an error condition or not.
		 * FIXME:  Make the context's cycle-lost behaviour configurable?
		 */
		d[0].branch_address = cpu_to_le32(d_bus | z);
3300 3301

		header = (__le32 *) &d[1];
3302 3303 3304 3305 3306
		header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
					IT_HEADER_TAG(p->tag) |
					IT_HEADER_TCODE(TCODE_STREAM_DATA) |
					IT_HEADER_CHANNEL(ctx->base.channel) |
					IT_HEADER_SPEED(ctx->base.speed));
3307
		header[1] =
3308
			cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3309 3310 3311 3312 3313
							  p->payload_length));
	}

	if (p->header_length > 0) {
		d[2].req_count    = cpu_to_le16(p->header_length);
3314
		d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326
		memcpy(&d[z], p->header, p->header_length);
	}

	pd = d + z - payload_z;
	payload_end_index = payload_index + p->payload_length;
	for (i = 0; i < payload_z; i++) {
		page               = payload_index >> PAGE_SHIFT;
		offset             = payload_index & ~PAGE_MASK;
		next_page_index    = (page + 1) << PAGE_SHIFT;
		length             =
			min(next_page_index, payload_end_index) - payload_index;
		pd[i].req_count    = cpu_to_le16(length);
3327 3328 3329

		page_bus = page_private(buffer->pages[page]);
		pd[i].data_address = cpu_to_le32(page_bus + offset);
3330

3331 3332 3333 3334
		dma_sync_single_range_for_device(ctx->context.ohci->card.device,
						 page_bus, offset, length,
						 DMA_TO_DEVICE);

3335 3336 3337 3338
		payload_index += length;
	}

	if (p->interrupt)
3339
		irq = DESCRIPTOR_IRQ_ALWAYS;
3340
	else
3341
		irq = DESCRIPTOR_NO_IRQ;
3342

3343
	last = z == 2 ? d : d + z - 1;
3344 3345 3346
	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
				     DESCRIPTOR_STATUS |
				     DESCRIPTOR_BRANCH_ALWAYS |
3347
				     irq);
3348

3349
	context_append(&ctx->context, d, z, header_z);
3350 3351 3352

	return 0;
}
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3353

3354 3355 3356 3357
static int queue_iso_packet_per_buffer(struct iso_context *ctx,
				       struct fw_iso_packet *packet,
				       struct fw_iso_buffer *buffer,
				       unsigned long payload)
3358
{
3359
	struct device *device = ctx->context.ohci->card.device;
3360
	struct descriptor *d, *pd;
3361 3362
	dma_addr_t d_bus, page_bus;
	u32 z, header_z, rest;
3363 3364
	int i, j, length;
	int page, offset, packet_count, header_size, payload_per_buffer;
3365 3366

	/*
3367 3368
	 * The OHCI controller puts the isochronous header and trailer in the
	 * buffer, so we need at least 8 bytes.
3369
	 */
3370
	packet_count = packet->header_length / ctx->base.header_size;
3371
	header_size  = max(ctx->base.header_size, (size_t)8);
3372 3373 3374 3375 3376

	/* Get header size in number of descriptors. */
	header_z = DIV_ROUND_UP(header_size, sizeof(*d));
	page     = payload >> PAGE_SHIFT;
	offset   = payload & ~PAGE_MASK;
3377
	payload_per_buffer = packet->payload_length / packet_count;
3378 3379 3380

	for (i = 0; i < packet_count; i++) {
		/* d points to the header descriptor */
3381
		z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3382
		d = context_get_descriptors(&ctx->context,
3383
				z + header_z, &d_bus);
3384 3385 3386
		if (d == NULL)
			return -ENOMEM;

3387 3388
		d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
					      DESCRIPTOR_INPUT_MORE);
3389
		if (packet->skip && i == 0)
3390
			d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3391 3392
		d->req_count    = cpu_to_le16(header_size);
		d->res_count    = d->req_count;
3393
		d->transfer_status = 0;
3394 3395
		d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));

3396
		rest = payload_per_buffer;
3397
		pd = d;
3398
		for (j = 1; j < z; j++) {
3399
			pd++;
3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413
			pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
						  DESCRIPTOR_INPUT_MORE);

			if (offset + rest < PAGE_SIZE)
				length = rest;
			else
				length = PAGE_SIZE - offset;
			pd->req_count = cpu_to_le16(length);
			pd->res_count = pd->req_count;
			pd->transfer_status = 0;

			page_bus = page_private(buffer->pages[page]);
			pd->data_address = cpu_to_le32(page_bus + offset);

3414 3415 3416 3417
			dma_sync_single_range_for_device(device, page_bus,
							 offset, length,
							 DMA_FROM_DEVICE);

3418 3419 3420 3421 3422
			offset = (offset + length) & ~PAGE_MASK;
			rest -= length;
			if (offset == 0)
				page++;
		}
3423 3424 3425
		pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
					  DESCRIPTOR_INPUT_LAST |
					  DESCRIPTOR_BRANCH_ALWAYS);
3426
		if (packet->interrupt && i == packet_count - 1)
3427 3428 3429 3430 3431 3432 3433 3434
			pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);

		context_append(&ctx->context, d, z, header_z);
	}

	return 0;
}

3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476
static int queue_iso_buffer_fill(struct iso_context *ctx,
				 struct fw_iso_packet *packet,
				 struct fw_iso_buffer *buffer,
				 unsigned long payload)
{
	struct descriptor *d;
	dma_addr_t d_bus, page_bus;
	int page, offset, rest, z, i, length;

	page   = payload >> PAGE_SHIFT;
	offset = payload & ~PAGE_MASK;
	rest   = packet->payload_length;

	/* We need one descriptor for each page in the buffer. */
	z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);

	if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
		return -EFAULT;

	for (i = 0; i < z; i++) {
		d = context_get_descriptors(&ctx->context, 1, &d_bus);
		if (d == NULL)
			return -ENOMEM;

		d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
					 DESCRIPTOR_BRANCH_ALWAYS);
		if (packet->skip && i == 0)
			d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
		if (packet->interrupt && i == z - 1)
			d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);

		if (offset + rest < PAGE_SIZE)
			length = rest;
		else
			length = PAGE_SIZE - offset;
		d->req_count = cpu_to_le16(length);
		d->res_count = d->req_count;
		d->transfer_status = 0;

		page_bus = page_private(buffer->pages[page]);
		d->data_address = cpu_to_le32(page_bus + offset);

3477 3478 3479 3480
		dma_sync_single_range_for_device(ctx->context.ohci->card.device,
						 page_bus, offset, length,
						 DMA_FROM_DEVICE);

3481 3482 3483 3484 3485 3486 3487 3488 3489 3490
		rest -= length;
		offset = 0;
		page++;

		context_append(&ctx->context, d, 1, 0);
	}

	return 0;
}

3491 3492 3493 3494
static int ohci_queue_iso(struct fw_iso_context *base,
			  struct fw_iso_packet *packet,
			  struct fw_iso_buffer *buffer,
			  unsigned long payload)
3495
{
3496
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3497
	unsigned long flags;
3498
	int ret = -ENOSYS;
3499

3500
	spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511
	switch (base->type) {
	case FW_ISO_CONTEXT_TRANSMIT:
		ret = queue_iso_transmit(ctx, packet, buffer, payload);
		break;
	case FW_ISO_CONTEXT_RECEIVE:
		ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
		break;
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
		break;
	}
3512 3513
	spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);

3514
	return ret;
3515 3516
}

3517 3518 3519 3520 3521 3522 3523 3524
static void ohci_flush_queue_iso(struct fw_iso_context *base)
{
	struct context *ctx =
			&container_of(base, struct iso_context, base)->context;

	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
}

3525 3526 3527 3528 3529
static int ohci_flush_iso_completions(struct fw_iso_context *base)
{
	struct iso_context *ctx = container_of(base, struct iso_context, base);
	int ret = 0;

3530
	tasklet_disable_in_atomic(&ctx->context.tasklet);
3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549

	if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
		context_tasklet((unsigned long)&ctx->context);

		switch (base->type) {
		case FW_ISO_CONTEXT_TRANSMIT:
		case FW_ISO_CONTEXT_RECEIVE:
			if (ctx->header_length != 0)
				flush_iso_completions(ctx);
			break;
		case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
			if (ctx->mc_completed != 0)
				flush_ir_buffer_fill(ctx);
			break;
		default:
			ret = -ENOSYS;
		}

		clear_bit_unlock(0, &ctx->flushing_completions);
3550
		smp_mb__after_atomic();
3551 3552 3553 3554 3555 3556 3557
	}

	tasklet_enable(&ctx->context.tasklet);

	return ret;
}

3558
static const struct fw_card_driver ohci_driver = {
3559
	.enable			= ohci_enable,
3560
	.read_phy_reg		= ohci_read_phy_reg,
3561 3562 3563 3564
	.update_phy_reg		= ohci_update_phy_reg,
	.set_config_rom		= ohci_set_config_rom,
	.send_request		= ohci_send_request,
	.send_response		= ohci_send_response,
3565
	.cancel_packet		= ohci_cancel_packet,
3566
	.enable_phys_dma	= ohci_enable_phys_dma,
3567 3568
	.read_csr		= ohci_read_csr,
	.write_csr		= ohci_write_csr,
3569 3570 3571

	.allocate_iso_context	= ohci_allocate_iso_context,
	.free_iso_context	= ohci_free_iso_context,
3572
	.set_iso_channels	= ohci_set_iso_channels,
3573
	.queue_iso		= ohci_queue_iso,
3574
	.flush_queue_iso	= ohci_flush_queue_iso,
3575
	.flush_iso_completions	= ohci_flush_iso_completions,
3576
	.start_iso		= ohci_start_iso,
3577
	.stop_iso		= ohci_stop_iso,
3578 3579
};

3580
#ifdef CONFIG_PPC_PMAC
3581
static void pmac_ohci_on(struct pci_dev *dev)
3582
{
3583 3584 3585 3586 3587 3588 3589 3590
	if (machine_is(powermac)) {
		struct device_node *ofn = pci_device_to_OF_node(dev);

		if (ofn) {
			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
			pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
		}
	}
3591 3592
}

3593
static void pmac_ohci_off(struct pci_dev *dev)
3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604
{
	if (machine_is(powermac)) {
		struct device_node *ofn = pci_device_to_OF_node(dev);

		if (ofn) {
			pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
		}
	}
}
#else
3605 3606
static inline void pmac_ohci_on(struct pci_dev *dev) {}
static inline void pmac_ohci_off(struct pci_dev *dev) {}
3607 3608
#endif /* CONFIG_PPC_PMAC */

3609 3610 3611
static void release_ohci(struct device *dev, void *data)
{
	struct pci_dev *pdev = to_pci_dev(dev);
3612
	struct fw_ohci *ohci = pci_get_drvdata(pdev);
3613 3614 3615

	pmac_ohci_off(pdev);

3616 3617 3618
	ar_context_release(&ohci->ar_response_ctx);
	ar_context_release(&ohci->ar_request_ctx);

3619 3620 3621
	dev_notice(dev, "removed fw-ohci device\n");
}

3622
static int pci_probe(struct pci_dev *dev,
3623
			       const struct pci_device_id *ent)
3624 3625
{
	struct fw_ohci *ohci;
3626
	u32 bus_options, max_receive, link_speed, version;
3627
	u64 guid;
3628
	int i, flags, irq, err;
3629 3630
	size_t size;

3631 3632 3633 3634 3635
	if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
		dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
		return -ENOSYS;
	}

3636 3637 3638
	ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL);
	if (ohci == NULL)
		return -ENOMEM;
3639
	fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3640
	pci_set_drvdata(dev, ohci);
3641
	pmac_ohci_on(dev);
3642
	devres_add(&dev->dev, ohci);
3643

3644
	err = pcim_enable_device(dev);
3645
	if (err) {
3646
		dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3647
		return err;
3648 3649 3650 3651 3652 3653
	}

	pci_set_master(dev);
	pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);

	spin_lock_init(&ohci->lock);
3654
	mutex_init(&ohci->phy_reg_mutex);
3655

3656
	INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3657

3658 3659
	if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
	    pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3660
		ohci_err(ohci, "invalid MMIO resource\n");
3661
		return -ENXIO;
3662 3663
	}

3664
	err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name);
3665
	if (err) {
3666 3667
		ohci_err(ohci, "request and map MMIO resource unavailable\n");
		return -ENXIO;
3668
	}
3669
	ohci->registers = pcim_iomap_table(dev)[0];
3670

3671
	for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3672 3673 3674 3675 3676
		if ((ohci_quirks[i].vendor == dev->vendor) &&
		    (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
		     ohci_quirks[i].device == dev->device) &&
		    (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
		     ohci_quirks[i].revision >= dev->revision)) {
3677 3678 3679
			ohci->quirks = ohci_quirks[i].flags;
			break;
		}
3680 3681
	if (param_quirks)
		ohci->quirks = param_quirks;
3682

3683 3684 3685
	if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev))
		ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ;

3686 3687 3688 3689 3690 3691 3692
	/*
	 * Because dma_alloc_coherent() allocates at least one page,
	 * we save space by using a common buffer for the AR request/
	 * response descriptors and the self IDs buffer.
	 */
	BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
	BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3693 3694
	ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus,
						GFP_KERNEL);
3695 3696
	if (!ohci->misc_buffer)
		return -ENOMEM;
3697 3698

	err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3699 3700
			      OHCI1394_AsReqRcvContextControlSet);
	if (err < 0)
3701
		return err;
3702

3703
	err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3704 3705
			      OHCI1394_AsRspRcvContextControlSet);
	if (err < 0)
3706
		return err;
3707

3708 3709 3710
	err = context_init(&ohci->at_request_ctx, ohci,
			   OHCI1394_AsReqTrContextControlSet, handle_at_packet);
	if (err < 0)
3711
		return err;
3712

3713 3714 3715
	err = context_init(&ohci->at_response_ctx, ohci,
			   OHCI1394_AsRspTrContextControlSet, handle_at_packet);
	if (err < 0)
3716
		return err;
3717 3718

	reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3719
	ohci->ir_context_channels = ~0ULL;
3720
	ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3721
	reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3722
	ohci->ir_context_mask = ohci->ir_context_support;
3723 3724
	ohci->n_ir = hweight32(ohci->ir_context_mask);
	size = sizeof(struct iso_context) * ohci->n_ir;
3725
	ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL);
3726 3727
	if (!ohci->ir_context_list)
		return -ENOMEM;
3728 3729

	reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3730
	ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3731 3732 3733 3734 3735
	/* JMicron JMB38x often shows 0 at first read, just ignore it */
	if (!ohci->it_context_support) {
		ohci_notice(ohci, "overriding IsoXmitIntMask\n");
		ohci->it_context_support = 0xf;
	}
3736
	reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3737
	ohci->it_context_mask = ohci->it_context_support;
3738 3739
	ohci->n_it = hweight32(ohci->it_context_mask);
	size = sizeof(struct iso_context) * ohci->n_it;
3740
	ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL);
3741 3742
	if (!ohci->it_context_list)
		return -ENOMEM;
3743

3744
	ohci->self_id     = ohci->misc_buffer     + PAGE_SIZE/2;
3745
	ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3746 3747 3748 3749 3750 3751 3752

	bus_options = reg_read(ohci, OHCI1394_BusOptions);
	max_receive = (bus_options >> 12) & 0xf;
	link_speed = bus_options & 0x7;
	guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
		reg_read(ohci, OHCI1394_GUIDLo);

3753
	flags = PCI_IRQ_INTX;
3754
	if (!(ohci->quirks & QUIRK_NO_MSI))
3755 3756 3757 3758
		flags |= PCI_IRQ_MSI;
	err = pci_alloc_irq_vectors(dev, 1, 1, flags);
	if (err < 0)
		return err;
3759 3760 3761 3762 3763
	irq = pci_irq_vector(dev, 0);
	if (irq < 0) {
		err = irq;
		goto fail_msi;
	}
3764

3765
	err = request_threaded_irq(irq, irq_handler, NULL,
3766 3767 3768
				   pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name,
				   ohci);
	if (err < 0) {
3769
		ohci_err(ohci, "failed to allocate interrupt %d\n", irq);
3770 3771 3772
		goto fail_msi;
	}

3773
	err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3774
	if (err)
3775
		goto fail_irq;
3776

3777
	version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3778 3779
	ohci_notice(ohci,
		    "added OHCI v%x.%x device as card %d, "
3780
		    "%d IR + %d IT contexts, quirks 0x%x%s\n",
3781
		    version >> 16, version & 0xff, ohci->card.index,
3782 3783
		    ohci->n_ir, ohci->n_it, ohci->quirks,
		    reg_read(ohci, OHCI1394_PhyUpperBound) ?
3784
			", physUB" : "");
3785

3786
	return 0;
3787

3788
 fail_irq:
3789
	free_irq(irq, ohci);
3790
 fail_msi:
3791
	pci_free_irq_vectors(dev);
3792

3793
	return err;
3794 3795 3796 3797
}

static void pci_remove(struct pci_dev *dev)
{
3798
	struct fw_ohci *ohci = pci_get_drvdata(dev);
3799
	int irq;
3800

3801 3802 3803 3804 3805 3806 3807 3808
	/*
	 * If the removal is happening from the suspend state, LPS won't be
	 * enabled and host registers (eg., IntMaskClear) won't be accessible.
	 */
	if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
		reg_write(ohci, OHCI1394_IntMaskClear, ~0);
		flush_writes(ohci);
	}
3809
	cancel_work_sync(&ohci->bus_reset_work);
3810 3811
	fw_core_remove_card(&ohci->card);

3812 3813 3814 3815
	/*
	 * FIXME: Fail all pending packets here, now that the upper
	 * layers can't queue any more.
	 */
3816 3817

	software_reset(ohci);
3818

3819 3820 3821
	irq = pci_irq_vector(dev, 0);
	if (irq >= 0)
		free_irq(irq, ohci);
3822
	pci_free_irq_vectors(dev);
3823

3824
	dev_notice(&dev->dev, "removing fw-ohci device\n");
3825 3826
}

3827
#ifdef CONFIG_PM
3828
static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3829
{
3830
	struct fw_ohci *ohci = pci_get_drvdata(dev);
3831 3832 3833
	int err;

	software_reset(ohci);
3834
	err = pci_save_state(dev);
3835
	if (err) {
3836
		ohci_err(ohci, "pci_save_state failed\n");
3837 3838
		return err;
	}
3839
	err = pci_set_power_state(dev, pci_choose_state(dev, state));
3840
	if (err)
3841
		ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3842
	pmac_ohci_off(dev);
3843

3844 3845 3846
	return 0;
}

3847
static int pci_resume(struct pci_dev *dev)
3848
{
3849
	struct fw_ohci *ohci = pci_get_drvdata(dev);
3850 3851
	int err;

3852
	pmac_ohci_on(dev);
3853 3854 3855
	pci_set_power_state(dev, PCI_D0);
	pci_restore_state(dev);
	err = pci_enable_device(dev);
3856
	if (err) {
3857
		ohci_err(ohci, "pci_enable_device failed\n");
3858 3859 3860
		return err;
	}

3861 3862 3863 3864 3865 3866 3867
	/* Some systems don't setup GUID register on resume from ram  */
	if (!reg_read(ohci, OHCI1394_GUIDLo) &&
					!reg_read(ohci, OHCI1394_GUIDHi)) {
		reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
		reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
	}

3868 3869 3870 3871 3872
	err = ohci_enable(&ohci->card, NULL, 0);
	if (err)
		return err;

	ohci_resume_iso_dma(ohci);
3873

3874
	return 0;
3875 3876 3877
}
#endif

3878
static const struct pci_device_id pci_table[] = {
3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889
	{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
	{ }
};

MODULE_DEVICE_TABLE(pci, pci_table);

static struct pci_driver fw_ohci_pci_driver = {
	.name		= ohci_driver_name,
	.id_table	= pci_table,
	.probe		= pci_probe,
	.remove		= pci_remove,
3890 3891 3892 3893
#ifdef CONFIG_PM
	.resume		= pci_resume,
	.suspend	= pci_suspend,
#endif
3894 3895
};

3896 3897
static int __init fw_ohci_init(void)
{
3898 3899 3900 3901
	selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
	if (!selfid_workqueue)
		return -ENOMEM;

3902 3903 3904 3905 3906 3907
	return pci_register_driver(&fw_ohci_pci_driver);
}

static void __exit fw_ohci_cleanup(void)
{
	pci_unregister_driver(&fw_ohci_pci_driver);
3908
	destroy_workqueue(selfid_workqueue);
3909 3910 3911 3912
}

module_init(fw_ohci_init);
module_exit(fw_ohci_cleanup);
Axel Lin's avatar
Axel Lin committed
3913

3914 3915 3916 3917
MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
MODULE_LICENSE("GPL");

3918 3919
/* Provide a module alias so root-on-sbp2 initrds don't break. */
MODULE_ALIAS("ohci1394");