• Russell King's avatar
    ARM: l2c: cns3xxx: remove cache size override · 24cb65fe
    Russell King authored
    The cache size should already be present in the L2 cache auxiliary
    control register: it is part of the integration process to configure
    the hardware IP.  Most platforms get this right, yet still many
    cargo-cult program, and assume that they always need specifying to
    the L2 cache code.  Remove them so we can find out which really need
    this.
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    24cb65fe
core.c 10.9 KB