• Maciej W. Rozycki's avatar
    MIPS: DECstation HRT calibration bug fixes · 8533966a
    Maciej W. Rozycki authored
    This change corrects DECstation HRT calibration, by removing the following
    bugs:
    
    1. Calibration period selection -- HZ / 10 has been chosen, however on
       DECstation computers, HZ never divides by 10, as the choice for HZ is
       among 128, 256 and 1024.  The choice therefore results in a systematic
       calibration error, e.g. 6.25% for the usual choice of 128 for HZ:
    
       128 / 10 * 10 = 120
    
       (128 - 120) / 128 -> 6.25%
    
       The change therefore makes calibration use HZ / 8 that is always
       accurate for the HZ values available, getting rid of the systematic
       error.
    
    2. Calibration starting point synchronisation -- the duration of a number
       of intervals between DS1287A periodic interrupt assertions is measured,
       however code does not ensure at the beginning that the interrupt has
       not been previously asserted.  This results in a variable error of e.g.
       up to another 6.25% for the period of HZ / 8 (8.(3)% with the original
       HZ / 10 period) and the usual choice of 128 for HZ:
    
       1 / 16 -> 6.25%
    
       1 / 12 -> 8.(3)%
    
       The change therefore adds an initial call to ds1287_timer_state that
       clears any previous periodic interrupt pending.
    
    The same issue applies to both I/O ASIC counter and R4k CP0 timer
    calibration on DECstation systems as similar code is used in both cases
    and both pieces of code are covered by this fix.
    
    On an R3400 test system used this fix results in a change of the I/O ASIC
    clock frequency reported from values like:
    
    I/O ASIC clock frequency 23185830Hz
    
    to:
    
    I/O ASIC clock frequency 24999288Hz
    
    removing the miscalculation by 6.25% from the systematic error and (for
    the individual sample provided) a further 1.00% from the variable error,
    accordingly.  The nominal I/O ASIC clock frequency is 25MHz on this
    system.
    
    Here's another result, with the fix applied, from a system that has both
    HRTs available (using an R4400 at 60MHz nominal):
    
    MIPS counter frequency 59999328Hz
    I/O ASIC clock frequency 24999432Hz
    Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/5807/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    8533966a
csrc-ioasic.c 1.73 KB