• Kees Cook's avatar
    x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup · 7a313666
    Kees Cook authored
    Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
    XD_DISABLE bit) when resuming from S3, which can interact poorly with
    ebba638a. In 32bit PAE mode, this can
    lead to a fault when EFER is restored by the kernel wakeup routines,
    due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
    now incorrectly thinks it lacks the NX feature. (64bit is not affected
    because it uses a common CPU bring-up that specifically handles the
    XD_DISABLE bit.)
    
    The need for MISC_ENABLE being restored so early is specific to the S3
    resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
    but this happens after the resume header is created, so just reproduce
    the logic here. (acpi_suspend_lowlevel() creates the header, calls
    do_suspend_lowlevel, which calls save_processor_state(), so the saved
    processor context isn't available during resume header creation.)
    
    [ hpa: Consider for stable if OK in mainline ]
    Signed-off-by: default avatarKees Cook <kees.cook@canonical.com>
    Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.netSigned-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
    Cc: Rafael J. Wysocki <rjw@sisk.pl>
    Cc: <stable@kernel.org> 2.6.38+
    7a313666
sleep.c 3.68 KB