Commit 0015edd6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk driver updates from Stephen Boyd:
 "A pile of clk driver updates with a small tracepoint patch to the clk
  core this time around.

  The core framework is effectively unchanged, with the majority of the
  diff going to the Qualcomm clk driver directory because they added two
  3k line files that are almost all clk data (Abel Vesa from Linaro
  tried to shrink the number of lines down, but it doesn't seem to be
  possible without sacrificing readability).

  The second big driver this time around is the Rockchip rk3588 clk and
  reset unit, at _only_ 2.5k lines.

  Ignoring the big clk drivers from the familiar SoC vendors, there's
  just a bunch of little clk driver updates and fixes throughout here.

  It's the usual set of clk data fixups to describe proper parents, or
  add frequencies to frequency tables, or plug memory leaks when
  function calls fail. Also, some drivers are converted to use modern
  clk_hw APIs, which is always nice to see. And data is deduplicated,
  leading to a smaller kernel Image.

  Overall this batch has a larger collection of cleanups than it
  typically does. Maybe that means there are less new SoCs right now
  that need supporting, and the focus has shifted to quality and
  reliability. I can dream.

  New Drivers:
   - Frequency hopping controller hardware on MediaTek MT8186
   - Global clock controller for Qualcomm SM8550
   - Display clock controller for Qualcomm SC8280XP
   - RPMh clock controller for Qualcomm QDU1000 and QRU1000 SoCs
   - CPU PLL on MStar/SigmaStar SoCs
   - Support for the clock and reset unit of the Rockchip rk3588

  Updates:
   - Tracepoints for clk_rate_request structures
   - Debugfs support for fractional divider clk
   - Make MxL's CGU driver secure compatible
   - Ingenic JZ4755 SoC clk support
   - Support audio clks on X1000 SoCs
   - Remove flags from univ/main/syspll child fixed factor clocks across
     MediaTek platforms
   - Fix clock dependency for ADC on MediaTek MT7986
   - Fix parent for FlexSPI clock for i.MX93
   - Add USB suspend clock on i.MX8MP
   - Unmap anatop base on error for i.MX93 driver
   - Change enet clock parent to wakeup_axi_root for i.MX93
   - Drop LPIT1, LPIT2, TPM1 and TPM3 clocks for i.MX93
   - Mark HSIO bus clock and SYS_CNT clock as critical on i.MX93
   - Add 320MHz and 640MHz entries to PLL146x
   - Add audio shared gate and SAI clocks for i.MX8MP
   - Fix a possible memory leak in the error path of rockchip PLL
     creation
   - Fix header guard for V3S clocks
   - Add IR module clock for f1c100s
   - Correct the parent clocks for the (High Speed) Serial Communication
     Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
     Switch clocks on Renesas R-Car S4-8
   - Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on Renesas
     R-Car V4H
   - Two PLL driver fixups for the Amlogic clk driver
   - Round SD clock rate to improve parent clock selection
   - Add Ethernet Switch and internal SASYNCPER clocks on Renesas R-Car
     S4-8
   - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX)
     serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI
     (RPC-IF) clocks on Renesas R-Car V4H
   - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
     Renesas RZ/G2L
   - Fix endless loop on Renesas RZ/N1
   - Correct the parent clocks for the High Speed Serial Communication
     Interfaces with FIFO (HSCIF) modules on the Renesas R-Car V4H SoC
     Note: HSCIF0 is used for the serial console on the White-Hawk
     development board
   - Various clk DT binding improvements and conversions to YAML
   - Qualcomm SM8150/SM8250 display clock controller cleaned up
   - Some missing clocks for Qualcomm SM8350 added
   - Qualcomm MSM8974 Global and Multimedia clock controllers
     transitioned to parent_data and parent_hws
   - Use parent_data and add network resets for Qualcomm IPQ8074
   - Qualcomm Krait clock controller modernized
   - Fix pm_runtime usage in Qualcomm SC7180 and SC7280 LPASS clock
     controllers
   - Enable retention mode on Qualcomm SM8250 USB GDSCs
   - Cleanup Qualcomm RPM and RPMh clock drivers to avoid duplicating
     clocks which definition could be shared between platforms
   - Various NULL pointer checks added for allocations"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (188 commits)
  clk: nomadik: correct struct name kernel-doc warning
  clk: lmk04832: fix kernel-doc warnings
  clk: lmk04832: drop superfluous #include
  clk: lmk04832: drop unnecessary semicolons
  clk: lmk04832: declare variables as const when possible
  clk: socfpga: Fix memory leak in socfpga_gate_init()
  clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
  clk: st: Fix memory leak in st_of_quadfs_setup()
  clk: samsung: Fix memory leak in _samsung_clk_register_pll()
  clk: Add trace events for rate requests
  clk: Store clk_core for clk_rate_request
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  ...
parents 71946a25 0e2c9884
......@@ -22,6 +22,7 @@ select:
enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
- ingenic,jz4755-cgu
- ingenic,jz4760-cgu
- ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
......@@ -51,6 +52,7 @@ properties:
- enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
- ingenic,jz4755-cgu
- ingenic,jz4760-cgu
- ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
......
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek frequency hopping and spread spectrum clocking control
maintainers:
- Edward-JW Yang <edward-jw.yang@mediatek.com>
description: |
Frequency hopping control (FHCTL) is a piece of hardware that control
some PLLs to adopt "hopping" mechanism to adjust their frequency.
Spread spectrum clocking (SSC) is another function provided by this hardware.
properties:
compatible:
const: mediatek,mt8186-fhctl
reg:
maxItems: 1
clocks:
description: Phandles of the PLL with FHCTL hardware capability.
minItems: 1
maxItems: 30
mediatek,hopping-ssc-percent:
description: The percentage of spread spectrum clocking for one PLL.
minItems: 1
maxItems: 30
items:
default: 0
minimum: 0
maximum: 8
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8186-clk.h>
fhctl: fhctl@1000ce00 {
compatible = "mediatek,mt8186-fhctl";
reg = <0x1000ce00 0x200>;
clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
mediatek,hopping-ssc-percent = <3>;
};
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A53 PLL Binding
title: Qualcomm A53 PLL clock
maintainers:
- Bjorn Andersson <andersson@kernel.org>
......
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A7 PLL Binding
title: Qualcomm A7 PLL clock
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
......
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs
title: LPASS Always ON Clock Controller on SM8250 SoCs
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
......@@ -17,7 +17,7 @@ description: |
properties:
compatible:
const: qcom,sm8250-lpass-aon
const: qcom,sm8250-lpass-aoncc
reg:
maxItems: 1
......@@ -28,11 +28,13 @@ properties:
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio codec voting clock
- description: Glitch Free Mux register clock
clock-names:
items:
- const: core
- const: audio
- const: bus
required:
......@@ -50,9 +52,10 @@ examples:
#include <dt-bindings/sound/qcom,q6afe.h>
clock-controller@3800000 {
#clock-cells = <1>;
compatible = "qcom,sm8250-lpass-aon";
compatible = "qcom,sm8250-lpass-aoncc";
reg = <0x03380000 0x40000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "bus";
clock-names = "core", "audio", "bus";
};
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs
title: LPASS Audio Clock Controller on SM8250 SoCs
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
......@@ -28,11 +28,13 @@ properties:
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio codec voting clock
- description: Glitch Free Mux register clock
clock-names:
items:
- const: core
- const: audio
- const: bus
required:
......@@ -53,6 +55,7 @@ examples:
compatible = "qcom,sm8250-lpass-audiocc";
reg = <0x03300000 0x30000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "bus";
clock-names = "core", "audio", "bus";
};
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
title: Qualcomm Camera Clock & Reset Controller on SM8250
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8250.
See also dt-bindings/clock/qcom,camcc-sm8250.h
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
properties:
compatible:
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains for the two MDSS instances on SC8280XP.
See also:
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
properties:
compatible:
enum:
- qcom,sc8280xp-dispcc0
- qcom,sc8280xp-dispcc1
clocks:
items:
- description: AHB interface clock,
- description: SoC CXO clock
- description: SoC sleep clock
- description: DisplayPort 0 link clock
- description: DisplayPort 0 VCO div clock
- description: DisplayPort 1 link clock
- description: DisplayPort 1 VCO div clock
- description: DisplayPort 2 link clock
- description: DisplayPort 2 VCO div clock
- description: DisplayPort 3 link clock
- description: DisplayPort 3 VCO div clock
- description: DSI 0 PLL byte clock
- description: DSI 0 PLL DSI clock
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
items:
- description: MMCX power domain
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@af00000 {
compatible = "qcom,sc8280xp-dispcc0";
reg = <0x0af00000 0x20000>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&mdss0_dp_phy0 0>,
<&mdss0_dp_phy0 1>,
<&mdss0_dp_phy1 0>,
<&mdss0_dp_phy1 1>,
<&mdss0_dp_phy2 0>,
<&mdss0_dp_phy2 1>,
<&mdss0_dp_phy3 0>,
<&mdss0_dp_phy3 1>,
<&mdss0_dsi0_phy 0>,
<&mdss0_dsi0_phy 1>,
<&mdss0_dsi1_phy 0>,
<&mdss0_dsi1_phy 1>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock Controller Binding for SM6125
title: Qualcomm Display Clock Controller on SM6125
maintainers:
- Martin Botka <martin.botka@somainline.org>
description: |
Qualcomm display clock control module which supports the clocks and
power domains on SM6125.
Qualcomm display clock control module provides the clocks and power domains
on SM6125.
See also:
dt-bindings/clock/qcom,dispcc-sm6125.h
See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
properties:
compatible:
......
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM6350
title: Qualcomm Display Clock & Reset Controller on SM6350
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM6350.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6350.
See also dt-bindings/clock/qcom,dispcc-sm6350.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
properties:
compatible:
......
......@@ -4,19 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8150/SM8250/SM8350.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8150/SM8250/SM8350.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
dt-bindings/clock/qcom,dispcc-sm8350.h
See also::
include/dt-bindings/clock/qcom,dispcc-sm8150.h
include/dt-bindings/clock/qcom,dispcc-sm8250.h
include/dt-bindings/clock/qcom,dispcc-sm8350.h
properties:
compatible:
......
......@@ -4,22 +4,22 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
allOf:
- $ref: qcom,gcc.yaml#
title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on APQ8064.
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8064.
See also:
- dt-bindings/clock/qcom,gcc-msm8960.h
- dt-bindings/reset/qcom,gcc-msm8960.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8960.h
include/dt-bindings/reset/qcom,gcc-msm8960.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
......
......@@ -4,19 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
title: Qualcomm Global Clock & Reset Controller on APQ8084
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on APQ8084.
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8084.
See also::
- dt-bindings/clock/qcom,gcc-apq8084.h
- dt-bindings/reset/qcom,gcc-apq8084.h
include/dt-bindings/clock/qcom,gcc-apq8084.h
include/dt-bindings/reset/qcom,gcc-apq8084.h
allOf:
- $ref: qcom,gcc.yaml#
......
......@@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
allOf:
- $ref: qcom,gcc.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ8064
maintainers:
- Ansuel Smith <ansuelsmth@gmail.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on IPQ8064.
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8064.
See also:
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
See also::
include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
......@@ -27,14 +27,18 @@ properties:
- const: syscon
clocks:
minItems: 2
items:
- description: PXO source
- description: CXO source
- description: PLL4 from LCC
clock-names:
minItems: 2
items:
- const: pxo
- const: cxo
- const: pll4
thermal-sensor:
type: object
......@@ -51,13 +55,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064", "syscon";
reg = <0x00900000 0x4000>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
clock-names = "pxo", "cxo", "pll4";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
......
......@@ -4,47 +4,39 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
title: Qualcomm Global Clock & Reset Controller on IPQ8074
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on IPQ8074.
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8074.
See also:
- dt-bindings/clock/qcom,gcc-ipq8074.h
See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq8074
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
clocks:
items:
- description: board XO clock
- description: sleep clock
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- reg
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |
......
......@@ -4,22 +4,22 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
title: Qualcomm Global Clock & Reset Controller on MSM8660
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks and resets on
Qualcomm global clock control module provides the clocks and resets on
MSM8660
See also:
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8660.h
include/dt-bindings/reset/qcom,gcc-msm8660.h
allOf:
- $ref: "qcom,gcc.yaml#"
- $ref: qcom,gcc.yaml#
properties:
compatible:
......
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
title: Qualcomm Global Clock & Reset Controller on MSM8909
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8909.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8909.
See also:
- dt-bindings/clock/qcom,gcc-msm8909.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
properties:
compatible:
......
......@@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8916 or MSM8939.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8916 or MSM8939.
See also:
- dt-bindings/clock/qcom,gcc-msm8916.h
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/reset/qcom,gcc-msm8916.h
- dt-bindings/reset/qcom,gcc-msm8939.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8916.h
include/dt-bindings/clock/qcom,gcc-msm8939.h
include/dt-bindings/reset/qcom,gcc-msm8916.h
include/dt-bindings/reset/qcom,gcc-msm8939.h
properties:
compatible:
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8974 (all variants) and MSM8226.
See also::
include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
$ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,gcc-msm8226
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@fc400000 {
compatible = "qcom,gcc-msm8974";
reg = <0x00100000 0x94000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>,
<&sleep_clk>;
};
...
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
title: Qualcomm Global Clock & Reset Controller on MSM8976
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8976.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8976.
See also:
- dt-bindings/clock/qcom,gcc-msm8976.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
properties:
compatible:
......
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