Commit 0d622143 authored by David S. Miller's avatar David S. Miller

Merge branch 'net-dsa-mt7530-PHYLINK-and-port-5'

René van Dorst says:

====================
net: dsa: mt7530: Convert to PHYLINK and add support for port 5

1. net: dsa: mt7530: Convert to PHYLINK API
   This patch converts mt7530 to PHYLINK API.
2. dt-bindings: net: dsa: mt7530: Add support for port 5
3. net: dsa: mt7530: Add support for port 5
   These 2 patches adding support for port 5 of the switch.

v2->v3:
 * Removed 'status = "okay"' lines in patch #2
 * Change a port 5 setup message in a debug message in patch #3
 * Added ack-by and tested-by tags
v1->v2:
 * Mostly phylink improvements after review.
rfc -> v1:
 * Mostly phylink improvements after review.
 * Drop phy isolation patches. Adds no value for now.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 771efeda 38f790a8
...@@ -35,6 +35,42 @@ Required properties for the child nodes within ports container: ...@@ -35,6 +35,42 @@ Required properties for the child nodes within ports container:
- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled - phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
"cpu". "cpu".
Port 5 of the switch is muxed between:
1. GMAC5: GMAC5 can interface with another external MAC or PHY.
2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
of the SOC. Used in many setups where port 0/4 becomes the WAN port.
Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
connected to external component!
Port 5 modes/configurations:
1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
GMAC of the SOC.
In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
and RGMII delay.
3. Port 5 is muxed to GMAC5 and can interface to an external phy.
Port 5 becomes an extra switch port.
Only works on platform where external phy TX<->RX lines are swapped.
Like in the Ubiquiti ER-X-SFP.
4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
Currently a 2nd CPU port is not supported by DSA code.
Depending on how the external PHY is wired:
1. normal: The PHY can only connect to 2nd GMAC but not to the switch
2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
a ethernet port. But can't interface to the 2nd GMAC.
Based on the DT the port 5 mode is configured.
Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
phy-mode must be set, see also example 2 below!
* mt7621: phy-mode = "rgmii-txid";
* mt7623: phy-mode = "rgmii";
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required, optional properties and how the integrated switch subnodes must required, optional properties and how the integrated switch subnodes must
be specified. be specified.
...@@ -94,3 +130,181 @@ Example: ...@@ -94,3 +130,181 @@ Example:
}; };
}; };
}; };
Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
&eth {
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii-txid";
phy-handle = <&phy4>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
/* Internal phy */
phy4: ethernet-phy@4 {
reg = <4>;
};
mt7530: switch@1f {
compatible = "mediatek,mt7621";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1f>;
pinctrl-names = "default";
mediatek,mcm;
resets = <&rstctrl 2>;
reset-names = "mcm";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
/* Commented out. Port 4 is handled by 2nd GMAC.
port@4 {
reg = <4>;
label = "lan4";
};
*/
cpu_port0: port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};
Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
&eth {
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
/* External phy */
ephy5: ethernet-phy@7 {
reg = <7>;
};
mt7530: switch@1f {
compatible = "mediatek,mt7621";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1f>;
pinctrl-names = "default";
mediatek,mcm;
resets = <&rstctrl 2>;
reset-names = "mcm";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
label = "lan5";
phy-mode = "rgmii";
phy-handle = <&ephy5>;
};
cpu_port0: port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};
This diff is collapsed.
...@@ -186,6 +186,7 @@ enum mt7530_vlan_port_attr { ...@@ -186,6 +186,7 @@ enum mt7530_vlan_port_attr {
/* Register for port MAC control register */ /* Register for port MAC control register */
#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
#define PMCR_EXT_PHY BIT(17)
#define PMCR_MAC_MODE BIT(16) #define PMCR_MAC_MODE BIT(16)
#define PMCR_FORCE_MODE BIT(15) #define PMCR_FORCE_MODE BIT(15)
#define PMCR_TX_EN BIT(14) #define PMCR_TX_EN BIT(14)
...@@ -198,26 +199,20 @@ enum mt7530_vlan_port_attr { ...@@ -198,26 +199,20 @@ enum mt7530_vlan_port_attr {
#define PMCR_FORCE_SPEED_100 BIT(2) #define PMCR_FORCE_SPEED_100 BIT(2)
#define PMCR_FORCE_FDX BIT(1) #define PMCR_FORCE_FDX BIT(1)
#define PMCR_FORCE_LNK BIT(0) #define PMCR_FORCE_LNK BIT(0)
#define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ PMCR_FORCE_SPEED_1000)
PMCR_TX_EN | PMCR_RX_EN | \
PMCR_TX_FC_EN | PMCR_RX_FC_EN)
#define PMCR_CPUP_LINK (PMCR_COMMON_LINK | PMCR_FORCE_MODE | \
PMCR_FORCE_SPEED_1000 | \
PMCR_FORCE_FDX | \
PMCR_FORCE_LNK)
#define PMCR_USERP_LINK PMCR_COMMON_LINK
#define PMCR_FIXED_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
PMCR_FORCE_MODE | PMCR_TX_EN | \
PMCR_RX_EN | PMCR_BACKPR_EN | \
PMCR_BACKOFF_EN | \
PMCR_FORCE_SPEED_1000 | \
PMCR_FORCE_FDX | \
PMCR_FORCE_LNK)
#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
PMCR_TX_FC_EN | PMCR_RX_FC_EN)
#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
#define PMSR_EEE1G BIT(7)
#define PMSR_EEE100M BIT(6)
#define PMSR_RX_FC BIT(5)
#define PMSR_TX_FC BIT(4)
#define PMSR_SPEED_1000 BIT(3)
#define PMSR_SPEED_100 BIT(2)
#define PMSR_SPEED_10 0x00
#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
#define PMSR_DPX BIT(1)
#define PMSR_LINK BIT(0)
/* Register for MIB */ /* Register for MIB */
#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
...@@ -251,6 +246,7 @@ enum mt7530_vlan_port_attr { ...@@ -251,6 +246,7 @@ enum mt7530_vlan_port_attr {
/* Register for hw trap modification */ /* Register for hw trap modification */
#define MT7530_MHWTRAP 0x7804 #define MT7530_MHWTRAP 0x7804
#define MHWTRAP_PHY0_SEL BIT(20)
#define MHWTRAP_MANUAL BIT(16) #define MHWTRAP_MANUAL BIT(16)
#define MHWTRAP_P5_MAC_SEL BIT(13) #define MHWTRAP_P5_MAC_SEL BIT(13)
#define MHWTRAP_P6_DIS BIT(8) #define MHWTRAP_P6_DIS BIT(8)
...@@ -408,6 +404,30 @@ struct mt7530_port { ...@@ -408,6 +404,30 @@ struct mt7530_port {
u16 pvid; u16 pvid;
}; };
/* Port 5 interface select definitions */
enum p5_interface_select {
P5_DISABLED = 0,
P5_INTF_SEL_PHY_P0,
P5_INTF_SEL_PHY_P4,
P5_INTF_SEL_GMAC5,
};
static const char *p5_intf_modes(unsigned int p5_interface)
{
switch (p5_interface) {
case P5_DISABLED:
return "DISABLED";
case P5_INTF_SEL_PHY_P0:
return "PHY P0";
case P5_INTF_SEL_PHY_P4:
return "PHY P4";
case P5_INTF_SEL_GMAC5:
return "GMAC5";
default:
return "unknown";
}
}
/* struct mt7530_priv - This is the main data structure for holding the state /* struct mt7530_priv - This is the main data structure for holding the state
* of the driver * of the driver
* @dev: The device pointer * @dev: The device pointer
...@@ -423,6 +443,8 @@ struct mt7530_port { ...@@ -423,6 +443,8 @@ struct mt7530_port {
* @ports: Holding the state among ports * @ports: Holding the state among ports
* @reg_mutex: The lock for protecting among process accessing * @reg_mutex: The lock for protecting among process accessing
* registers * registers
* @p6_interface Holding the current port 6 interface
* @p5_intf_sel: Holding the current port 5 interface select
*/ */
struct mt7530_priv { struct mt7530_priv {
struct device *dev; struct device *dev;
...@@ -435,6 +457,9 @@ struct mt7530_priv { ...@@ -435,6 +457,9 @@ struct mt7530_priv {
struct gpio_desc *reset; struct gpio_desc *reset;
unsigned int id; unsigned int id;
bool mcm; bool mcm;
phy_interface_t p6_interface;
phy_interface_t p5_interface;
unsigned int p5_intf_sel;
struct mt7530_port ports[MT7530_NUM_PORTS]; struct mt7530_port ports[MT7530_NUM_PORTS];
/* protect among processes for registers access*/ /* protect among processes for registers access*/
......
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