Skip to content

L
linux
Commit 1c2de3e7 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files
Options

Merge git://git.kernel.org/pub/scm/linux/kernel/git/lwfinger/r8192E into staging-next 

* git://git.kernel.org/pub/scm/linux/kernel/git/lwfinger/r8192E: (166 commits)
  staging: rtl8192e: Remove files that are not used
  staging: rtl8192e: Convert typedefs that can be replaced with #define
  staging: rtl8192e: Convert typedef HT_AGGRE_SIZE_E to enum ht_aggre_size
  staging: rtl8192e: Convert typedef RATR_TABLE_MODE_8192S to enum ratr_table_mode_8192s
  staging: rtl8192e: Convert typedef FW_CMD_IO_TYPE to enum fw_cmd_io_type
  staging: rtl8192e: Convert typedef SCAN_OPERATION_BACKUP_OPT to enum scan_op_backup_opt
  staging: rtl8192e: Convert typedef country_code_type_t to enum country_code_type
  staging: rtl8192e: Convert typedef WOLPATTERN_TYPE to enum wol_pattern_type
  staging: rtl8192e: Convert typedef RT_RF_POWER_STATE to enum rt_rf_power_state
  staging: rtl8192e: Convert typedef RT_JOIN_ACTION to enum rt_join_action
  staging: rtl8192e: Convert typedef IPS_CALLBACK_FUNCION to enum ips_callback_function
  staging: rtl8192e: Convert typedef RT_PS_MODE to enum rt_ps_mode
  staging: rtl8192e: Convert typedef Fsync_State to enum fsync_state
  staging: rtl8192e: Convert typedef erp_t to enum erp_t
  staging: rtl8192e: Convert typedef WIRELESS_NETWORK_TYPE to enum wireless_network_type
  staging: rtl8192e: Convert typedef WIRELESS_MODE to enum wireless_mode
  staging: rtl8192e: Convert typedef RT_RF_TYPE_DEF to enum rt_rf_type_def
  staging: rtl8192e: Convert typedef LED_CTL_MODE to enum led_ctl_mode
  staging: rtl8192e: Convert typedef InitialGainOpType to enum init_gain_op_type
  staging: rtl8192e: Convert typedef BA_ACTION to enum ba_action
  ...
parents 1ec3ba93 09505184
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 914 additions and 30448 deletions
drivers/staging/rtl8192e/internal.h deleted 100644 → 0
View file @ 1ec3ba93
/*
* Cryptographic API.
*
* Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_INTERNAL_H
#define _CRYPTO_INTERNAL_H
#include <linux/version.h>
#include "rtl_crypto.h"
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/init.h>
#include <linux/hardirq.h>
#include <linux/sched.h>
#include <asm/kmap_types.h>
extern enum km_type crypto_km_types[];
static inline enum km_type crypto_kmap_type(int out)
{
return crypto_km_types[(in_softirq() ? 2 : 0) + out];
}
static inline void *crypto_kmap(struct page *page, int out)
{
return kmap_atomic(page, crypto_kmap_type(out));
}
static inline void crypto_kunmap(void *vaddr, int out)
{
kunmap_atomic(vaddr, crypto_kmap_type(out));
}
static inline void crypto_yield(struct crypto_tfm *tfm)
{
if (!in_softirq())
cond_resched();
}
static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm)
{
return (void *)&tfm[1];
}
struct crypto_alg *crypto_alg_lookup(const char *name);
#ifdef CONFIG_KMOD
void crypto_alg_autoload(const char *name);
struct crypto_alg *crypto_alg_mod_lookup(const char *name);
#else
static inline struct crypto_alg *crypto_alg_mod_lookup(const char *name)
{
return crypto_alg_lookup(name);
}
#endif
static inline int crypto_alloc_hmac_block(struct crypto_tfm *tfm)
{
return 0;
}
static inline void crypto_free_hmac_block(struct crypto_tfm *tfm)
{ }
#ifdef CONFIG_PROC_FS
void __init crypto_init_proc(void);
#else
static inline void crypto_init_proc(void)
{ }
#endif
int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_digest_ops(struct crypto_tfm *tfm);
int crypto_init_cipher_ops(struct crypto_tfm *tfm);
int crypto_init_compress_ops(struct crypto_tfm *tfm);
void crypto_exit_digest_ops(struct crypto_tfm *tfm);
void crypto_exit_cipher_ops(struct crypto_tfm *tfm);
void crypto_exit_compress_ops(struct crypto_tfm *tfm);
#endif /* _CRYPTO_INTERNAL_H */
drivers/staging/rtl8192e/kmap_types.h deleted 100644 → 0
View file @ 1ec3ba93
#ifndef __KMAP_TYPES_H
#define __KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_SUNRPC_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BH_IRQ,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_TYPE_NR
};
#define _ASM_KMAP_TYPES_H
#endif
drivers/staging/rtl8192e/r8180_93cx6.c deleted 100644 → 0
View file @ 1ec3ba93
/*
This files contains card eeprom (93c46 or 93c56) programming routines,
memory is addressed by 16 bits words.
This is part of rtl8180 OpenSource driver.
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
Parts of this driver are based on the GPL part of the
official realtek driver.
Parts of this driver are based on the rtl8180 driver skeleton
from Patric Schenke & Andres Salomon.
Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
We want to tanks the Authors of those projects and the Ndiswrapper
project Authors.
*/
#include "r8180_93cx6.h"
static void eprom_cs(struct r8192_priv *priv, short bit)
{
if (bit)
write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CS_SHIFT) |
read_nic_byte(priv, EPROM_CMD)); //enable EPROM
else
write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_CS_SHIFT)); //disable EPROM
udelay(EPROM_DELAY);
}
static void eprom_ck_cycle(struct r8192_priv *priv)
{
write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CK_SHIFT) | read_nic_byte(priv, EPROM_CMD));
udelay(EPROM_DELAY);
write_nic_byte(priv, EPROM_CMD,
read_nic_byte(priv, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
udelay(EPROM_DELAY);
}
static void eprom_w(struct r8192_priv *priv, short bit)
{
if (bit)
write_nic_byte(priv, EPROM_CMD, (1<<EPROM_W_SHIFT) |
read_nic_byte(priv, EPROM_CMD));
else
write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_W_SHIFT));
udelay(EPROM_DELAY);
}
static short eprom_r(struct r8192_priv *priv)
{
short bit;
bit = (read_nic_byte(priv, EPROM_CMD) & (1<<EPROM_R_SHIFT));
udelay(EPROM_DELAY);
if (bit)
return 1;
return 0;
}
static void eprom_send_bits_string(struct r8192_priv *priv, short b[], int len)
{
int i;
for (i = 0; i < len; i++) {
eprom_w(priv, b[i]);
eprom_ck_cycle(priv);
}
}
u32 eprom_read(struct r8192_priv *priv, u32 addr)
{
short read_cmd[] = {1, 1, 0};
short addr_str[8];
int i;
int addr_len;
u32 ret;
ret = 0;
//enable EPROM programming
write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
udelay(EPROM_DELAY);
if (priv->epromtype == EPROM_93c56) {
addr_str[7] = addr & 1;
addr_str[6] = addr & (1<<1);
addr_str[5] = addr & (1<<2);
addr_str[4] = addr & (1<<3);
addr_str[3] = addr & (1<<4);
addr_str[2] = addr & (1<<5);
addr_str[1] = addr & (1<<6);
addr_str[0] = addr & (1<<7);
addr_len = 8;
} else {
addr_str[5] = addr & 1;
addr_str[4] = addr & (1<<1);
addr_str[3] = addr & (1<<2);
addr_str[2] = addr & (1<<3);
addr_str[1] = addr & (1<<4);
addr_str[0] = addr & (1<<5);
addr_len = 6;
}
eprom_cs(priv, 1);
eprom_ck_cycle(priv);
eprom_send_bits_string(priv, read_cmd, 3);
eprom_send_bits_string(priv, addr_str, addr_len);
//keep chip pin D to low state while reading.
//I'm unsure if it is necessary, but anyway shouldn't hurt
eprom_w(priv, 0);
for (i = 0; i < 16; i++) {
//eeprom needs a clk cycle between writing opcode&adr
//and reading data. (eeprom outs a dummy 0)
eprom_ck_cycle(priv);
ret |= (eprom_r(priv)<<(15-i));
}
eprom_cs(priv, 0);
eprom_ck_cycle(priv);
//disable EPROM programming
write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
return ret;
}
drivers/staging/rtl8192e/r8180_93cx6.h deleted 100644 → 0
View file @ 1ec3ba93
/* r8180_93cx6.h - 93c46 or 93c56 eeprom card programming routines
*
* This is part of rtl8187 OpenSource driver
* Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
* Released under the terms of GPL (General Public Licence)
* Parts of this driver are based on the GPL part of the official realtek driver
*
* Parts of this driver are based on the rtl8180 driver skeleton from
* Patric Schenke & Andres Salomon.
*
* Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
*
* We want to thank the authors of the above mentioned projects and to
* the authors of the Ndiswrapper project.
*/
#include "r8192E.h"
#include "r8192E_hw.h"
#define EPROM_DELAY 10
#define EPROM_ANAPARAM_ADDRLWORD 0xd
#define EPROM_ANAPARAM_ADDRHWORD 0xe
#define EPROM_RFCHIPID 0x6
#define EPROM_TXPW_BASE 0x05
#define EPROM_RFCHIPID_RTL8225U 5
#define EPROM_RF_PARAM 0x4
#define EPROM_CONFIG2 0xc
#define EPROM_VERSION 0x1E
#define MAC_ADR 0x7
#define CIS 0x18
#define EPROM_TXPW0 0x16
#define EPROM_TXPW2 0x1b
#define EPROM_TXPW1 0x3d
/* Reads a 16 bits word. */
u32 eprom_read(struct r8192_priv *priv, u32 addr);
drivers/staging/rtl8192e/r8190P_def.h
View file @ 1c2de3e7
......@@ -29,12 +29,12 @@
#define RX_CMD_QUEUE 1
typedef enum _rtl819x_loopback{
enum rtl819x_loopback {
RTL819X_NO_LOOPBACK = 0,
RTL819X_MAC_LOOPBACK = 1,
RTL819X_DMA_LOOPBACK = 2,
RTL819X_CCK_LOOPBACK = 3,
}rtl819x_loopback_e;
};
#define RESET_DELAY_8185 20
......@@ -129,37 +129,35 @@ typedef enum _rtl819x_loopback{
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
typedef enum _VERSION_8190{
enum version_8190_loopback {
VERSION_8190_BD=0x3,
VERSION_8190_BE
}VERSION_8190,*PVERSION_8190;
};
#define IC_VersionCut_C 0x2
#define IC_VersionCut_D 0x3
#define IC_VersionCut_E 0x4
typedef enum tag_Rf_OpType
{
enum rf_optype {
RF_OP_By_SW_3wire = 0,
RF_OP_By_FW,
RF_OP_MAX
}RF_OpType_E;
};
typedef enum _POWER_SAVE_MODE
{
enum power_save_mode {
POWER_SAVE_MODE_ACTIVE,
POWER_SAVE_MODE_SAVE,
}POWER_SAVE_MODE;
};
typedef enum _INTERFACE_SELECT_8190PCI{
enum interface_select_8190pci {
INTF_SEL1_MINICARD = 0,
INTF_SEL0_PCIE = 1,
INTF_SEL2_RSV = 2,
INTF_SEL3_RSV = 3,
} INTERFACE_SELECT_8190PCI, *PINTERFACE_SELECT_8190PCI;
};
typedef struct _BB_REGISTER_DEFINITION{
struct bb_reg_definition {
u32 rfintfs;
u32 rfintfi;
u32 rfintfo;
......@@ -178,9 +176,9 @@ typedef struct _BB_REGISTER_DEFINITION{
u32 rfTxAFE;
u32 rfLSSIReadBack;
u32 rfLSSIReadBackPi;
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
};
typedef struct _TX_FWINFO_STRUCUTRE{
struct tx_fwinfo {
u8 TxRate:7;
u8 CtsEnable:1;
u8 RtsRate:7;
......@@ -205,9 +203,9 @@ typedef struct _TX_FWINFO_STRUCUTRE{
u32 TxAGCSign:1;
u32 Tx_INFO_RSVD:6;
u32 PacketID:13;
}TX_FWINFO_T;
};
typedef struct _TX_FWINFO_8190PCI{
struct tx_fwinfo_8190pci {
u8 TxRate:7;
u8 CtsEnable:1;
u8 RtsRate:7;
......@@ -237,7 +235,7 @@ typedef struct _TX_FWINFO_8190PCI{
u32 PacketID:13;
}TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
};
#define TX_DESC_SIZE 32
......@@ -256,8 +254,7 @@ typedef struct _TX_FWINFO_8190PCI{
#define RX_DRIVER_INFO_SIZE 8
typedef struct _LOG_INTERRUPT_8190
{
struct log_int_8190 {
u32 nIMR_COMDOK;
u32 nIMR_MGNTDOK;
u32 nIMR_HIGH;
......@@ -270,17 +267,16 @@ typedef struct _LOG_INTERRUPT_8190
u32 nIMR_TBDOK;
u32 nIMR_BDOK;
u32 nIMR_RXFOVW;
} LOG_INTERRUPT_8190_T, *PLOG_INTERRUPT_8190_T;
};
typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
u8 reserved:4;
u8 rxsc:2;
u8 sgi_en:1;
u8 ex_intf_flag:1;
}phy_ofdm_rx_status_rxsc_sgien_exintfflag;
};
typedef struct _phy_ofdm_rx_status_report_819xpci
{
struct phy_sts_ofdm_819xpci {
u8 trsw_gain_X[4];
u8 pwdb_all;
u8 cfosho_X[4];
......@@ -294,20 +290,19 @@ typedef struct _phy_ofdm_rx_status_report_819xpci
u8 max_ex_pwr;
u8 sgi_en;
u8 rxsc_sgien_exflg;
}phy_sts_ofdm_819xpci_t;
};
typedef struct _phy_cck_rx_status_report_819xpci
{
struct phy_sts_cck_819xpci {
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
}phy_sts_cck_819xpci_t, phy_sts_cck_8192s_t;
};
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
typedef struct _tx_desc_819x_pci {
struct tx_desc {
u16 PktSize;
u8 Offset;
u8 Reserved1:3;
......@@ -343,10 +338,10 @@ typedef struct _tx_desc_819x_pci {
u32 Reserved5;
u32 Reserved6;
u32 Reserved7;
}tx_desc, *ptx_desc;
};
typedef struct _tx_desc_cmd_819x_pci {
struct tx_desc_cmd {
u16 PktSize;
u8 Reserved1;
u8 CmdType:3;
......@@ -367,9 +362,9 @@ typedef struct _tx_desc_cmd_819x_pci {
u32 Reserved4;
u32 Reserved5;
u32 Reserved6;
}tx_desc_cmd, *ptx_desc_cmd;
};
typedef struct _rx_desc_819x_pci{
struct rx_desc {
u16 Length:14;
u16 CRC32:1;
u16 ICV:1;
......@@ -388,10 +383,10 @@ typedef struct _rx_desc_819x_pci{
u32 BufferAddress;
}rx_desc, *prx_desc;
};
typedef struct _rx_fwinfo_819x_pci{
struct rx_fwinfo {
u16 Reserved1:12;
u16 PartAggr:1;
u16 FirstAGGR:1;
......@@ -410,6 +405,6 @@ typedef struct _rx_fwinfo_819x_pci{
u32 TSFL;
}rx_fwinfo, *prx_fwinfo;
};
#endif
drivers/staging/rtl8192e/r8190P_hwimg.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8190P_hwimg.h deleted 100644 → 0
View file @ 1ec3ba93
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef __INC_HAL8190Pci_FW_IMG_H
#define __INC_HAL8190Pci_FW_IMG_H
/*Created on 2008/12/ 3, 3:26*/
#include <linux/types.h>
#define BootArrayLengthPci 344
extern u8 Rtl8190PciFwBootArray[BootArrayLengthPci];
#define MainArrayLengthPci 55388
extern u8 Rtl8190PciFwMainArray[MainArrayLengthPci];
#define DataArrayLengthPci 2960
extern u8 Rtl8190PciFwDataArray[DataArrayLengthPci];
#define PHY_REGArrayLengthPci 280
extern u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLengthPci];
#define PHY_REG_1T2RArrayLengthPci 280
extern u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPci];
#define RadioA_ArrayLengthPci 246
extern u32 Rtl8190PciRadioA_Array[RadioA_ArrayLengthPci] ;
#define RadioB_ArrayLengthPci 78
extern u32 Rtl8190PciRadioB_Array[RadioB_ArrayLengthPci] ;
#define RadioC_ArrayLengthPci 246
extern u32 Rtl8190PciRadioC_Array[RadioC_ArrayLengthPci] ;
#define RadioD_ArrayLengthPci 78
extern u32 Rtl8190PciRadioD_Array[RadioD_ArrayLengthPci] ;
#define MACPHY_ArrayLengthPci 18
extern u32 Rtl8190PciMACPHY_Array[MACPHY_ArrayLengthPci] ;
#define MACPHY_Array_PGLengthPci 21
extern u32 Rtl8190PciMACPHY_Array_PG[MACPHY_Array_PGLengthPci] ;
#define AGCTAB_ArrayLengthPci 384
extern u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLengthPci] ;
#endif
drivers/staging/rtl8192e/r8190P_rtl8256.c
View file @ 1c2de3e7
......@@ -22,7 +22,7 @@
#include "r8192E_phy.h"
#include "r8190P_rtl8256.h"
void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth)
{
u8 eRFPath;
struct r8192_priv *priv = rtllib_priv(dev);
......@@ -34,9 +34,9 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) {
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x100);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x021);
} else {
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
......@@ -45,9 +45,9 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
break;
case HT_CHANNEL_WIDTH_20_40:
if (priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE) {
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x300);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x0e1);
} else {
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
......@@ -79,7 +79,7 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev)
u32 u4RegValue = 0;
u8 eRFPath;
bool rtStatus = true;
BB_REGISTER_DEFINITION_T *pPhyReg;
struct bb_reg_definition *pPhyReg;
struct r8192_priv *priv = rtllib_priv(dev);
u32 RegOffSetToBeCheck = 0x3;
u32 RegValueToBeCheck = 0x7f1;
......@@ -87,7 +87,7 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev)
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) {
for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) {
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
......@@ -112,9 +112,9 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev)
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf);
rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath);
rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath);
if (rtStatus!= true) {
RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
......@@ -125,32 +125,32 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev)
switch (eRFPath) {
case RF90_PATH_A:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_B:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_C:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_D:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
......
drivers/staging/rtl8192e/r8190P_rtl8256.h
View file @ 1c2de3e7
......@@ -21,7 +21,7 @@
#define RTL8225H
#define RTL819X_TOTAL_RF_PATH 2
extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
extern void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth);
extern bool PHY_RF8256_Config(struct net_device* dev);
extern bool phy_RF8256_Config_ParaFile(struct net_device* dev);
extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel);
......
drivers/staging/rtl8192e/r8190_rtl8256.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8190_rtl8256.h deleted 100644 → 0
View file @ 1ec3ba93
/* r8190_rtl8256.h - rtl8256 radio frontend
*
* This is part of the rtl8180-sa2400 driver
* released under the GPL (See file COPYING for details).
* Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
*
* Many thanks to Realtek Corp. for their great support!
*/
#ifndef RTL8225_H
#define RTL8225_H
#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */
void PHY_SetRF8256Bandwidth(struct r8192_priv *priv,
HT_CHANNEL_WIDTH Bandwidth);
RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv);
RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv);
void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel);
void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel);
bool MgntActSet_RF_State(struct r8192_priv *priv,
RT_RF_POWER_STATE StateToSet,
RT_RF_CHANGE_SOURCE ChangeSource);
#endif /* RTL8225_H */
drivers/staging/rtl8192e/r8192E.h deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_cmdpkt.c
View file @ 1c2de3e7
......@@ -42,16 +42,16 @@
{
bool rt_status = true;
struct r8192_priv *priv = rtllib_priv(dev);
struct r8192_priv *priv = rtllib_priv(dev);
u16 frag_threshold;
u16 frag_length = 0, frag_offset = 0;
rt_firmware *pfirmware = priv->pFirmware;
struct rt_firmware *pfirmware = priv->pFirmware;
struct sk_buff *skb;
unsigned char *seg_ptr;
cb_desc *tcb_desc;
struct cb_desc *tcb_desc;
u8 bLastIniPkt;
PTX_FWINFO_8190PCI pTxFwInfo = NULL;
struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
RT_TRACE(COMP_CMDPKT,"%s(),buffer_len is %d\n",__func__,buffer_len);
firmware_init_param(dev);
......@@ -75,15 +75,15 @@
}
memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_NORMAL;
tcb_desc->bLastIniPkt = bLastIniPkt;
tcb_desc->pkt_size = frag_length;
seg_ptr = skb_put(skb, priv->rtllib->tx_headroom);
pTxFwInfo = (PTX_FWINFO_8190PCI)seg_ptr;
memset(pTxFwInfo,0,sizeof(TX_FWINFO_8190PCI));
pTxFwInfo = (struct tx_fwinfo_8190pci *)seg_ptr;
memset(pTxFwInfo,0,sizeof(struct tx_fwinfo_8190pci));
memset(pTxFwInfo,0x12,8);
seg_ptr = skb_put(skb, frag_length);
......@@ -104,11 +104,11 @@
static void
cmpk_count_txstatistic(
struct net_device *dev,
cmpk_txfb_t *pstx_fb)
struct cmpk_txfb *pstx_fb)
{
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef ENABLE_PS
RT_RF_POWER_STATE rtState;
enum rt_rf_power_state rtState;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
......@@ -158,12 +158,12 @@ cmpk_handle_tx_feedback(
u8 * pmsg)
{
struct r8192_priv *priv = rtllib_priv(dev);
cmpk_txfb_t rx_tx_fb; /* */
struct cmpk_txfb rx_tx_fb; /* */
priv->stats.txfeedback++;
memcpy((u8*)&rx_tx_fb, pmsg, sizeof(cmpk_txfb_t));
memcpy((u8*)&rx_tx_fb, pmsg, sizeof(struct cmpk_txfb));
cmpk_count_txstatistic(dev, &rx_tx_fb);
} /* cmpk_Handle_Tx_Feedback */
......@@ -199,14 +199,14 @@ cmpk_handle_interrupt_status(
struct net_device *dev,
u8* pmsg)
{
cmpk_intr_sta_t rx_intr_status; /* */
struct cmpk_intr_sta rx_intr_status; /* */
struct r8192_priv *priv = rtllib_priv(dev);
DMESG("---> cmpk_Handle_Interrupt_Status()\n");
rx_intr_status.length = pmsg[1];
if (rx_intr_status.length != (sizeof(cmpk_intr_sta_t) - 2))
if (rx_intr_status.length != (sizeof(struct cmpk_intr_sta) - 2))
{
DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n");
return;
......@@ -266,13 +266,13 @@ cmpk_handle_query_config_rx(
static void cmpk_count_tx_status( struct net_device *dev,
cmpk_tx_status_t *pstx_status)
struct cmpk_tx_status *pstx_status)
{
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef ENABLE_PS
RT_RF_POWER_STATE rtstate;
enum rt_rf_power_state rtstate;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
......@@ -314,9 +314,9 @@ cmpk_handle_tx_status(
struct net_device *dev,
u8* pmsg)
{
cmpk_tx_status_t rx_tx_sts; /* */
struct cmpk_tx_status rx_tx_sts; /* */
memcpy((void*)&rx_tx_sts, (void*)pmsg, sizeof(cmpk_tx_status_t));
memcpy((void*)&rx_tx_sts, (void*)pmsg, sizeof(struct cmpk_tx_status));
cmpk_count_tx_status(dev, &rx_tx_sts);
}
......@@ -327,9 +327,9 @@ cmpk_handle_tx_rate_history(
struct net_device *dev,
u8* pmsg)
{
cmpk_tx_rahis_t *ptxrate;
struct cmpk_tx_rahis *ptxrate;
u8 i, j;
u16 length = sizeof(cmpk_tx_rahis_t);
u16 length = sizeof(struct cmpk_tx_rahis);
u32 *ptemp;
struct r8192_priv *priv = rtllib_priv(dev);
......@@ -354,7 +354,7 @@ cmpk_handle_tx_rate_history(
ptemp[i] = (temp1<<16)|temp2;
}
ptxrate = (cmpk_tx_rahis_t *)pmsg;
ptxrate = (struct cmpk_tx_rahis *)pmsg;
if (ptxrate == NULL )
{
......@@ -416,7 +416,7 @@ cmpk_message_handle_rx(
case RX_INTERRUPT_STATUS:
RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_INTERRUPT_STATUS\n");
cmpk_handle_interrupt_status(dev, pcmd_buff);
cmd_length = sizeof(cmpk_intr_sta_t);
cmd_length = sizeof(struct cmpk_intr_sta);
break;
case BOTH_QUERY_CONFIG:
RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():BOTH_QUERY_CONFIG\n");
......
drivers/staging/rtl8192e/r8192E_cmdpkt.h
View file @ 1c2de3e7
......@@ -18,20 +18,19 @@
******************************************************************************/
#ifndef R819XUSB_CMDPKT_H
#define R819XUSB_CMDPKT_H
#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t)
#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t)
#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t)
#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)
#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)
#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t)
#define CMPK_RX_TX_FB_SIZE sizeof(struct cmpk_txfb)
#define CMPK_TX_SET_CONFIG_SIZE sizeof(struct cmpk_set_cfg)
#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(struct cmpk_set_cfg)
#define CMPK_RX_TX_STS_SIZE sizeof(struct cmpk_tx_status)
#define CMPK_RX_DBG_MSG_SIZE sizeof(struct cmpk_rx_dbginfo)
#define CMPK_TX_RAHIS_SIZE sizeof(struct cmpk_tx_rahis)
#define ISR_TxBcnOk BIT27
#define ISR_TxBcnErr BIT26
#define ISR_BcnTimerIntr BIT13
typedef struct tag_cmd_pkt_tx_feedback
{
struct cmpk_txfb {
u8 element_id;
u8 length;
u8 TID:4; /* */
......@@ -56,19 +55,17 @@ typedef struct tag_cmd_pkt_tx_feedback
u16 reserve3; /* */
u16 duration; /* */
}cmpk_txfb_t;
};
typedef struct tag_cmd_pkt_interrupt_status
{
struct cmpk_intr_sta {
u8 element_id;
u8 length;
u16 reserve;
u32 interrupt_status;
}cmpk_intr_sta_t;
};
typedef struct tag_cmd_pkt_set_configuration
{
struct cmpk_set_cfg {
u8 element_id;
u8 length;
u16 reserve1;
......@@ -82,12 +79,11 @@ typedef struct tag_cmd_pkt_set_configuration
u8 cfg_offset;
u32 value;
u32 mask;
}cmpk_set_cfg_t;
};
#define cmpk_query_cfg_t cmpk_set_cfg_t
#define cmpk_query_cfg_t struct cmpk_set_cfg
typedef struct tag_tx_stats_feedback
{
struct cmpk_tx_status {
u16 reserve1;
u8 length;
u8 element_id;
......@@ -114,19 +110,17 @@ typedef struct tag_tx_stats_feedback
u16 reserve3_23;
u8 reserve3_1;
u8 rate;
}__attribute__((packed)) cmpk_tx_status_t;
}__packed;
typedef struct tag_rx_debug_message_feedback
{
struct cmpk_rx_dbginfo {
u16 reserve1;
u8 length;
u8 element_id;
}cmpk_rx_dbginfo_t;
};
typedef struct tag_tx_rate_history
{
struct cmpk_tx_rahis {
u8 element_id;
u8 length;
u16 reserved1;
......@@ -141,10 +135,9 @@ typedef struct tag_tx_rate_history
u16 ht_mcs[4][16];
}__attribute__((packed)) cmpk_tx_rahis_t;
} __packed;
typedef enum tag_command_packet_directories
{
enum cmpk_element {
RX_TX_FEEDBACK = 0,
RX_INTERRUPT_STATUS = 1,
TX_SET_CONFIG = 2,
......@@ -154,7 +147,7 @@ typedef enum tag_command_packet_directories
RX_TX_PER_PKT_FEEDBACK = 6,
RX_TX_RATE_HISTORY = 7,
RX_CMD_ELE_MAX
}cmpk_element_e;
};
extern u32 cmpk_message_handle_rx(struct net_device *dev, struct rtllib_rx_stats * pstats);
extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
......
drivers/staging/rtl8192e/r8192E_core.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_core.c.porig deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_core.c.rej deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_dev.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_dev.h
View file @ 1c2de3e7
......@@ -27,7 +27,7 @@
#include "r8190P_def.h"
u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc);
u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc);
bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device* dev);
bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev);
bool rtl8192_HalTxCheckStuck(struct net_device *dev);
......@@ -45,12 +45,12 @@ void rtl8192_get_eeprom_size(struct net_device* dev);
bool rtl8192_adapter_start(struct net_device *dev);
void rtl8192_link_change(struct net_device *dev);
void rtl8192_AllowAllDestAddr(struct net_device* dev, bool bAllowAllDA, bool WriteIntoReg);
void rtl8192_tx_fill_desc(struct net_device* dev, tx_desc * pdesc, cb_desc * cb_desc,
void rtl8192_tx_fill_desc(struct net_device* dev, struct tx_desc * pdesc, struct cb_desc *cb_desc,
struct sk_buff* skb);
void rtl8192_tx_fill_cmd_desc(struct net_device* dev, tx_desc_cmd * entry,
cb_desc * cb_desc, struct sk_buff* skb);
void rtl8192_tx_fill_cmd_desc(struct net_device* dev, struct tx_desc_cmd * entry,
struct cb_desc *cb_desc, struct sk_buff* skb);
bool rtl8192_rx_query_status_desc(struct net_device* dev, struct rtllib_rx_stats *stats,
rx_desc *pdesc, struct sk_buff* skb);
struct rx_desc *pdesc, struct sk_buff* skb);
void rtl8192_halt_adapter(struct net_device *dev, bool reset);
void rtl8192_update_ratr_table(struct net_device* dev);
#endif
drivers/staging/rtl8192e/r8192E_dm.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_dm.h deleted 100644 → 0
View file @ 1ec3ba93
/*****************************************************************************
* Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
*
* Module: Hal819xUsbDM.h (RTL8192 Header H File)
*
*
* Note: For dynamic control definition constant structure.
*
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
* 10/04/2007 MHC Create initial version.
*
*****************************************************************************/
#ifndef __R8192UDM_H__
#define __R8192UDM_H__
#define OFDM_Table_Length 19
#define CCK_Table_length 12
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
#define DM_DIG_HIGH_PWR_THRESH_LOW 70
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_check_fsync_time_interval 500
#define DM_DIG_BACKOFF 12
#define DM_DIG_MAX 0x36
#define DM_DIG_MIN 0x1c
#define DM_DIG_MIN_Netcore 0x12
#define RxPathSelection_SS_TH_low 30
#define RxPathSelection_diff_TH 18
#define RateAdaptiveTH_High 50
#define RateAdaptiveTH_Low_20M 30
#define RateAdaptiveTH_Low_40M 10
#define VeryLowRSSI 15
#define CTSToSelfTHVal 35
//defined by vivi, for tx power track
#define E_FOR_TX_POWER_TRACK 300
//Dynamic Tx Power Control Threshold
#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
//added by amy for atheros AP
#define TX_POWER_ATHEROAP_THRESH_HIGH 78
#define TX_POWER_ATHEROAP_THRESH_LOW 72
//defined by vivi, for showing on UI. Newer firmware has changed to 0x1e0
#define Current_Tx_Rate_Reg 0x1e0//0x1b8
#define Initial_Tx_Rate_Reg 0x1e1 //0x1b9
#define Tx_Retry_Count_Reg 0x1ac
#define RegC38_TH 20
/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
typedef struct _dynamic_initial_gain_threshold_
{
u8 dig_enable_flag;
u8 dig_algorithm;
u8 dbg_mode;
u8 dig_algorithm_switch;
long rssi_low_thresh;
long rssi_high_thresh;
long rssi_high_power_lowthresh;
long rssi_high_power_highthresh;
u8 dig_state;
u8 dig_highpwr_state;
u8 cur_connect_state;
u8 pre_connect_state;
u8 curpd_thstate;
u8 prepd_thstate;
u8 curcs_ratio_state;
u8 precs_ratio_state;
u32 pre_ig_value;
u32 cur_ig_value;
u8 backoff_val;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
bool initialgain_lowerbound_state;
long rssi_val;
}dig_t;
typedef enum tag_dynamic_init_gain_state_definition
{
DM_STA_DIG_OFF = 0,
DM_STA_DIG_ON,
DM_STA_DIG_MAX
}dm_dig_sta_e;
/* 2007/10/08 MH Define RATR state. */
typedef enum tag_dynamic_ratr_state_definition
{
DM_RATR_STA_HIGH = 0,
DM_RATR_STA_MIDDLE = 1,
DM_RATR_STA_LOW = 2,
DM_RATR_STA_MAX
}dm_ratr_sta_e;
/* 2007/10/11 MH Define DIG operation type. */
typedef enum tag_dynamic_init_gain_operation_type_definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
DIG_TYPE_DBG_MODE = 4,
DIG_TYPE_RSSI = 5,
DIG_TYPE_ALGORITHM = 6,
DIG_TYPE_BACKOFF = 7,
DIG_TYPE_PWDB_FACTOR = 8,
DIG_TYPE_RX_GAIN_MIN = 9,
DIG_TYPE_RX_GAIN_MAX = 10,
DIG_TYPE_ENABLE = 20,
DIG_TYPE_DISABLE = 30,
DIG_OP_TYPE_MAX
}dm_dig_op_e;
typedef enum tag_dig_algorithm_definition
{
DIG_ALGO_BY_FALSE_ALARM = 0,
DIG_ALGO_BY_RSSI = 1,
DIG_ALGO_MAX
}dm_dig_alg_e;
typedef enum tag_dig_dbgmode_definition
{
DIG_DBG_OFF = 0,
DIG_DBG_ON = 1,
DIG_DBG_MAX
}dm_dig_dbg_e;
typedef enum tag_dig_connect_definition
{
DIG_DISCONNECT = 0,
DIG_CONNECT = 1,
DIG_CONNECT_MAX
}dm_dig_connect_e;
typedef enum tag_dig_packetdetection_threshold_definition
{
DIG_PD_AT_LOW_POWER = 0,
DIG_PD_AT_NORMAL_POWER = 1,
DIG_PD_AT_HIGH_POWER = 2,
DIG_PD_MAX
}dm_dig_pd_th_e;
typedef enum tag_dig_cck_cs_ratio_state_definition
{
DIG_CS_RATIO_LOWER = 0,
DIG_CS_RATIO_HIGHER = 1,
DIG_CS_MAX
}dm_dig_cs_ratio_e;
typedef struct _Dynamic_Rx_Path_Selection_
{
u8 Enable;
u8 DbgMode;
u8 cck_method;
u8 cck_Rx_path;
u8 SS_TH_low;
u8 diff_TH;
u8 disabledRF;
u8 reserved;
u8 rf_rssi[4];
u8 rf_enable_rssi_th[4];
long cck_pwdb_sta[4];
}DRxPathSel;
typedef enum tag_CCK_Rx_Path_Method_Definition
{
CCK_Rx_Version_1 = 0,
CCK_Rx_Version_2= 1,
CCK_Rx_Version_MAX
}DM_CCK_Rx_Path_Method;
typedef enum tag_DM_DbgMode_Definition
{
DM_DBG_OFF = 0,
DM_DBG_ON = 1,
DM_DBG_MAX
}DM_DBG_E;
typedef struct tag_Tx_Config_Cmd_Format
{
u32 Op; /* Command packet type. */
u32 Length; /* Command packet length. */
u32 Value;
}DCMD_TXCMD_T, *PDCMD_TXCMD_T;
extern dig_t dm_digtable;
extern DRxPathSel DM_RxPathSelTable;
void init_hal_dm(struct r8192_priv *priv);
void deinit_hal_dm(struct r8192_priv *priv);
void hal_dm_watchdog(struct r8192_priv *priv);
void init_rate_adaptive(struct r8192_priv *priv);
void dm_txpower_trackingcallback(struct work_struct *work);
void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
void dm_initialize_txpower_tracking(struct r8192_priv *priv);
void dm_cck_txpower_adjust(struct r8192_priv *priv, bool binch14);
#endif /*__R8192UDM_H__ */
drivers/staging/rtl8192e/r8192E_firmware.c
View file @ 1c2de3e7
......@@ -25,24 +25,24 @@
extern void firmware_init_param(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
rt_firmware *pfirmware = priv->pFirmware;
struct r8192_priv *priv = rtllib_priv(dev);
struct rt_firmware *pfirmware = priv->pFirmware;
pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE);
}
bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len)
{
struct r8192_priv *priv = rtllib_priv(dev);
struct r8192_priv *priv = rtllib_priv(dev);
bool rt_status = true;
u16 frag_threshold;
u16 frag_length, frag_offset = 0;
int i;
rt_firmware *pfirmware = priv->pFirmware;
struct rt_firmware *pfirmware = priv->pFirmware;
struct sk_buff *skb;
unsigned char *seg_ptr;
cb_desc *tcb_desc;
struct cb_desc *tcb_desc;
u8 bLastIniPkt;
firmware_init_param(dev);
......@@ -60,7 +60,7 @@ bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buff
skb = dev_alloc_skb(frag_length + 4);
memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
tcb_desc->bLastIniPkt = bLastIniPkt;
......@@ -101,16 +101,16 @@ fwSendNullPacket(
)
{
bool rtStatus = true;
struct r8192_priv *priv = rtllib_priv(dev);
struct r8192_priv *priv = rtllib_priv(dev);
struct sk_buff *skb;
cb_desc *tcb_desc;
struct cb_desc *tcb_desc;
unsigned char *ptr_buf;
bool bLastInitPacket = false;
skb = dev_alloc_skb(Length+ 4);
memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
tcb_desc->queue_index = TXCMD_QUEUE;
tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
tcb_desc->bLastIniPkt = bLastInitPacket;
......@@ -209,8 +209,8 @@ bool CPUcheck_firmware_ready(struct net_device *dev)
inline static bool firmware_check_ready(struct net_device *dev, u8 load_fw_status)
{
struct r8192_priv *priv = rtllib_priv(dev);
rt_firmware *pfirmware = priv->pFirmware;
struct r8192_priv *priv = rtllib_priv(dev);
struct rt_firmware *pfirmware = priv->pFirmware;
bool rt_status = true;
switch (load_fw_status) {
......@@ -253,7 +253,7 @@ inline static bool firmware_check_ready(struct net_device *dev, u8 load_fw_statu
bool init_firmware(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
struct r8192_priv *priv = rtllib_priv(dev);
bool rt_status = true;
u8 *firmware_img_buf[3] = { &Rtl8192PciEFwBootArray[0],
......@@ -266,10 +266,10 @@ bool init_firmware(struct net_device *dev)
u32 file_length = 0;
u8 *mapped_file = NULL;
u8 init_step = 0;
opt_rst_type_e rst_opt = OPT_SYSTEM_RESET;
firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT;
enum opt_rst_type rst_opt = OPT_SYSTEM_RESET;
enum firmware_init_step starting_state = FW_INIT_STEP0_BOOT;
rt_firmware *pfirmware = priv->pFirmware;
struct rt_firmware *pfirmware = priv->pFirmware;
RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n");
......@@ -303,7 +303,7 @@ bool init_firmware(struct net_device *dev)
goto download_firmware_fail;
}
if (fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) {
RT_TRACE(COMP_FIRMWARE, "img file size exceed the container buffer fail!\n");
RT_TRACE(COMP_FIRMWARE, "img file size exceed the container struct buffer fail!\n");
goto download_firmware_fail;
}
......
drivers/staging/rtl8192e/r8192E_firmware.h
View file @ 1c2de3e7
......@@ -23,49 +23,49 @@
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 )
typedef enum _firmware_init_step{
enum firmware_init_step {
FW_INIT_STEP0_BOOT = 0,
FW_INIT_STEP1_MAIN = 1,
FW_INIT_STEP2_DATA = 2,
}firmware_init_step_e;
};
typedef enum _opt_rst_type{
enum opt_rst_type {
OPT_SYSTEM_RESET = 0,
OPT_FIRMWARE_RESET = 1,
}opt_rst_type_e;
};
typedef enum _desc_packet_type_e{
enum desc_packet_type {
DESC_PACKET_TYPE_INIT = 0,
DESC_PACKET_TYPE_NORMAL = 1,
}desc_packet_type_e;
};
typedef enum _firmware_source{
enum firmware_source {
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1,
}firmware_source_e, *pfirmware_source_e;
};
typedef enum _firmware_status{
enum firmware_status {
FW_STATUS_0_INIT = 0,
FW_STATUS_1_MOVE_BOOT_CODE = 1,
FW_STATUS_2_MOVE_MAIN_CODE = 2,
FW_STATUS_3_TURNON_CPU = 3,
FW_STATUS_4_MOVE_DATA_CODE = 4,
FW_STATUS_5_READY = 5,
}firmware_status_e;
};
typedef struct _rt_firmare_seg_container {
struct fw_seg_container {
u16 seg_size;
u8 *seg_ptr;
}fw_seg_container, *pfw_seg_container;
};
typedef struct _rt_firmware{
firmware_status_e firmware_status;
struct rt_firmware {
enum firmware_status firmware_status;
u16 cmdpacket_frag_thresold;
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
#define MAX_FW_INIT_STEP 3
u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
u16 firmware_buf_size[MAX_FW_INIT_STEP];
} rt_firmware, *prt_firmware;
};
bool init_firmware(struct net_device *dev);
extern void firmware_init_param(struct net_device *dev);
......
drivers/staging/rtl8192e/r8192E_hw.h
View file @ 1c2de3e7
......@@ -21,10 +21,10 @@
#ifndef R8180_HW
#define R8180_HW
typedef enum _BaseBand_Config_Type {
enum baseband_config {
BaseBand_Config_PHY_REG = 0,
BaseBand_Config_AGC_TAB = 1,
} BaseBand_Config_Type, *PBaseBand_Config_Type;
};
#define RTL8187_REQT_READ 0xc0
#define RTL8187_REQT_WRITE 0x40
......
drivers/staging/rtl8192e/r8192E_phy.c
View file @ 1c2de3e7
......@@ -47,8 +47,8 @@ static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
/*************************Define local function prototype**********************/
static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
static u32 phy_FwRFSerialRead(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset);
static void phy_FwRFSerialWrite(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data);
u32 rtl8192_CalculateBitShift(u32 dwBitMask)
{
u32 i;
......@@ -99,12 +99,12 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
return (Ret);
}
u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 ret = 0;
u32 NewOffset = 0;
BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
struct bb_reg_definition* pPhyReg = &priv->PHYRegDef[eRFPath];
Offset &= 0x3f;
if (priv->rf_chip == RF_8256)
......@@ -160,11 +160,11 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath,
}
void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 DataAndAddr = 0, NewOffset = 0;
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
Offset &= 0x3f;
if (priv->rf_chip == RF_8256)
......@@ -218,7 +218,7 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath
return;
}
void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 Original_Value, BitShift, New_Value;
......@@ -258,7 +258,7 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
return;
}
u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask)
{
u32 Original_Value, Readback_Value, BitShift;
struct r8192_priv *priv = rtllib_priv(dev);
......@@ -285,7 +285,7 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u3
static u32 phy_FwRFSerialRead(
struct net_device* dev,
RF90_RADIO_PATH_E eRFPath,
enum rf90_radio_path eRFPath,
u32 Offset )
{
u32 retValue = 0;
......@@ -322,7 +322,7 @@ static u32 phy_FwRFSerialRead(
static void
phy_FwRFSerialWrite(
struct net_device* dev,
RF90_RADIO_PATH_E eRFPath,
enum rf90_radio_path eRFPath,
u32 Offset,
u32 Data )
{
......@@ -510,7 +510,7 @@ void rtl8192_InitBBRFRegDef(struct net_device* dev)
priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
}
bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath)
{
bool ret = true;
u32 i, CheckTimes = 4, dwRegRead = 0;
......@@ -576,9 +576,9 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev)
dwRegValue = read_nic_dword(dev, CPU_GEN);
write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
for (eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
for (eCheckItem=(enum hw90_block)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
{
rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0);
rtStatus = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block)eCheckItem, (enum rf90_radio_path)0);
if (rtStatus != true)
{
RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
......@@ -741,7 +741,7 @@ void rtl8192_phy_updateInitGain(struct net_device* dev)
return;
}
u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath)
{
int i;
......@@ -824,16 +824,16 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
return;
}
u8 rtl8192_phy_SetSwChnlCmdArray(
SwChnlCmd* CmdTable,
struct sw_chnl_cmd* CmdTable,
u32 CmdTableIdx,
u32 CmdTableSz,
SwChnlCmdID CmdID,
enum sw_chnl_cmd_id CmdID,
u32 Para1,
u32 Para2,
u32 msDelay
)
{
SwChnlCmd* pCmd;
struct sw_chnl_cmd* pCmd;
if (CmdTable == NULL)
{
......@@ -858,13 +858,13 @@ u8 rtl8192_phy_SetSwChnlCmdArray(
u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
{
struct r8192_priv *priv = rtllib_priv(dev);
SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
u32 PreCommonCmdCnt;
SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT];
u32 PostCommonCmdCnt;
SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
u32 RfDependCmdCnt;
SwChnlCmd *CurrentCmd = NULL;
struct sw_chnl_cmd *CurrentCmd = NULL;
u8 eRFPath;
RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel);
......@@ -969,7 +969,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u
break;
case CmdID_RF_WriteReg:
for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
break;
default:
break;
......@@ -1264,7 +1264,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
}
void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset)
{
struct r8192_priv *priv = rtllib_priv(dev);
......@@ -1377,11 +1377,11 @@ PHY_SetRtl8192eRfOff(struct net_device* dev )
bool
SetRFPowerState8190(
struct net_device* dev,
RT_RF_POWER_STATE eRFPowerState
enum rt_rf_power_state eRFPowerState
)
{
struct r8192_priv *priv = rtllib_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)(&(priv->rtllib->PowerSaveControl));
bool bResult = true;
u8 i = 0, QueueID = 0;
struct rtl8192_tx_ring *ring = NULL;
......@@ -1547,7 +1547,7 @@ SetRFPowerState8190(
bool
SetRFPowerState(
struct net_device* dev,
RT_RF_POWER_STATE eRFPowerState
enum rt_rf_power_state eRFPowerState
)
{
struct r8192_priv *priv = rtllib_priv(dev);
......
drivers/staging/rtl8192e/r8192E_phy.h
View file @ 1c2de3e7
......@@ -47,7 +47,7 @@
typedef enum _SwChnlCmdID {
enum sw_chnl_cmd_id {
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
......@@ -55,15 +55,15 @@ typedef enum _SwChnlCmdID {
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
} SwChnlCmdID;
};
/*--------------------------------Define structure--------------------------------*/
typedef struct _SwChnlCmd {
SwChnlCmdID CmdID;
struct sw_chnl_cmd {
enum sw_chnl_cmd_id CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
} __attribute__ ((packed)) SwChnlCmd;
} __packed;
extern u32 rtl819XMACPHY_Array_PG[];
extern u32 rtl819XPHY_REG_1T2RArray[];
......@@ -73,21 +73,21 @@ extern u32 rtl819XRadioB_Array[];
extern u32 rtl819XRadioC_Array[];
extern u32 rtl819XRadioD_Array[];
typedef enum _HW90_BLOCK {
enum hw90_block {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4,
} HW90_BLOCK_E, *PHW90_BLOCK_E;
};
typedef enum _RF90_RADIO_PATH{
enum rf90_radio_path {
RF90_PATH_A = 0,
RF90_PATH_B = 1,
RF90_PATH_C = 2,
RF90_PATH_D = 3,
RF90_PATH_MAX
}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
};
#define bMaskByte0 0xff
#define bMaskByte1 0xff00
......@@ -100,20 +100,20 @@ typedef enum _RF90_RADIO_PATH{
extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
extern void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask);
extern void rtl8192_phy_configmac(struct net_device* dev);
extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath);
extern bool rtl8192_BBConfig(struct net_device* dev);
extern void rtl8192_phy_getTxPower(struct net_device* dev);
extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
extern bool rtl8192_phy_RFConfig(struct net_device* dev);
extern void rtl8192_phy_updateInitGain(struct net_device* dev);
extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath);
extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath);
extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
extern void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset);
extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
......@@ -123,7 +123,7 @@ extern void PHY_SetRtl8192eRfOff(struct net_device *dev);
bool
SetRFPowerState(
struct net_device* dev,
RT_RF_POWER_STATE eRFPowerState
enum rt_rf_power_state eRFPowerState
);
#define PHY_SetRFPowerState SetRFPowerState
......
drivers/staging/rtl8192e/r8192E_wx.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_wx.h deleted 100644 → 0
View file @ 1ec3ba93
/*
This is part of rtl8180 OpenSource driver - v 0.3
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
Parts of this driver are based on the GPL part of the official realtek driver
Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon
Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
We want to tanks the Authors of such projects and the Ndiswrapper project Authors.
*/
/* this file (will) contains wireless extension handlers*/
#ifndef R8180_WX_H
#define R8180_WX_H
extern struct iw_handler_def r8192_wx_handlers_def;
#endif
drivers/staging/rtl8192e/r8192_pm.c deleted 100644 → 0
View file @ 1ec3ba93
/*
Power management interface routines.
Written by Mariusz Matuszek.
This code is currently just a placeholder for later work and
does not do anything useful.
This is part of rtl8180 OpenSource driver.
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
*/
#include "r8192E.h"
#include "r8192E_hw.h"
#include "r8192_pm.h"
#include "r8190_rtl8256.h"
int rtl8192E_save_state (struct pci_dev *dev, pm_message_t state)
{
printk(KERN_NOTICE "r8192E save state call (state %u).\n", state.event);
return -EAGAIN;
}
int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct r8192_priv *priv = ieee80211_priv(dev);
u32 ulRegRead;
RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n");
if (!netif_running(dev))
goto out_pci_suspend;
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
// Call MgntActSet_RF_State instead to prevent RF config race condition.
if(!priv->ieee80211->bSupportRemoteWakeUp) {
MgntActSet_RF_State(priv, eRfOff, RF_CHANGE_BY_INIT);
// 2006.11.30. System reset bit
ulRegRead = read_nic_dword(priv, CPU_GEN);
ulRegRead|=CPU_GEN_SYSTEM_RESET;
write_nic_dword(priv, CPU_GEN, ulRegRead);
} else {
//2008.06.03 for WOL
write_nic_dword(priv, WFCRC0, 0xffffffff);
write_nic_dword(priv, WFCRC1, 0xffffffff);
write_nic_dword(priv, WFCRC2, 0xffffffff);
//Write PMR register
write_nic_byte(priv, PMR, 0x5);
//Disable tx, enanble rx
write_nic_byte(priv, MacBlkCtrl, 0xa);
}
out_pci_suspend:
RT_TRACE(COMP_POWER, "r8192E support WOL call??????????????????????\n");
if(priv->ieee80211->bSupportRemoteWakeUp) {
RT_TRACE(COMP_POWER, "r8192E support WOL call!!!!!!!!!!!!!!!!!!.\n");
}
netif_device_detach(dev);
pci_save_state(pdev);
pci_disable_device(pdev);
pci_enable_wake(pdev, pci_choose_state(pdev,state),
priv->ieee80211->bSupportRemoteWakeUp?1:0);
pci_set_power_state(pdev,pci_choose_state(pdev,state));
return 0;
}
int rtl8192E_resume (struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
int err;
u32 val;
RT_TRACE(COMP_POWER, "================>r8192E resume call.\n");
pci_set_power_state(pdev, PCI_D0);
err = pci_enable_device(pdev);
if(err) {
printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
dev->name);
return err;
}
pci_restore_state(pdev);
/*
* Suspend/Resume resets the PCI configuration space, so we have to
* re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
* from interfering with C3 CPU state. pci_restore_state won't help
* here since it only restores the first 64 bytes pci config header.
*/
pci_read_config_dword(pdev, 0x40, &val);
if ((val & 0x0000ff00) != 0) {
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
}
pci_enable_wake(pdev, PCI_D0, 0);
if(!netif_running(dev))
goto out;
netif_device_attach(dev);
if (dev->netdev_ops->ndo_open)
dev->netdev_ops->ndo_open(dev);
out:
RT_TRACE(COMP_POWER, "<================r8192E resume call.\n");
return 0;
}
int rtl8192E_enable_wake (struct pci_dev *dev, pm_message_t state, int enable)
{
printk(KERN_NOTICE "r8192E enable wake call (state %u, enable %d).\n",
state.event, enable);
return -EAGAIN;
}
drivers/staging/rtl8192e/r8192_pm.h deleted 100644 → 0
View file @ 1ec3ba93
/*
Power management interface routines.
Written by Mariusz Matuszek.
This code is currently just a placeholder for later work and
does not do anything useful.
This is part of rtl8180 OpenSource driver.
Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it>
Released under the terms of GPL (General Public Licence)
*/
#ifndef R8192E_PM_H
#define R8192E_PM_H
#include <linux/types.h>
#include <linux/pci.h>
int rtl8192E_save_state (struct pci_dev *dev, pm_message_t state);
int rtl8192E_suspend (struct pci_dev *dev, pm_message_t state);
int rtl8192E_resume (struct pci_dev *dev);
int rtl8192E_enable_wake (struct pci_dev *dev, pm_message_t state, int enable);
#endif //R8192E_PM_H
drivers/staging/rtl8192e/r819xE_cmdpkt.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r819xE_cmdpkt.h deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r819xE_firmware.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r819xE_phy.c deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/r819xE_phy.h deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/readme deleted 100644 → 0
View file @ 1ec3ba93
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_BA.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_BAProc.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_HT.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_HTProc.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_Qos.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_TS.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl819x_TSProc.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_cam.c
View file @ 1c2de3e7
......@@ -119,7 +119,7 @@ void setKey(struct net_device *dev,
u16 usConfig = 0;
u8 i;
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
RT_RF_POWER_STATE rtState;
enum rt_rf_power_state rtState;
rtState = priv->rtllib->eRFPowerState;
if (priv->rtllib->PowerSaveControl.bInactivePs){
if (rtState == eRfOff){
......
drivers/staging/rtl8192e/rtl_core.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_core.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_debug.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_debug.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_dm.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_dm.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_pci.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_ps.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtl_wx.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib.h
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib_crypt.h
View file @ 1c2de3e7
......@@ -61,7 +61,7 @@ struct rtllib_crypto_ops {
/* maximum number of bytes added by encryption; encrypt buf is
* allocated with extra_prefix_len bytes, copy of in_buf, and
* extra_postfix_len; encrypt need not use all this space, but
* the result must start at the beginning of the buffer and correct
* the result must start at the beginning of the struct buffer and correct
* length must be returned */
int extra_prefix_len, extra_postfix_len;
......
drivers/staging/rtl8192e/rtllib_crypt_wep.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib_module.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib_rx.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib_softmac.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib_tx.c
View file @ 1c2de3e7
This diff is collapsed.
drivers/staging/rtl8192e/rtllib_wx.c
View file @ 1c2de3e7
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7