Commit 2b89da46 authored by Mario Limonciello's avatar Mario Limonciello Committed by Alex Deucher

drm/amd: fix some dead code in `gfx_v9_0_init_cp_compute_microcode`

Some dead code was introduced as part of utilizing the `amdgpu_ucode_*`
helpers. Adjust the control flow to make sure that firmware is released
in the appropriate error flows.
Reported-by: default avatarcoverity-bot <keescook+coverity-bot@chromium.org>
Addresses-Coverity-ID: 1530548 ("Control flow issues")
Fixes: ec787deb ("drm/amd: Use `amdgpu_ucode_*` helpers for GFX9")
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Reviewed-by: default avatarKees Cook <keescook@chromium.org>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d144b40a
...@@ -1345,7 +1345,7 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, ...@@ -1345,7 +1345,7 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
if (err) if (err)
return err; goto out;
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
...@@ -1355,13 +1355,14 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, ...@@ -1355,13 +1355,14 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
else else
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
/* ignore failures to load */
err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
if (!err) { if (!err) {
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
} else { } else {
err = 0; err = 0;
adev->gfx.mec2_fw = NULL; amdgpu_ucode_release(&adev->gfx.mec2_fw);
} }
} else { } else {
adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
...@@ -1370,10 +1371,10 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, ...@@ -1370,10 +1371,10 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
gfx_v9_0_check_if_need_gfxoff(adev); gfx_v9_0_check_if_need_gfxoff(adev);
gfx_v9_0_check_fw_write_wait(adev); gfx_v9_0_check_fw_write_wait(adev);
if (err) {
out:
if (err)
amdgpu_ucode_release(&adev->gfx.mec_fw); amdgpu_ucode_release(&adev->gfx.mec_fw);
amdgpu_ucode_release(&adev->gfx.mec2_fw);
}
return err; return err;
} }
......
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