[IA64-SGI] Add support for a future SGI chipset (shub2) 2of4

This patch adds the addresses of shub2 MMRS to the shub_mmr
header file. During boot, a SAL call is made to determine the
type of the shub. Platform initialization sets the appropriate
MMR addresses for the platform.

A new macro (is_shub1() & is_shub2()) can be used at runtime to
determine the type of the shub.
Signed-off-by: Jack Steiner <steiner@sgi.com>

arch/ia64/sn/kernel/iomv.c

@@ -42,8 +42,7 @@ void *sn_io_addr(unsigned long port)
 		 */
 		if ((port >= 0x1f0 && port <= 0x1f7) ||
 		    port == 0x3f6 || port == 0x3f7) {
-			io_base = (0xc000000fcc000000UL |
-				   ((unsigned long)get_nasid() << 38));
+			io_base = GLOBAL_MMR_ADDR(get_nasid(), 0xfcc000000UL);
 			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
 		} else {
 			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
@@ -66,9 +65,10 @@ EXPORT_SYMBOL(sn_io_addr);
  */
 void __sn_mmiowb(void)
 {
-	while ((((volatile unsigned long)(*pda->pio_write_status_addr)) &
-		SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK) !=
-	       SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK)
+	volatile unsigned long *adr = pda->pio_write_status_addr;
+	unsigned long val = pda->pio_write_status_val;
+
+	while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
 		cpu_relax();
 }
 

arch/ia64/sn/kernel/setup.c

@@ -215,8 +215,10 @@ static inline int __init is_shub_1_1(int nasid)
 	unsigned long id;
 	int rev;
 
-	id = REMOTE_HUB_L(nasid, SH_SHUB_ID);
-	rev = (id & SH_SHUB_ID_REVISION_MASK) >> SH_SHUB_ID_REVISION_SHFT;
+	if (is_shub2())
+		return 0;
+	id = REMOTE_HUB_L(nasid, SH1_SHUB_ID);
+	rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT;
 	return rev <= 2;
 }
 
@@ -224,9 +226,13 @@ static void __init sn_check_for_wars(void)
 {
 	int cnode;
 
-	for (cnode = 0; cnode < numnodes; cnode++)
-		if (is_shub_1_1(cnodeid_to_nasid(cnode)))
-			shub_1_1_found = 1;
+	if (is_shub2()) {
+		/* none yet */
+	} else {
+		for (cnode = 0; cnode < numnodes; cnode++)
+			if (is_shub_1_1(cnodeid_to_nasid(cnode)))
+				shub_1_1_found = 1;
+	}
 }
 
 /**
@@ -477,21 +483,29 @@ void __init sn_cpu_init(void)
 	pda->shub_1_1_found = shub_1_1_found;
 
 	/*
-	 * We must use different memory allocators for first cpu (bootmem 
-	 * allocator) than for the other cpus (regular allocator).
+	 * Set up addresses of PIO/MEM write status registers.
 	 */
-	pda->pio_write_status_addr = (volatile unsigned long *)
-	    LOCAL_MMR_ADDR((slice <
-			    2 ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1));
+	{
+		u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
+		u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_1, 
+			SH2_PIO_WRITE_STATUS_2, SH2_PIO_WRITE_STATUS_3};
+		u64 *pio;
+		pio = is_shub1() ? pio1 : pio2;
+		pda->pio_write_status_addr = (volatile unsigned long *) LOCAL_MMR_ADDR(pio[slice]);
+		pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0;
+	}
 
-	if (local_node_data->active_cpu_count++ == 0) {
+	/*
+	 * WAR addresses for SHUB 1.x.
+	 */
+	if (local_node_data->active_cpu_count++ == 0 && is_shub1()) {
 		int buddy_nasid;
 		buddy_nasid =
 		    cnodeid_to_nasid(numa_node_id() ==
 				     numnodes - 1 ? 0 : numa_node_id() + 1);
 		pda->pio_shub_war_cam_addr =
 		    (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid,
-							      SH_PI_CAM_CONTROL);
+							      SH1_PI_CAM_CONTROL);
 	}
 }
 

arch/ia64/sn/kernel/sn2/ptc_deadlock.S

@@ -9,9 +9,9 @@
 #include <asm/sn/shub_mmr.h>
 
 #define ZEROVAL		0x3f		// "zero" value for outstanding PIO requests
-#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT
-#define WRITECOUNT	SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT
-#define ALIAS_OFFSET	(SH_PIO_WRITE_STATUS_0_ALIAS-SH_PIO_WRITE_STATUS_0)
+#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
+#define WRITECOUNT	SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT
+#define ALIAS_OFFSET	(SH1_PIO_WRITE_STATUS_0_ALIAS-SH1_PIO_WRITE_STATUS_0)
 
 
 	.global	sn2_ptc_deadlock_recovery_core

arch/ia64/sn/kernel/sn2/sn2_smp.c

@@ -46,15 +46,14 @@ static unsigned long sn2_ptc_deadlock_count;
 
 static inline unsigned long wait_piowc(void)
 {
-	volatile unsigned long *piows;
+	volatile unsigned long *piows, piows_val;
 	unsigned long ws;
 
 	piows = pda->pio_write_status_addr;
+	piows_val = pda->pio_write_status_val;
 	do {
-		ia64_mfa();
-	} while (((ws =
-		   *piows) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK) !=
-		 SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK);
+		cpu_relax();
+	} while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != piows_val);
 	return ws;
 }
 
@@ -129,20 +128,20 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
 	     cnode = find_next_bit(&nodes_flushed, NR_NODES, ++cnode))
 		nasids[nix++] = cnodeid_to_nasid(cnode);
 
-	data0 = (1UL << SH_PTC_0_A_SHFT) |
-	    (nbits << SH_PTC_0_PS_SHFT) |
-	    ((ia64_get_rr(start) >> 8) << SH_PTC_0_RID_SHFT) |
-	    (1UL << SH_PTC_0_START_SHFT);
+	data0 = (1UL << SH1_PTC_0_A_SHFT) |
+	    (nbits << SH1_PTC_0_PS_SHFT) |
+	    ((ia64_get_rr(start) >> 8) << SH1_PTC_0_RID_SHFT) |
+	    (1UL << SH1_PTC_0_START_SHFT);
 
-	ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH_PTC_0);
-	ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH_PTC_1);
+	ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
+	ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
 
 	mynasid = get_nasid();
 
 	spin_lock_irqsave(&sn2_global_ptc_lock, flags);
 
 	do {
-		data1 = start | (1UL << SH_PTC_1_START_SHFT);
+		data1 = start | (1UL << SH1_PTC_1_START_SHFT);
 		for (i = 0; i < nix; i++) {
 			nasid = nasids[i];
 			if (likely(nasid == mynasid)) {
@@ -159,7 +158,7 @@ sn2_global_tlb_purge(unsigned long start, unsigned long end,
 
 		if (flushed
 		    && (wait_piowc() &
-			SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK)) {
+			SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK)) {
 			sn2_ptc_deadlock_recovery(data0, data1);
 		}
 
@@ -188,8 +187,8 @@ void sn2_ptc_deadlock_recovery(unsigned long data0, unsigned long data1)
 
 	sn2_ptc_deadlock_count++;
 
-	ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH_PTC_0);
-	ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH_PTC_1);
+	ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
+	ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
 	piows = (long *)pda->pio_write_status_addr;
 
 	mycnode = numa_node_id();

arch/ia64/sn/kernel/sn2/timer.c

@@ -15,7 +15,6 @@
 #include <asm/hw_irq.h>
 #include <asm/system.h>
 
-#include "shub.h"
 #include <asm/sn/leds.h>
 #include <asm/sn/shub_mmr.h>
 #include <asm/sn/clksupport.h>

include/asm-ia64/sn/arch.h

@@ -20,7 +20,8 @@
  * Effectively, it's the maximum number of compact node ids (cnodeid_t).
  * This is not necessarily the same as MAX_NASIDS.
  */
-#define MAX_COMPACT_NODES       2048
+#define MAX_COMPACT_NODES	2048
+#define CPUS_PER_NODE		4
 
 extern void sn_flush_all_caches(long addr, long bytes);
 

include/asm-ia64/sn/sn_cpuid.h

@@ -13,6 +13,7 @@
 
 #include <linux/config.h>
 #include <linux/smp.h>
+#include <asm/sn/addrs.h>
 #include <asm/sn/pda.h>
 #include <asm/intrinsics.h>
 
@@ -86,11 +87,9 @@
 #endif
 
 
-#define get_node_number(addr)			(((unsigned long)(addr)>>38) & 0x7ff)
+#define get_node_number(addr)			NASID_GET(addr)
 
 /*
- * NOTE: id & eid refer to Intel's definitions of the LID register
- * 
  * NOTE: on non-MP systems, only cpuid 0 exists
  */