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Commit 2e9cf554 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Matthias Brugger
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arm64: dts: mediatek: adjust whitespace around '=' 

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220526204402.832393-1-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 77d30613
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Showing with 40 additions and 40 deletions
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View file @ 2e9cf554
......@@ -106,7 +106,7 @@ &cpu2 {
};
&eth {
phy-mode ="rgmii-rxid";
phy-mode = "rgmii-rxid";
phy-handle = <&ethernet_phy0>;
mediatek,tx-delay-ps = <1530>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
......
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View file @ 2e9cf554
......@@ -336,14 +336,14 @@ mux {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
groups = "i2c2_0";
};
};
......@@ -366,14 +366,14 @@ conf {
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
groups = "ir_1_tx";
};
};
......
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View file @ 2e9cf554
......@@ -298,14 +298,14 @@ mux {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
groups = "i2c2_0";
};
};
......@@ -328,14 +328,14 @@ conf {
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
groups = "ir_1_tx";
};
};
......
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View file @ 2e9cf554
......@@ -118,8 +118,8 @@ clk25m: oscillator {
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
pmu {
......@@ -616,9 +616,9 @@ audsys: clock-controller@11220000 {
afe: audio-controller {
compatible = "mediatek,mt7622-audio";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
<&topckgen CLK_TOP_AUD1_SEL>,
......
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View file @ 2e9cf554
......@@ -57,8 +57,8 @@ cpu3: cpu@3 {
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
......
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View file @ 2e9cf554
......@@ -300,8 +300,8 @@ da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
......@@ -312,8 +312,8 @@ da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
......@@ -374,8 +374,8 @@ &mmc0 {
mmc-hs400-1_8v;
cap-mmc-hw-reset;
hs400-ds-delay = <0x14015>;
mediatek,hs200-cmd-int-delay=<30>;
mediatek,hs400-cmd-int-delay=<14>;
mediatek,hs200-cmd-int-delay = <30>;
mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
......
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View file @ 2e9cf554
......@@ -122,8 +122,8 @@ da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
};
......@@ -132,8 +132,8 @@ da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
......@@ -148,8 +148,8 @@ &mmc0 {
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mediatek,hs200-cmd-int-delay=<26>;
mediatek,hs400-cmd-int-delay=<14>;
mediatek,hs200-cmd-int-delay = <26>;
mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
......
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file @ 2e9cf554
......@@ -246,9 +246,9 @@ pmu_a72 {
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
clk26m: oscillator0 {
......@@ -1505,7 +1505,7 @@ larb5: larb@19001000 {
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
......
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file @ 2e9cf554
......@@ -581,8 +581,8 @@ pmu-a73 {
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
compatible = "arm,psci-1.0";
method = "smc";
};
clk26m: oscillator {
......@@ -790,7 +790,7 @@ power-domain@MT8183_POWER_DOMAIN_CONN {
power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&topckgen CLK_TOP_MUX_MFG>;
clocks = <&topckgen CLK_TOP_MUX_MFG>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
......@@ -1448,7 +1448,7 @@ i2c8: i2c@1101b000 {
};
ssusb: usb@11201000 {
compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
......
arch/arm64/boot/dts/mediatek/mt8195-evb.dts
View file @ 2e9cf554
......@@ -139,19 +139,19 @@ pins {
};
&u3phy0 {
status="okay";
status = "okay";
};
&u3phy1 {
status="okay";
status = "okay";
};
&u3phy2 {
status="okay";
status = "okay";
};
&u3phy3 {
status="okay";
status = "okay";
};
&uart0 {
......
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