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Commit 4fda1e73 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'v4.14-rockchip-dts64-1' of... 

Merge tag 'v4.14-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Pull "Rockchip dts64 changes for 4.14" from Heiko Stübner:

64bit Rockchip devicetree changes containing fixes for pinctrl typos
and the use of keep-power-in-suspend in non-sdio nodes as well as the
removal of the deprecated num-slots property from dwmmc nodes.

rk3328 gets support for spdif, io-domains and usb (including enablement
of usb on the evaluation board), while rk3368 gains support for spdif.

The biggest chunk of course aims for the rk3399 with a number of pcie
changes, support for the mali gpu, a new power-domain, sdmmc support
on the firefly board and dynamic-power-coefficients.

The gru family also gets support for their quite central pwm regulators
using the newly introduced vctrl regulator types.

* tag 'v4.14-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: update dynamic-power-coefficient for rk3399
  arm64: dts: rockchip: add rk3328 spdif node
  arm64: dts: rockchip: add rk3368 spdif node
  arm64: dts: rockchip: enable sdmmc controller on rk3399-firefly
  arm64: dts: rockchip: Add rk3328 io-domain node
  arm64: dts: rockchip: kill pcie_clkreqn and pcie_clkreqnb for rk3399
  arm64: dts: rockchip: change clkreq mode for rk3399-firefly
  arm64: dts: rockchip: enable the GPU for RK3399-GRU
  arm64: dts: rockchip: add ARM Mali GPU node for RK3399 SoCs
  dt-bindings: gpu: add the RK3399 mali for rockchip specifics
  arm64: dts: rockchip: remove abused keep-power-in-suspend
  arm64: dts: rockchip: remove num-slots from all platforms
  arm64: dts: rockchip: change clkreq mode for rk3399-evb
  arm64: dts: rockchip: add SdioAudio pd control for rk3399
  arm64: dts: rockchip: enable usb2 for RK3328 evaluation board
  arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs
  arm64: dts: rockchip: set rk3399 dynamic CPU power coefficients
  arm64: dts: rockchip: Use vctrl regulators for dynamic CPU voltages on Gru/Kevin
  arm64: dts: rockchip: Update CPU regulator voltage ranges for Gru
  arm64: dts: rockchip: fix typo in mmc pinctrl
parents 77dcb02f 45a995c0
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Showing with 374 additions and 60 deletions
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
View file @ 4fda1e73
......@@ -17,6 +17,7 @@ Required properties:
* which must be preceded by one of the following vendor specifics:
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
- reg : Physical base address of the device and length of the register area.
......
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
View file @ 4fda1e73
......@@ -55,3 +55,27 @@ chosen {
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View file @ 4fda1e73
......@@ -156,12 +156,30 @@ xin24m: xin24m {
clock-output-names = "xin24m";
};
spdif: spdif@ff030000 {
compatible = "rockchip,rk3328-spdif";
reg = <0x0 0xff030000 0x0 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac 10>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdifm2_tx>;
status = "disabled";
};
grf: syscon@ff100000 {
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk3328-io-voltage-domain";
status = "disabled";
};
power: power-controller {
compatible = "rockchip,rk3328-power-controller";
#power-domain-cells = <1>;
......@@ -372,6 +390,43 @@ cru: clock-controller@ff440000 {
<32768>;
};
usb2phy_grf: syscon@ff450000 {
compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xff450000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy: usb2-phy@100 {
compatible = "rockchip,rk3328-usb2phy";
reg = <0x100 0x10>;
clocks = <&xin24m>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy";
#clock-cells = <0>;
assigned-clocks = <&cru USB480M>;
assigned-clock-parents = <&u2phy>;
status = "disabled";
u2phy_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
};
sdmmc: dwmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
......@@ -424,6 +479,45 @@ gmac2io: ethernet@ff540000 {
status = "disabled";
};
usb20_otg: usb@ff580000 {
compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x0 0xff580000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy>;
clock-names = "usbhost", "utmi";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
usb_host0_ohci: usb@ff5d0000 {
compatible = "generic-ohci";
reg = <0x0 0xff5d0000 0x0 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy>;
clock-names = "usbhost", "utmi";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
......
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
View file @ 4fda1e73
......@@ -156,7 +156,6 @@ &emmc {
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
......
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
View file @ 4fda1e73
......@@ -117,7 +117,6 @@ &emmc {
clock-frequency = <150000000>;
disable-wp;
non-removable;
num-slots = <1>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_flash>;
pinctrl-names = "default";
......
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
View file @ 4fda1e73
......@@ -203,7 +203,6 @@ &emmc {
mmc-hs200-1_2v;
mmc-hs200-1_8v;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
......@@ -347,7 +346,6 @@ &sdmmc {
max-frequency = <50000000>;
cap-sd-highspeed;
card-detect-delay = <200>;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
......
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
View file @ 4fda1e73
......@@ -86,12 +86,10 @@ &emmc {
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
keep-power-in-suspend;
mmc-hs200-1_8v;
no-sdio;
no-sd;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
vmmc-supply = <&vcc_io>;
......@@ -281,7 +279,6 @@ &sdmmc {
card-detect-delay = <200>;
no-emmc;
no-sdio;
num-slots = <1>;
sd-uhs-sdr12;
sd-uhs-sdr25;
pinctrl-names = "default";
......
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
View file @ 4fda1e73
......@@ -189,7 +189,6 @@ &emmc {
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
......@@ -254,7 +253,6 @@ &sdio0 {
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
vmmc-supply = <&vcc_io>;
......
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ 4fda1e73
......@@ -700,6 +700,19 @@ timer@ff810000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
spdif: spdif@ff880000 {
compatible = "rockchip,rk3368-spdif";
reg = <0x0 0xff880000 0x0 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
clock-names = "mclk", "hclk";
dmas = <&dmac_bus 3>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
status = "disabled";
};
i2s_2ch: i2s-2ch@ff890000 {
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
......@@ -1024,6 +1037,12 @@ sdmmc_bus4: sdmmc-bus4 {
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
......
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
View file @ 4fda1e73
......@@ -199,7 +199,7 @@ &pcie0 {
ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "disabled";
};
......
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
View file @ 4fda1e73
......@@ -550,7 +550,7 @@ &pcie0 {
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
......@@ -630,9 +630,20 @@ &saradc {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
keep-power-in-suspend;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
......
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
View file @ 4fda1e73
......@@ -264,6 +264,50 @@ touchscreen@4b {
};
};
&ppvar_bigcpu_pwm {
regulator-min-microvolt = <798674>;
regulator-max-microvolt = <1302172>;
};
&ppvar_bigcpu {
regulator-min-microvolt = <798674>;
regulator-max-microvolt = <1302172>;
ctrl-voltage-range = <798674 1302172>;
};
&ppvar_litcpu_pwm {
regulator-min-microvolt = <799065>;
regulator-max-microvolt = <1303738>;
};
&ppvar_litcpu {
regulator-min-microvolt = <799065>;
regulator-max-microvolt = <1303738>;
ctrl-voltage-range = <799065 1303738>;
};
&ppvar_gpu_pwm {
regulator-min-microvolt = <785782>;
regulator-max-microvolt = <1217729>;
};
&ppvar_gpu {
regulator-min-microvolt = <785782>;
regulator-max-microvolt = <1217729>;
ctrl-voltage-range = <785782 1217729>;
};
&ppvar_centerlogic_pwm {
regulator-min-microvolt = <800069>;
regulator-max-microvolt = <1049692>;
};
&ppvar_centerlogic {
regulator-min-microvolt = <800069>;
regulator-max-microvolt = <1049692>;
ctrl-voltage-range = <800069 1049692>;
};
&saradc {
status = "okay";
vref-supply = <&pp1800_ap_io>;
......
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View file @ 4fda1e73
......@@ -164,14 +164,9 @@ pp5000: pp5000 {
vin-supply = <&ppvar_sys>;
};
ppvar_bigcpu: ppvar-bigcpu {
ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_bigcpu";
/*
* OVP circuit requires special handling which is not yet
* represented. Keep disabled for now.
*/
status = "disabled";
regulator-name = "ppvar_bigcpu_pwm";
pwms = <&pwm1 0 3337 0>;
pwm-supply = <&ppvar_sys>;
......@@ -181,18 +176,28 @@ ppvar_bigcpu: ppvar-bigcpu {
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <798674>;
regulator-max-microvolt = <1302172>;
regulator-min-microvolt = <800107>;
regulator-max-microvolt = <1302232>;
};
ppvar_litcpu: ppvar-litcpu {
ppvar_bigcpu: ppvar-bigcpu {
compatible = "vctrl-regulator";
regulator-name = "ppvar_bigcpu";
regulator-min-microvolt = <800107>;
regulator-max-microvolt = <1302232>;
ctrl-supply = <&ppvar_bigcpu_pwm>;
ctrl-voltage-range = <800107 1302232>;
regulator-settling-time-up-us = <322>;
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
ppvar_litcpu_pwm: ppvar-litcpu-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_litcpu";
/*
* OVP circuit requires special handling which is not yet
* represented. Keep disabled for now.
*/
status = "disabled";
regulator-name = "ppvar_litcpu_pwm";
pwms = <&pwm2 0 3337 0>;
pwm-supply = <&ppvar_sys>;
......@@ -202,18 +207,28 @@ ppvar_litcpu: ppvar-litcpu {
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <799065>;
regulator-max-microvolt = <1303738>;
regulator-min-microvolt = <797743>;
regulator-max-microvolt = <1307837>;
};
ppvar_gpu: ppvar-gpu {
ppvar_litcpu: ppvar-litcpu {
compatible = "vctrl-regulator";
regulator-name = "ppvar_litcpu";
regulator-min-microvolt = <797743>;
regulator-max-microvolt = <1307837>;
ctrl-supply = <&ppvar_litcpu_pwm>;
ctrl-voltage-range = <797743 1307837>;
regulator-settling-time-up-us = <384>;
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
ppvar_gpu_pwm: ppvar-gpu-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_gpu";
/*
* OVP circuit requires special handling which is not yet
* represented. Keep disabled for now.
*/
status = "disabled";
regulator-name = "ppvar_gpu_pwm";
pwms = <&pwm0 0 3337 0>;
pwm-supply = <&ppvar_sys>;
......@@ -223,18 +238,28 @@ ppvar_gpu: ppvar-gpu {
/* EC turns on w/ ap_core_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <785782>;
regulator-max-microvolt = <1217729>;
regulator-min-microvolt = <786384>;
regulator-max-microvolt = <1217747>;
};
ppvar_centerlogic: ppvar-centerlogic {
ppvar_gpu: ppvar-gpu {
compatible = "vctrl-regulator";
regulator-name = "ppvar_gpu";
regulator-min-microvolt = <786384>;
regulator-max-microvolt = <1217747>;
ctrl-supply = <&ppvar_gpu_pwm>;
ctrl-voltage-range = <786384 1217747>;
regulator-settling-time-up-us = <390>;
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
ppvar_centerlogic_pwm: ppvar-centerlogic-pwm {
compatible = "pwm-regulator";
regulator-name = "ppvar_centerlogic";
/*
* OVP circuit requires special handling which is not yet
* represented. Keep disabled for now.
*/
status = "disabled";
regulator-name = "ppvar_centerlogic_pwm";
pwms = <&pwm3 0 3337 0>;
pwm-supply = <&ppvar_sys>;
......@@ -244,8 +269,23 @@ ppvar_centerlogic: ppvar-centerlogic {
/* EC turns on w/ ppvar_centerlogic_en; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800069>;
regulator-max-microvolt = <1049692>;
regulator-min-microvolt = <799434>;
regulator-max-microvolt = <1049925>;
};
ppvar_centerlogic: ppvar-centerlogic {
compatible = "vctrl-regulator";
regulator-name = "ppvar_centerlogic";
regulator-min-microvolt = <799434>;
regulator-max-microvolt = <1049925>;
ctrl-supply = <&ppvar_centerlogic_pwm>;
ctrl-voltage-range = <799434 1049925>;
regulator-settling-time-up-us = <378>;
min-slew-down-rate = <225>;
ovp-threshold-percent = <16>;
};
/* Schematics call this PPVAR even though it's fixed */
......@@ -555,6 +595,11 @@ &emmc_phy {
status = "okay";
};
&gpu {
mali-supply = <&ppvar_gpu>;
status = "okay";
};
ap_i2c_mic: &i2c1 {
status = "okay";
......@@ -1031,7 +1076,7 @@ sdmmc_cmd: sdmmc-cmd {
* hurt and dw_mmc will ignore it. We make sure to disable
* the pull though so we don't burn needless power.
*/
sdmmc_cd: sdmcc-cd {
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 7 RK_FUNC_1 &pcfg_pull_none>;
};
......
arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
View file @ 4fda1e73
......@@ -118,6 +118,35 @@ opp08 {
opp-microvolt = <1250000>;
};
};
gpu_opp_table: opp-table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <800000>;
};
opp01 {
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <825000>;
};
opp03 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <850000>;
};
opp04 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <925000>;
};
opp05 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1075000>;
};
};
};
&cpu_l0 {
......@@ -143,3 +172,7 @@ &cpu_b0 {
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
View file @ 4fda1e73
......@@ -110,6 +110,35 @@ opp07 {
opp-microvolt = <1200000>;
};
};
gpu_opp_table: opp-table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <800000>;
};
opp01 {
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <825000>;
};
opp03 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <875000>;
};
opp04 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <925000>;
};
opp05 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1100000>;
};
};
};
&cpu_l0 {
......@@ -135,3 +164,7 @@ &cpu_b0 {
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file @ 4fda1e73
......@@ -110,6 +110,7 @@ cpu_l0: cpu@0 {
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
dynamic-power-coefficient = <100>;
};
cpu_l1: cpu@1 {
......@@ -118,6 +119,7 @@ cpu_l1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
dynamic-power-coefficient = <100>;
};
cpu_l2: cpu@2 {
......@@ -126,6 +128,7 @@ cpu_l2: cpu@2 {
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
dynamic-power-coefficient = <100>;
};
cpu_l3: cpu@3 {
......@@ -134,6 +137,7 @@ cpu_l3: cpu@3 {
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
dynamic-power-coefficient = <100>;
};
cpu_b0: cpu@100 {
......@@ -143,6 +147,7 @@ cpu_b0: cpu@100 {
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
dynamic-power-coefficient = <436>;
};
cpu_b1: cpu@101 {
......@@ -151,6 +156,7 @@ cpu_b1: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
dynamic-power-coefficient = <436>;
};
};
......@@ -287,6 +293,7 @@ sdio0: dwmmc@fe310000 {
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
resets = <&cru SRST_SDIO0>;
reset-names = "reset";
status = "disabled";
......@@ -676,6 +683,7 @@ spi5: spi@ff200000 {
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
......@@ -965,6 +973,11 @@ pd_sd@RK3399_PD_SD {
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sd>;
};
pd_sdioaudio@RK3399_PD_SDIOAUDIO {
reg = <RK3399_PD_SDIOAUDIO>;
clocks = <&cru HCLK_SDIO>;
pm_qos = <&qos_sdioaudio>;
};
pd_vio@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
#address-cells = <1>;
......@@ -1385,6 +1398,7 @@ spdif: spdif@ff870000 {
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
......@@ -1399,6 +1413,7 @@ i2s0: i2s@ff880000 {
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
......@@ -1412,6 +1427,7 @@ i2s1: i2s@ff890000 {
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
......@@ -1423,6 +1439,19 @@ i2s2: i2s@ff8a0000 {
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
status = "disabled";
};
gpu: gpu@ff9a0000 {
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
reg = <0x0 0xff9a0000 0x0 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "gpu", "job", "mmu";
clocks = <&cru ACLK_GPU>;
power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
......@@ -1786,7 +1815,7 @@ sdmmc_cmd: sdmmc-cmd {
<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_cd: sdmcc-cd {
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
};
......@@ -2090,16 +2119,6 @@ hdmi_cec: hdmi-cec {
};
pcie {
pcie_clkreqn: pci-clkreqn {
rockchip,pins =
<2 26 RK_FUNC_2 &pcfg_pull_none>;
};
pcie_clkreqnb: pci-clkreqnb {
rockchip,pins =
<4 24 RK_FUNC_1 &pcfg_pull_none>;
};
pcie_clkreqn_cpm: pci-clkreqn-cpm {
rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
......
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