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Commit 8c11fcc2 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu into next/dt 

Pull "mvebu dt64 for 4.16 (part 2)" from Gregory CLEMENT:

The main change here are the series of commits doing the Armada 7K/8K
CP110 DT de-duplication, they include the de-duplication itself and
small fixes in the device tree files.

Besides them there are 2 other patches:
 - One adding the crypto support for Armada 37xx SoCs
 - An other adding Ethernet aliases on A7K/A8K base boards

* tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add Ethernet aliases
  arm64: dts: marvell: replace cpm by cp0, cps by cp1
  arm64: dts: marvell: de-duplicate CP110 description
  arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
  arm64: dts: marvell: use mvebu-icu.h where possible
  arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
  arm64: dts: marvell: fix typos in comment describing the NAND controller
  arm64: dts: marvell: use lower case for unit address and reg property
  arm64: dts: marvell: fix watchdog unit address in Armada AP806
  arm64: dts: marvell: armada-37xx: add a crypto node
  ARM64: dts: marvell: armada-cp110: Fix clock resources for various node
  ARM: dts: kirkwood: fix pin-muxing of MPP7 on OpenBlocks A7
parents c503f594 474c5885
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Showing with 678 additions and 1027 deletions
arch/arm/boot/dts/kirkwood-openblocks_a7.dts
View file @ 8c11fcc2
......@@ -53,7 +53,8 @@ s24c02: s24c02@50 {
};
pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
&pmx_gpio_header_gpo>;
pinctrl-names = "default";
pmx_uart0: pmx-uart0 {
......@@ -85,11 +86,16 @@ pmx_dip_switches: pmx-dip-switches {
* ground.
*/
pmx_gpio_header: pmx-gpio-header {
marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
marvell,pins = "mpp17", "mpp29", "mpp28",
"mpp35", "mpp34", "mpp40";
marvell,function = "gpio";
};
pmx_gpio_header_gpo: pxm-gpio-header-gpo {
marvell,pins = "mpp7";
marvell,function = "gpo";
};
pmx_gpio_init: pmx-init {
marvell,pins = "mpp38";
marvell,function = "gpio";
......
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View file @ 8c11fcc2
......@@ -316,6 +316,20 @@ xor11 {
};
};
crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&nb_periph_clk 15>;
};
sdhci1: sdhci@d0000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
......
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View file @ 8c11fcc2
......@@ -61,7 +61,13 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
};
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h0-vbus";
regulator-min-microvolt = <5000000>;
......@@ -70,7 +76,7 @@ cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h1-vbus";
regulator-min-microvolt = <5000000>;
......@@ -79,14 +85,14 @@ cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
cpm_usb3_0_phy: cpm-usb3-0-phy {
cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_0_vbus>;
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
cpm_usb3_1_phy: cpm-usb3-1-phy {
cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_1_vbus>;
vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
};
......@@ -129,11 +135,11 @@ &uart0 {
};
&cpm_pcie2 {
&cp0_pcie2 {
status = "okay";
};
&cpm_i2c0 {
&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
......@@ -156,7 +162,7 @@ expander0: pca9555@21 {
};
};
&cpm_nand {
&cp0_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
......@@ -186,7 +192,7 @@ partition@1000000 {
};
&cpm_spi1 {
&cp0_spi1 {
status = "okay";
spi-flash@0 {
......@@ -214,17 +220,17 @@ partition@400000 {
};
};
&cpm_sata0 {
&cp0_sata0 {
status = "okay";
};
&cpm_usb3_0 {
usb-phy = <&cpm_usb3_0_phy>;
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
&cpm_usb3_1 {
usb-phy = <&cpm_usb3_1_phy>;
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
......@@ -235,14 +241,14 @@ &ap_sdhci0 {
non-removable;
};
&cpm_sdhci0 {
&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
&cpm_mdio {
&cp0_mdio {
status = "okay";
phy0: ethernet-phy@0 {
......@@ -253,28 +259,28 @@ phy1: ethernet-phy@1 {
};
};
&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};
&cpm_eth0 {
&cp0_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy2 0>;
phys = <&cp0_comphy2 0>;
};
&cpm_eth1 {
&cp0_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy0 1>;
phys = <&cp0_comphy0 1>;
};
&cpm_eth2 {
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
......
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View file @ 8c11fcc2
......@@ -44,25 +44,46 @@
* Device Tree file for the Armada 70x0 SoC
*/
#include "armada-cp110-master.dtsi"
/ {
aliases {
gpio1 = &cpm_gpio1;
gpio2 = &cpm_gpio2;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
};
};
&cpm_gpio1 {
/*
* Instantiate the CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
&cp0_gpio1 {
status = "okay";
};
&cpm_gpio2 {
&cp0_gpio2 {
status = "okay";
};
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
nand_pins: nand-pins {
......
arch/arm64/boot/dts/marvell/armada-8020.dtsi
View file @ 8c11fcc2
......@@ -60,6 +60,6 @@ / {
* oscillator so this one is let enabled.
*/
&cpm_rtc {
&cp0_rtc {
status = "disabled";
};
arch/arm64/boot/dts/marvell/armada-8040-db.dts
View file @ 8c11fcc2
......@@ -61,46 +61,53 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth2;
ethernet2 = &cp1_eth0;
ethernet3 = &cp1_eth1;
};
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cpm-usb3h0-vbus";
regulator-name = "cp0-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "cpm-usb3h1-vbus";
regulator-name = "cp0-usb3h1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
cpm_usb3_0_phy: cpm-usb3-0-phy {
cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_0_vbus>;
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
cpm_usb3_1_phy: cpm-usb3-1-phy {
cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_1_vbus>;
vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cps-usb3h0-vbus";
regulator-name = "cp1-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
};
cps_usb3_0_phy: cps-usb3-0-phy {
cp1_usb3_0_phy: cp1-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cps_reg_usb3_0_vbus>;
vcc-supply = <&cp1_reg_usb3_0_vbus>;
};
};
......@@ -144,16 +151,16 @@ &uart0 {
};
/* CON6 on CP0 expansion */
&cpm_pcie0 {
&cp0_pcie0 {
status = "okay";
};
/* CON5 on CP0 expansion */
&cpm_pcie2 {
&cp0_pcie2 {
status = "okay";
};
&cpm_i2c0 {
&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
......@@ -178,23 +185,23 @@ expander1: pca9555@25 {
};
/* CON4 on CP0 expansion */
&cpm_sata0 {
&cp0_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
&cpm_usb3_0 {
usb-phy = <&cpm_usb3_0_phy>;
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP0 expansion */
&cpm_usb3_1 {
usb-phy = <&cpm_usb3_1_phy>;
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
&cpm_mdio {
&cp0_mdio {
status = "okay";
phy1: ethernet-phy@1 {
......@@ -202,42 +209,42 @@ phy1: ethernet-phy@1 {
};
};
&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};
&cpm_eth0 {
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cpm_eth2 {
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON6 on CP1 expansion */
&cps_pcie0 {
&cp1_pcie0 {
status = "okay";
};
/* CON7 on CP1 expansion */
&cps_pcie1 {
&cp1_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
&cps_pcie2 {
&cp1_pcie2 {
status = "okay";
};
&cps_i2c0 {
&cp1_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&cps_spi1 {
&cp1_spi1 {
status = "okay";
spi-flash@0 {
......@@ -272,14 +279,14 @@ partition@f00000 {
* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
* MDIO signal of CP1.
*/
&cps_nand {
&cp1_nand {
num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
marvell,system-controller = <&cps_syscon0>;
marvell,system-controller = <&cp1_syscon0>;
nand-on-flash-bbt;
partition@0 {
......@@ -297,22 +304,22 @@ partition@1000000 {
};
/* CON4 on CP1 expansion */
&cps_sata0 {
&cp1_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
&cps_usb3_0 {
usb-phy = <&cps_usb3_0_phy>;
&cp1_usb3_0 {
usb-phy = <&cp1_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP1 expansion */
&cps_usb3_1 {
&cp1_usb3_1 {
status = "okay";
};
&cps_mdio {
&cp1_mdio {
status = "okay";
phy0: ethernet-phy@0 {
......@@ -320,16 +327,16 @@ phy0: ethernet-phy@0 {
};
};
&cps_ethernet {
&cp1_ethernet {
status = "okay";
};
&cps_eth0 {
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cps_eth1 {
&cp1_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
......@@ -341,7 +348,7 @@ &ap_sdhci0 {
non-removable;
};
&cpm_sdhci0 {
&cp0_sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
......
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
View file @ 8c11fcc2
......@@ -62,6 +62,12 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp1_eth0;
ethernet2 = &cp1_eth1;
};
/* Regulator labels correspond with schematics */
v_3_3: regulator-3-3v {
compatible = "regulator-fixed";
......@@ -84,9 +90,9 @@ v_vddo_h: regulator-1-8v {
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_xhci_vbus_pins>;
pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
......@@ -120,17 +126,17 @@ &ap_sdhci0 {
vqmmc-supply = <&v_vddo_h>;
};
&cpm_i2c0 {
&cp0_i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_i2c0_pins>;
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
};
&cpm_i2c1 {
&cp0_i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_i2c1_pins>;
pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
i2c-switch@70 {
......@@ -157,9 +163,9 @@ sfp_1g_i2c: i2c@2 {
};
};
&cpm_mdio {
&cp0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&cpm_ge_mdio_pins>;
pinctrl-0 = <&cp0_ge_mdio_pins>;
status = "okay";
ge_phy: ethernet-phy@0 {
......@@ -167,44 +173,44 @@ ge_phy: ethernet-phy@0 {
};
};
&cpm_pcie0 {
&cp0_pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_pins>;
pinctrl-0 = <&cp0_pcie_pins>;
num-lanes = <4>;
num-viewport = <8>;
reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
&cpm_pinctrl {
cpm_ge_mdio_pins: ge-mdio-pins {
&cp0_pinctrl {
cp0_ge_mdio_pins: ge-mdio-pins {
marvell,pins = "mpp32", "mpp34";
marvell,function = "ge";
};
cpm_i2c1_pins: i2c1-pins {
cp0_i2c1_pins: i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cpm_i2c0_pins: i2c0-pins {
cp0_i2c0_pins: i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cpm_xhci_vbus_pins: xhci0-vbus-pins {
cp0_xhci_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cpm_pcie_pins: pcie-pins {
cp0_pcie_pins: pcie-pins {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
cpm_sdhci_pins: sdhci-pins {
cp0_sdhci_pins: sdhci-pins {
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
"mpp60", "mpp61";
marvell,function = "sdio";
};
};
&cpm_xmdio {
&cp0_xmdio {
status = "okay";
phy0: ethernet-phy@0 {
......@@ -218,83 +224,83 @@ phy8: ethernet-phy@8 {
};
};
&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};
&cpm_eth0 {
&cp0_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy4 0>;
phys = <&cp0_comphy4 0>;
};
&cpm_sata0 {
&cp0_sata0 {
/* CPM Lane 0 - U29 */
status = "okay";
};
&cpm_sdhci0 {
&cp0_sdhci0 {
/* U6 */
broken-cd;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_sdhci_pins>;
pinctrl-0 = <&cp0_sdhci_pins>;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
&cpm_usb3_0 {
&cp0_usb3_0 {
/* J38? - USB2.0 only */
status = "okay";
};
&cpm_usb3_1 {
&cp0_usb3_1 {
/* J38? - USB2.0 only */
status = "okay";
};
&cps_ethernet {
&cp1_ethernet {
status = "okay";
};
&cps_eth0 {
&cp1_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy4 0>;
phys = <&cp1_comphy4 0>;
};
&cps_eth1 {
&cp1_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
/* Network PHY */
phy = <&ge_phy>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy0 1>;
phys = <&cp1_comphy0 1>;
};
&cps_pinctrl {
cps_spi1_pins: spi1-pins {
&cp1_pinctrl {
cp1_spi1_pins: spi1-pins {
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
&cps_sata0 {
&cp1_sata0 {
/* CPS Lane 1 - U32 */
/* CPS Lane 3 - U31 */
status = "okay";
};
&cps_spi1 {
&cp1_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cps_spi1_pins>;
pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
......@@ -304,7 +310,7 @@ spi-flash@0 {
};
};
&cps_usb3_0 {
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
usb-phy = <&usb3h0_phy>;
status = "okay";
......
arch/arm64/boot/dts/marvell/armada-8040.dtsi
View file @ 8c11fcc2
......@@ -59,6 +59,6 @@ / {
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
&cpm_rtc {
&cp0_rtc {
status = "disabled";
};
arch/arm64/boot/dts/marvell/armada-80x0.dtsi
View file @ 8c11fcc2
......@@ -44,34 +44,77 @@
* Device Tree file for the Armada 80x0 SoC family
*/
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
/ {
aliases {
gpio1 = &cps_gpio1;
gpio2 = &cpm_gpio2;
gpio1 = &cp1_gpio1;
gpio2 = &cp0_gpio2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
spi3 = &cp1_spi0;
spi4 = &cp1_spi1;
};
};
/*
* Instantiate the master CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
/*
* Instantiate the slave CP110
*/
#define CP110_NAME cp1
#define CP110_BASE f4000000
#define CP110_PCIE_IO_BASE 0xfd000000
#define CP110_PCIE_MEM_BASE 0xfa000000
#define CP110_PCIE0_BASE f4600000
#define CP110_PCIE1_BASE f4620000
#define CP110_PCIE2_BASE f4640000
#include "armada-cp110.dtsi"
#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
/* The 80x0 has two CP blocks, but uses only one block from each. */
&cps_gpio1 {
&cp1_gpio1 {
status = "okay";
};
&cpm_gpio2 {
&cp0_gpio2 {
status = "okay";
};
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cp0-pinctrl";
};
};
&cps_syscon0 {
cps_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cps-pinctrl";
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cp1-pinctrl";
nand_pins: nand-pins {
marvell,pins =
......@@ -91,3 +134,14 @@ nand_rb: nand-rb {
};
};
};
&cp1_crypto {
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC
* level. Because it is not possible as of now
* to enable two cryptographic engines in
* parallel, disable this one by default.
*/
status = "disabled";
};
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file @ 8c11fcc2
......@@ -58,6 +58,7 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
gpio0 = &ap_gpio;
spi0 = &spi0;
};
psci {
......@@ -203,7 +204,6 @@ spi0: spi@510600 {
reg = <0x510600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk 3>;
status = "disabled";
......@@ -241,7 +241,7 @@ uart1: serial@512100 {
};
watchdog: watchdog@600000 {
watchdog: watchdog@610000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -286,9 +286,9 @@ ap_gpio: gpio@1040 {
};
};
ap_thermal: thermal@6f808C {
ap_thermal: thermal@6f808c {
compatible = "marvell,armada-ap806-thermal";
reg = <0x6f808C 0x4>,
reg = <0x6f808c 0x4>,
<0x6f8084 0x8>;
};
};
......
arch/arm64/boot/dts/marvell/armada-common.dtsi 0 → 100644
View file @ 8c11fcc2
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*/
/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi deleted 100644 → 0
View file @ c503f594
This diff is collapsed.
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi deleted 100644 → 0
View file @ c503f594
This diff is collapsed.
arch/arm64/boot/dts/marvell/armada-cp110.dtsi 0 → 100644
View file @ 8c11fcc2
This diff is collapsed.
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