Commit 93830ef7 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson

arm64: dts: qcom: sc8280xp: describe USB signals properly

Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-7-ad153c747a97@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 757688ad
...@@ -56,7 +56,7 @@ port@0 { ...@@ -56,7 +56,7 @@ port@0 {
reg = <0>; reg = <0>;
pmic_glink_con0_hs: endpoint { pmic_glink_con0_hs: endpoint {
remote-endpoint = <&usb_0_role_switch>; remote-endpoint = <&usb_0_dwc3_hs>;
}; };
}; };
...@@ -91,7 +91,7 @@ port@0 { ...@@ -91,7 +91,7 @@ port@0 {
reg = <0>; reg = <0>;
pmic_glink_con1_hs: endpoint { pmic_glink_con1_hs: endpoint {
remote-endpoint = <&usb_1_role_switch>; remote-endpoint = <&usb_1_dwc3_hs>;
}; };
}; };
...@@ -675,6 +675,10 @@ &usb_0_dwc3 { ...@@ -675,6 +675,10 @@ &usb_0_dwc3 {
dr_mode = "host"; dr_mode = "host";
}; };
&usb_0_dwc3_hs {
remote-endpoint = <&pmic_glink_con0_hs>;
};
&usb_0_hsphy { &usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>; vdda18-supply = <&vreg_l1c>;
...@@ -700,10 +704,6 @@ &usb_0_qmpphy_out { ...@@ -700,10 +704,6 @@ &usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>; remote-endpoint = <&pmic_glink_con0_ss>;
}; };
&usb_0_role_switch {
remote-endpoint = <&pmic_glink_con0_hs>;
};
&usb_1 { &usb_1 {
status = "okay"; status = "okay";
}; };
...@@ -712,6 +712,10 @@ &usb_1_dwc3 { ...@@ -712,6 +712,10 @@ &usb_1_dwc3 {
dr_mode = "host"; dr_mode = "host";
}; };
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_con1_hs>;
};
&usb_1_hsphy { &usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>; vdda18-supply = <&vreg_l1c>;
...@@ -737,10 +741,6 @@ &usb_1_qmpphy_out { ...@@ -737,10 +741,6 @@ &usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>; remote-endpoint = <&pmic_glink_con1_ss>;
}; };
&usb_1_role_switch {
remote-endpoint = <&pmic_glink_con1_hs>;
};
&xo_board_clk { &xo_board_clk {
clock-frequency = <38400000>; clock-frequency = <38400000>;
}; };
......
...@@ -117,7 +117,7 @@ port@0 { ...@@ -117,7 +117,7 @@ port@0 {
reg = <0>; reg = <0>;
pmic_glink_con0_hs: endpoint { pmic_glink_con0_hs: endpoint {
remote-endpoint = <&usb_0_role_switch>; remote-endpoint = <&usb_0_dwc3_hs>;
}; };
}; };
...@@ -152,7 +152,7 @@ port@0 { ...@@ -152,7 +152,7 @@ port@0 {
reg = <0>; reg = <0>;
pmic_glink_con1_hs: endpoint { pmic_glink_con1_hs: endpoint {
remote-endpoint = <&usb_1_role_switch>; remote-endpoint = <&usb_1_dwc3_hs>;
}; };
}; };
...@@ -1131,6 +1131,10 @@ &usb_0_dwc3 { ...@@ -1131,6 +1131,10 @@ &usb_0_dwc3 {
dr_mode = "host"; dr_mode = "host";
}; };
&usb_0_dwc3_hs {
remote-endpoint = <&pmic_glink_con0_hs>;
};
&usb_0_hsphy { &usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>; vdda18-supply = <&vreg_l1c>;
...@@ -1156,10 +1160,6 @@ &usb_0_qmpphy_out { ...@@ -1156,10 +1160,6 @@ &usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>; remote-endpoint = <&pmic_glink_con0_ss>;
}; };
&usb_0_role_switch {
remote-endpoint = <&pmic_glink_con0_hs>;
};
&usb_1 { &usb_1 {
status = "okay"; status = "okay";
}; };
...@@ -1168,6 +1168,10 @@ &usb_1_dwc3 { ...@@ -1168,6 +1168,10 @@ &usb_1_dwc3 {
dr_mode = "host"; dr_mode = "host";
}; };
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_con1_hs>;
};
&usb_1_hsphy { &usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>; vdda18-supply = <&vreg_l1c>;
...@@ -1193,10 +1197,6 @@ &usb_1_qmpphy_out { ...@@ -1193,10 +1197,6 @@ &usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>; remote-endpoint = <&pmic_glink_con1_ss>;
}; };
&usb_1_role_switch {
remote-endpoint = <&pmic_glink_con1_hs>;
};
&usb_2 { &usb_2 {
status = "okay"; status = "okay";
}; };
......
...@@ -3222,6 +3222,14 @@ port@0 { ...@@ -3222,6 +3222,14 @@ port@0 {
usb_0_qmpphy_out: endpoint {}; usb_0_qmpphy_out: endpoint {};
}; };
port@1 {
reg = <1>;
usb_0_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_0_dwc3_ss>;
};
};
port@2 { port@2 {
reg = <2>; reg = <2>;
...@@ -3275,6 +3283,14 @@ port@0 { ...@@ -3275,6 +3283,14 @@ port@0 {
usb_1_qmpphy_out: endpoint {}; usb_1_qmpphy_out: endpoint {};
}; };
port@1 {
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_dwc3_ss>;
};
};
port@2 { port@2 {
reg = <2>; reg = <2>;
...@@ -3560,8 +3576,23 @@ usb_0_dwc3: usb@a600000 { ...@@ -3560,8 +3576,23 @@ usb_0_dwc3: usb@a600000 {
phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy"; phy-names = "usb2-phy", "usb3-phy";
port { ports {
usb_0_role_switch: endpoint { #address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_0_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_0_dwc3_ss: endpoint {
remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
};
}; };
}; };
}; };
...@@ -3622,8 +3653,23 @@ usb_1_dwc3: usb@a800000 { ...@@ -3622,8 +3653,23 @@ usb_1_dwc3: usb@a800000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy"; phy-names = "usb2-phy", "usb3-phy";
port { ports {
usb_1_role_switch: endpoint { #address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
}; };
}; };
}; };
......
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