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Commit 9f1a2068 authored by Russell King's avatar Russell King
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Convert ARM92x/ARM1020 specific configuration symbols to generic CPU 

symbols.  Remove unused flush_page_to_ram in ARM code.
parent 1b00b832
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Showing with 141 additions and 425 deletions
arch/arm/Config.help
View file @ 9f1a2068
...@@ -678,23 +678,6 @@ CONFIG_CPU_ARM922T ...@@ -678,23 +678,6 @@ CONFIG_CPU_ARM922T
Say Y if you want support for the ARM922T processor. Say Y if you want support for the ARM922T processor.
Otherwise, say N. Otherwise, say N.
CONFIG_CPU_ARM922_CPU_IDLE
Saying Y here will allow the processor to enter a low power
mode whilst waiting for an interrupt in idle. If you're unsure
say Y.
CONFIG_CPU_ARM922_I_CACHE_ON
Say Y here to enable the processor instruction cache. Unless
you have a reason not to, say Y.
CONFIG_CPU_ARM922_D_CACHE_ON
Say Y here to enable the processor data cache. Unless
you have a reason not to, say Y.
CONFIG_CPU_ARM922_WRITETHROUGH
Say Y here to use the data cache in writethough mode. Unless you
specifically require this, say N.
CONFIG_CPU_ARM1020 CONFIG_CPU_ARM1020
The ARM1020 is the cached version of the ARM10 processor, The ARM1020 is the cached version of the ARM10 processor,
with an addition of a floating-point unit. with an addition of a floating-point unit.
...@@ -711,6 +694,25 @@ CONFIG_CPU_SA110 ...@@ -711,6 +694,25 @@ CONFIG_CPU_SA110
Say Y if you want support for the SA-110 processor. Say Y if you want support for the SA-110 processor.
Otherwise, say N. Otherwise, say N.
CONFIG_CPU_ICACHE_DISABLE
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
CONFIG_CPU_DCACHE_DISABLE
Say Y here to disable the processor data cache. Unless
you have a reason not to or are unsure, say N.
CONFIG_CPU_DCACHE_WRITETHROUGH
Say Y here to use the data cache in writethough mode. Unless you
specifically require this or are unsure, say N.
CONFIG_CPU_CACHE_ROUND_ROBIN
Say Y here to use the predictable round-robin cache replacement
policy. Unless you specifically require this or are unsure, say N.
CONFIG_CPU_BPREDICT_DISABLE
Say Y here to disable branch prediction. If unsure, say N.
CONFIG_FPE_NWFPE CONFIG_FPE_NWFPE
Say Y to include the NWFPE floating point emulator in the kernel. Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently This is necessary to run most binaries. Linux does not currently
......
arch/arm/config.in
View file @ 9f1a2068
...@@ -218,7 +218,7 @@ fi ...@@ -218,7 +218,7 @@ fi
comment 'Processor Type' comment 'Processor Type'
# Firstly, figure out what processor architecture version we should be using. # Firstly, figure out what processor architecture version we should be using.
# This depends more on the machine type than anything else. # This defines the compiler instruction set which depends on the machine type.
if [ "$CONFIG_ARCH_RPC" = "y" -o "$CONFIG_ARCH_CLPS7500" = "y" ]; then if [ "$CONFIG_ARCH_RPC" = "y" -o "$CONFIG_ARCH_CLPS7500" = "y" ]; then
define_bool CONFIG_CPU_32v3 y define_bool CONFIG_CPU_32v3 y
...@@ -235,10 +235,15 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \ ...@@ -235,10 +235,15 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \
else else
define_bool CONFIG_CPU_32v4 n define_bool CONFIG_CPU_32v4 n
fi fi
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then
define_bool CONFIG_CPU_32v5 y
else
define_bool CONFIG_CPU_32v5 n
fi
# Select CPU types depending on the architecture selected. # Select CPU types depending on the architecture selected. This selects
# We use this to select which CPUs are supported, and to select # which CPUs we support in the kernel image, and the compiler instruction
# the compiler tuning options. # optimiser behaviour.
# ARM610 # ARM610
if [ "$CONFIG_ARCH_RPC" = "y" ]; then if [ "$CONFIG_ARCH_RPC" = "y" ]; then
...@@ -277,14 +282,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then ...@@ -277,14 +282,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
else else
define_bool CONFIG_CPU_ARM920T n define_bool CONFIG_CPU_ARM920T n
fi fi
if [ "$CONFIG_CPU_ARM920T" = "y" ]; then
bool ' ARM920T CPU idle' CONFIG_CPU_ARM920_CPU_IDLE
bool ' ARM920T I-Cache on' CONFIG_CPU_ARM920_I_CACHE_ON
bool ' ARM920T D-Cache on' CONFIG_CPU_ARM920_D_CACHE_ON
if [ "$CONFIG_CPU_ARM920_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM920T' CONFIG_CPU_ARM920_WRITETHROUGH
fi
fi
# ARM922T # ARM922T
if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then
...@@ -292,14 +289,6 @@ if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then ...@@ -292,14 +289,6 @@ if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then
else else
define_bool CONFIG_CPU_ARM922T n define_bool CONFIG_CPU_ARM922T n
fi fi
if [ "$CONFIG_CPU_ARM922T" = "y" ]; then
bool ' ARM922T CPU idle' CONFIG_CPU_ARM922_CPU_IDLE
bool ' ARM922T I-Cache on' CONFIG_CPU_ARM922_I_CACHE_ON
bool ' ARM922T D-Cache on' CONFIG_CPU_ARM922_D_CACHE_ON
if [ "$CONFIG_CPU_ARM922_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM922T' CONFIG_CPU_ARM922_WRITETHROUGH
fi
fi
# ARM926T # ARM926T
if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
...@@ -307,18 +296,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then ...@@ -307,18 +296,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
else else
define_bool CONFIG_CPU_ARM926T n define_bool CONFIG_CPU_ARM926T n
fi fi
if [ "$CONFIG_CPU_ARM926T" = "y" ]; then
bool ' ARM926T CPU idle' CONFIG_CPU_ARM926_CPU_IDLE
bool ' ARM926T I-Cache on' CONFIG_CPU_ARM926_I_CACHE_ON
bool ' ARM926T D-Cache on' CONFIG_CPU_ARM926_D_CACHE_ON
if [ "$CONFIG_CPU_ARM926_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM926T' CONFIG_CPU_ARM926_WRITETHROUGH
fi
if [ "$CONFIG_CPU_ARM926_I_CACHE_ON" = "y" -o \
"$CONFIG_CPU_ARM926_D_CACHE_ON" = "y" ]; then
bool ' Round robin I and D cache replacement algorithm' CONFIG_CPU_ARM926_ROUND_ROBIN
fi
fi
# ARM1020 # ARM1020
if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
...@@ -326,17 +303,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then ...@@ -326,17 +303,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
else else
define_bool CONFIG_CPU_ARM1020 n define_bool CONFIG_CPU_ARM1020 n
fi fi
if [ "$CONFIG_CPU_ARM1020" = "y" ]; then
bool ' ARM1020 I-Cache on' CONFIG_CPU_ARM1020_I_CACHE_ON
bool ' ARM10 D-Cache on' CONFIG_CPU_ARM1020_D_CACHE_ON
if [ "$CONFIG_CPU_ARM1020_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM1020' CONFIG_CPU_ARM1020_FORCE_WRITE_THROUGH
fi
if [ "$CONFIG_CPU_ARM1020_I_CACHE_ON" = "y" -o \
"$CONFIG_CPU_ARM1020_D_CACHE_ON" = "y" ]; then
bool ' Round robin I and D cache replacement algorithm' CONFIG_CPU_ARM1020_ROUND_ROBIN
fi
fi
# SA110 # SA110
if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \
...@@ -360,8 +326,9 @@ fi ...@@ -360,8 +326,9 @@ fi
# XScale # XScale
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then
define_bool CONFIG_CPU_32v5 y
define_bool CONFIG_CPU_XSCALE y define_bool CONFIG_CPU_XSCALE y
else
define_bool CONFIG_CPU_XSCALE n
fi fi
#if [ "$CONFIG_CPU_XSCALE" = "y" ]; then #if [ "$CONFIG_CPU_XSCALE" = "y" ]; then
...@@ -374,9 +341,34 @@ else ...@@ -374,9 +341,34 @@ else
define_bool CONFIG_XSCALE_PMU n define_bool CONFIG_XSCALE_PMU n
fi fi
if [ "$CONFIG_CPU_32" = "y" ]; then comment 'Processor Features'
if [ "$CONFIG_CPU_ARM720T" = "y" -o "$CONFIG_CPU_ARM920T" = "y" -o \
"$CONFIG_CPU_ARM922T" = "y" -o "$CONFIG_CPU_ARM926T" = "y" -o \
"$CONFIG_CPU_ARM1020" = "y" -o "$CONFIG_CPU_XSCALE" = "y" ]; then
dep_bool 'Support Thumb instructions (experimental)' CONFIG_ARM_THUMB $CONFIG_EXPERIMENTAL dep_bool 'Support Thumb instructions (experimental)' CONFIG_ARM_THUMB $CONFIG_EXPERIMENTAL
fi fi
if [ "$CONFIG_CPU_ARM920T" = "y" -o "$CONFIG_CPU_ARM922T" = "y" -o \
"$CONFIG_CPU_ARM926T" = "y" -o "$CONFIG_CPU_ARM1020" = "y" ]; then
bool 'Disable I-Cache' CONFIG_CPU_ICACHE_DISABLE
bool 'Disable D-Cache' CONFIG_CPU_DCACHE_DISABLE
if [ "$CONFIG_CPU_DISABLE_DCACHE" = "n" ]; then
bool 'Force write through D-cache' CONFIG_CPU_DCACHE_WRITETHROUGH
fi
fi
if [ "$CONFIG_CPU_ARM926T" = "y" -o "$CONFIG_CPU_ARM1020" = "y" ]; then
if [ "$CONFIG_CPU_ICACHE_DISABLE" = "n" -o "$CONFIG_CPU_DCACHE_DISABLE" = "n" ]; then
bool 'Round robin I and D cache replacement algorithm' CONFIG_CPU_CACHE_ROUND_ROBIN
fi
fi
if [ "$CONFIG_CPU_ARM1020" = "y" ]; then
bool 'Disable branch prediction' CONFIG_CPU_BPREDICT_DISABLE
fi
endmenu
mainmenu_option next_comment
comment 'General setup'
# Select various configuration options depending on the machine type # Select various configuration options depending on the machine type
if [ "$CONFIG_ARCH_EDB7211" = "y" -o \ if [ "$CONFIG_ARCH_EDB7211" = "y" -o \
...@@ -386,11 +378,6 @@ else ...@@ -386,11 +378,6 @@ else
define_bool CONFIG_DISCONTIGMEM n define_bool CONFIG_DISCONTIGMEM n
fi fi
endmenu
mainmenu_option next_comment
comment 'General setup'
# Now handle the bus types # Now handle the bus types
if [ "$CONFIG_ARCH_FTVPCI" = "y" -o \ if [ "$CONFIG_ARCH_FTVPCI" = "y" -o \
"$CONFIG_ARCH_SHARK" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \
......
arch/arm/mm/proc-arm1020.S
View file @ 9f1a2068
This diff is collapsed.
arch/arm/mm/proc-arm6,7.S
View file @ 9f1a2068
...@@ -43,8 +43,6 @@ ENTRY(cpu_arm6_dcache_clean_page) ...@@ -43,8 +43,6 @@ ENTRY(cpu_arm6_dcache_clean_page)
ENTRY(cpu_arm7_dcache_clean_page) ENTRY(cpu_arm7_dcache_clean_page)
ENTRY(cpu_arm6_dcache_clean_entry) ENTRY(cpu_arm6_dcache_clean_entry)
ENTRY(cpu_arm7_dcache_clean_entry) ENTRY(cpu_arm7_dcache_clean_entry)
ENTRY(cpu_arm6_flush_ram_page)
ENTRY(cpu_arm7_flush_ram_page)
mov pc, lr mov pc, lr
/* /*
...@@ -358,7 +356,6 @@ ENTRY(arm6_processor_functions) ...@@ -358,7 +356,6 @@ ENTRY(arm6_processor_functions)
/* cache */ /* cache */
.word cpu_arm6_cache_clean_invalidate_all .word cpu_arm6_cache_clean_invalidate_all
.word cpu_arm6_cache_clean_invalidate_range .word cpu_arm6_cache_clean_invalidate_range
.word cpu_arm6_flush_ram_page
/* dcache */ /* dcache */
.word cpu_arm6_dcache_invalidate_range .word cpu_arm6_dcache_invalidate_range
...@@ -393,7 +390,6 @@ ENTRY(arm7_processor_functions) ...@@ -393,7 +390,6 @@ ENTRY(arm7_processor_functions)
/* cache */ /* cache */
.word cpu_arm7_cache_clean_invalidate_all .word cpu_arm7_cache_clean_invalidate_all
.word cpu_arm7_cache_clean_invalidate_range .word cpu_arm7_cache_clean_invalidate_range
.word cpu_arm7_flush_ram_page
/* dcache */ /* dcache */
.word cpu_arm7_dcache_invalidate_range .word cpu_arm7_dcache_invalidate_range
......
arch/arm/mm/proc-arm720.S
View file @ 9f1a2068
...@@ -63,7 +63,6 @@ ENTRY(cpu_arm720_dcache_invalidate_range) ...@@ -63,7 +63,6 @@ ENTRY(cpu_arm720_dcache_invalidate_range)
ENTRY(cpu_arm720_dcache_clean_range) ENTRY(cpu_arm720_dcache_clean_range)
ENTRY(cpu_arm720_dcache_clean_page) ENTRY(cpu_arm720_dcache_clean_page)
ENTRY(cpu_arm720_dcache_clean_entry) ENTRY(cpu_arm720_dcache_clean_entry)
ENTRY(cpu_arm720_flush_ram_page)
mov pc, lr mov pc, lr
/* /*
...@@ -211,7 +210,6 @@ ENTRY(arm720_processor_functions) ...@@ -211,7 +210,6 @@ ENTRY(arm720_processor_functions)
/* cache */ /* cache */
.word cpu_arm720_cache_clean_invalidate_all .word cpu_arm720_cache_clean_invalidate_all
.word cpu_arm720_cache_clean_invalidate_range .word cpu_arm720_cache_clean_invalidate_range
.word cpu_arm720_flush_ram_page
/* dcache */ /* dcache */
.word cpu_arm720_dcache_invalidate_range .word cpu_arm720_dcache_invalidate_range
......
arch/arm/mm/proc-arm920.S
View file @ 9f1a2068
...@@ -21,6 +21,8 @@ ...@@ -21,6 +21,8 @@
* *
* These are the low level assembler for performing cache and TLB * These are the low level assembler for performing cache and TLB
* functions on the arm920. * functions on the arm920.
*
* CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
*/ */
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/config.h> #include <linux/config.h>
...@@ -106,9 +108,7 @@ ENTRY(cpu_arm920_reset) ...@@ -106,9 +108,7 @@ ENTRY(cpu_arm920_reset)
*/ */
.align 5 .align 5
ENTRY(cpu_arm920_do_idle) ENTRY(cpu_arm920_do_idle)
#if defined(CONFIG_CPU_ARM920_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#endif
mov pc, lr mov pc, lr
/* ================================= CACHE ================================ */ /* ================================= CACHE ================================ */
...@@ -127,7 +127,7 @@ ENTRY(cpu_arm920_cache_clean_invalidate_all) ...@@ -127,7 +127,7 @@ ENTRY(cpu_arm920_cache_clean_invalidate_all)
mov r2, #1 mov r2, #1
cpu_arm920_cache_clean_invalidate_all_r2: cpu_arm920_cache_clean_invalidate_all_r2:
mov ip, #0 mov ip, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else #else
/* /*
...@@ -165,7 +165,7 @@ ENTRY(cpu_arm920_cache_clean_invalidate_range) ...@@ -165,7 +165,7 @@ ENTRY(cpu_arm920_cache_clean_invalidate_range)
cmp r3, #MAX_AREA_SIZE cmp r3, #MAX_AREA_SIZE
bgt cpu_arm920_cache_clean_invalidate_all_r2 bgt cpu_arm920_cache_clean_invalidate_all_r2
1: teq r2, #0 1: teq r2, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE add r0, r0, #DCACHELINESIZE
...@@ -186,32 +186,6 @@ ENTRY(cpu_arm920_cache_clean_invalidate_range) ...@@ -186,32 +186,6 @@ ENTRY(cpu_arm920_cache_clean_invalidate_range)
mcr p15, 0, r1, c7, c10, 4 @ drain WB mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr mov pc, lr
/*
* cpu_arm920_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm920_flush_ram_page)
mov r1, #PAGESIZE
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */ /* ================================ D-CACHE =============================== */
/* /*
...@@ -227,7 +201,7 @@ ENTRY(cpu_arm920_flush_ram_page) ...@@ -227,7 +201,7 @@ ENTRY(cpu_arm920_flush_ram_page)
*/ */
.align 5 .align 5
ENTRY(cpu_arm920_dcache_invalidate_range) ENTRY(cpu_arm920_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1 tst r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1 tst r1, #DCACHELINESIZE - 1
...@@ -253,7 +227,7 @@ ENTRY(cpu_arm920_dcache_invalidate_range) ...@@ -253,7 +227,7 @@ ENTRY(cpu_arm920_dcache_invalidate_range)
*/ */
.align 5 .align 5
ENTRY(cpu_arm920_dcache_clean_range) ENTRY(cpu_arm920_dcache_clean_range)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1 bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0 sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE cmp r1, #MAX_AREA_SIZE
...@@ -286,7 +260,7 @@ ENTRY(cpu_arm920_dcache_clean_range) ...@@ -286,7 +260,7 @@ ENTRY(cpu_arm920_dcache_clean_range)
*/ */
.align 5 .align 5
ENTRY(cpu_arm920_dcache_clean_page) ENTRY(cpu_arm920_dcache_clean_page)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r1, #PAGESIZE mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE add r0, r0, #DCACHELINESIZE
...@@ -307,7 +281,7 @@ ENTRY(cpu_arm920_dcache_clean_page) ...@@ -307,7 +281,7 @@ ENTRY(cpu_arm920_dcache_clean_page)
*/ */
.align 5 .align 5
ENTRY(cpu_arm920_dcache_clean_entry) ENTRY(cpu_arm920_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif #endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB mcr p15, 0, r0, c7, c10, 4 @ drain WB
...@@ -370,7 +344,7 @@ ENTRY(cpu_arm920_icache_invalidate_page) ...@@ -370,7 +344,7 @@ ENTRY(cpu_arm920_icache_invalidate_page)
.align 5 .align 5
ENTRY(cpu_arm920_set_pgd) ENTRY(cpu_arm920_set_pgd)
mov ip, #0 mov ip, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */ /* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else #else
...@@ -403,7 +377,7 @@ ENTRY(cpu_arm920_set_pgd) ...@@ -403,7 +377,7 @@ ENTRY(cpu_arm920_set_pgd)
*/ */
.align 5 .align 5
ENTRY(cpu_arm920_set_pmd) ENTRY(cpu_arm920_set_pmd)
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit biceq r1, r1, #4 @ clear bufferable bit
...@@ -439,7 +413,7 @@ ENTRY(cpu_arm920_set_pte) ...@@ -439,7 +413,7 @@ ENTRY(cpu_arm920_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young? tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0 movne r2, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page? eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b tst r3, #0x0b
biceq r2, r2, #4 biceq r2, r2, #4
...@@ -455,15 +429,12 @@ cpu_manu_name: ...@@ -455,15 +429,12 @@ cpu_manu_name:
.asciz "ARM/CIRRUS" .asciz "ARM/CIRRUS"
ENTRY(cpu_arm920_name) ENTRY(cpu_arm920_name)
.ascii "Arm920T" .ascii "Arm920T"
#if defined(CONFIG_CPU_ARM920_CPU_IDLE) #ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM920_I_CACHE_ON)
.ascii "i" .ascii "i"
#endif #endif
#if defined(CONFIG_CPU_ARM920_D_CACHE_ON) #ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d" .ascii "d"
#if defined(CONFIG_CPU_ARM920_WRITETHROUGH) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)" .ascii "(wt)"
#else #else
.ascii "(wb)" .ascii "(wb)"
...@@ -497,10 +468,10 @@ __arm920_setup: ...@@ -497,10 +468,10 @@ __arm920_setup:
orr r0, r0, #0x0031 orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifdef CONFIG_CPU_ARM920_D_CACHE_ON #ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1.. orr r0, r0, #0x0004 @ .... .... .... .1..
#endif #endif
#ifdef CONFIG_CPU_ARM920_I_CACHE_ON #ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... .... orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif #endif
mov pc, lr mov pc, lr
...@@ -523,7 +494,6 @@ arm920_processor_functions: ...@@ -523,7 +494,6 @@ arm920_processor_functions:
/* cache */ /* cache */
.word cpu_arm920_cache_clean_invalidate_all .word cpu_arm920_cache_clean_invalidate_all
.word cpu_arm920_cache_clean_invalidate_range .word cpu_arm920_cache_clean_invalidate_range
.word cpu_arm920_flush_ram_page
/* dcache */ /* dcache */
.word cpu_arm920_dcache_invalidate_range .word cpu_arm920_dcache_invalidate_range
......
arch/arm/mm/proc-arm922.S
View file @ 9f1a2068
...@@ -22,6 +22,8 @@ ...@@ -22,6 +22,8 @@
* *
* These are the low level assembler for performing cache and TLB * These are the low level assembler for performing cache and TLB
* functions on the arm922. * functions on the arm922.
*
* CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
*/ */
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/config.h> #include <linux/config.h>
...@@ -107,9 +109,7 @@ ENTRY(cpu_arm922_reset) ...@@ -107,9 +109,7 @@ ENTRY(cpu_arm922_reset)
*/ */
.align 5 .align 5
ENTRY(cpu_arm922_do_idle) ENTRY(cpu_arm922_do_idle)
#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#endif
mov pc, lr mov pc, lr
/* ================================= CACHE ================================ */ /* ================================= CACHE ================================ */
...@@ -128,7 +128,7 @@ ENTRY(cpu_arm922_cache_clean_invalidate_all) ...@@ -128,7 +128,7 @@ ENTRY(cpu_arm922_cache_clean_invalidate_all)
mov r2, #1 mov r2, #1
cpu_arm922_cache_clean_invalidate_all_r2: cpu_arm922_cache_clean_invalidate_all_r2:
mov ip, #0 mov ip, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else #else
/* /*
...@@ -166,7 +166,7 @@ ENTRY(cpu_arm922_cache_clean_invalidate_range) ...@@ -166,7 +166,7 @@ ENTRY(cpu_arm922_cache_clean_invalidate_range)
cmp r3, #MAX_AREA_SIZE cmp r3, #MAX_AREA_SIZE
bgt cpu_arm922_cache_clean_invalidate_all_r2 bgt cpu_arm922_cache_clean_invalidate_all_r2
1: teq r2, #0 1: teq r2, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE add r0, r0, #DCACHELINESIZE
...@@ -187,32 +187,6 @@ ENTRY(cpu_arm922_cache_clean_invalidate_range) ...@@ -187,32 +187,6 @@ ENTRY(cpu_arm922_cache_clean_invalidate_range)
mcr p15, 0, r1, c7, c10, 4 @ drain WB mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr mov pc, lr
/*
* cpu_arm922_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm922_flush_ram_page)
mov r1, #PAGESIZE
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */ /* ================================ D-CACHE =============================== */
/* /*
...@@ -228,7 +202,7 @@ ENTRY(cpu_arm922_flush_ram_page) ...@@ -228,7 +202,7 @@ ENTRY(cpu_arm922_flush_ram_page)
*/ */
.align 5 .align 5
ENTRY(cpu_arm922_dcache_invalidate_range) ENTRY(cpu_arm922_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1 tst r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1 tst r1, #DCACHELINESIZE - 1
...@@ -254,7 +228,7 @@ ENTRY(cpu_arm922_dcache_invalidate_range) ...@@ -254,7 +228,7 @@ ENTRY(cpu_arm922_dcache_invalidate_range)
*/ */
.align 5 .align 5
ENTRY(cpu_arm922_dcache_clean_range) ENTRY(cpu_arm922_dcache_clean_range)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1 bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0 sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE cmp r1, #MAX_AREA_SIZE
...@@ -287,7 +261,7 @@ ENTRY(cpu_arm922_dcache_clean_range) ...@@ -287,7 +261,7 @@ ENTRY(cpu_arm922_dcache_clean_range)
*/ */
.align 5 .align 5
ENTRY(cpu_arm922_dcache_clean_page) ENTRY(cpu_arm922_dcache_clean_page)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r1, #PAGESIZE mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE add r0, r0, #DCACHELINESIZE
...@@ -308,7 +282,7 @@ ENTRY(cpu_arm922_dcache_clean_page) ...@@ -308,7 +282,7 @@ ENTRY(cpu_arm922_dcache_clean_page)
*/ */
.align 5 .align 5
ENTRY(cpu_arm922_dcache_clean_entry) ENTRY(cpu_arm922_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif #endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB mcr p15, 0, r0, c7, c10, 4 @ drain WB
...@@ -371,7 +345,7 @@ ENTRY(cpu_arm922_icache_invalidate_page) ...@@ -371,7 +345,7 @@ ENTRY(cpu_arm922_icache_invalidate_page)
.align 5 .align 5
ENTRY(cpu_arm922_set_pgd) ENTRY(cpu_arm922_set_pgd)
mov ip, #0 mov ip, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */ /* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else #else
...@@ -404,7 +378,7 @@ ENTRY(cpu_arm922_set_pgd) ...@@ -404,7 +378,7 @@ ENTRY(cpu_arm922_set_pgd)
*/ */
.align 5 .align 5
ENTRY(cpu_arm922_set_pmd) ENTRY(cpu_arm922_set_pmd)
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit biceq r1, r1, #4 @ clear bufferable bit
...@@ -440,7 +414,7 @@ ENTRY(cpu_arm922_set_pte) ...@@ -440,7 +414,7 @@ ENTRY(cpu_arm922_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young? tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0 movne r2, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page? eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b tst r3, #0x0b
biceq r2, r2, #4 biceq r2, r2, #4
...@@ -456,15 +430,12 @@ cpu_manu_name: ...@@ -456,15 +430,12 @@ cpu_manu_name:
.asciz "ARM/ALTERA" .asciz "ARM/ALTERA"
ENTRY(cpu_arm922_name) ENTRY(cpu_arm922_name)
.ascii "Arm922T" .ascii "Arm922T"
#if defined(CONFIG_CPU_ARM922_CPU_IDLE) #ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM922_I_CACHE_ON)
.ascii "i" .ascii "i"
#endif #endif
#if defined(CONFIG_CPU_ARM922_D_CACHE_ON) #ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d" .ascii "d"
#if defined(CONFIG_CPU_ARM922_WRITETHROUGH) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)" .ascii "(wt)"
#else #else
.ascii "(wb)" .ascii "(wb)"
...@@ -498,10 +469,10 @@ __arm922_setup: ...@@ -498,10 +469,10 @@ __arm922_setup:
orr r0, r0, #0x0031 orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifdef CONFIG_CPU_ARM922_D_CACHE_ON #ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1.. orr r0, r0, #0x0004 @ .... .... .... .1..
#endif #endif
#ifdef CONFIG_CPU_ARM922_I_CACHE_ON #ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... .... orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif #endif
mov pc, lr mov pc, lr
...@@ -524,7 +495,6 @@ arm922_processor_functions: ...@@ -524,7 +495,6 @@ arm922_processor_functions:
/* cache */ /* cache */
.word cpu_arm922_cache_clean_invalidate_all .word cpu_arm922_cache_clean_invalidate_all
.word cpu_arm922_cache_clean_invalidate_range .word cpu_arm922_cache_clean_invalidate_range
.word cpu_arm922_flush_ram_page
/* dcache */ /* dcache */
.word cpu_arm922_dcache_invalidate_range .word cpu_arm922_dcache_invalidate_range
......
arch/arm/mm/proc-arm926.S
View file @ 9f1a2068
...@@ -21,6 +21,8 @@ ...@@ -21,6 +21,8 @@
* *
* These are the low level assembler for performing cache and TLB * These are the low level assembler for performing cache and TLB
* functions on the arm926. * functions on the arm926.
*
* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
*/ */
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/config.h> #include <linux/config.h>
...@@ -52,45 +54,6 @@ ...@@ -52,45 +54,6 @@
.text .text
/*
* cpu_arm926_data_abort()
*
* obtain information about current aborted instruction
* Note: we read user space. This means we might cause a data
* abort here if the I-TLB and D-TLB aren't seeing the same
* picture. Unfortunately, this does happen. We live with it.
*
* Inputs:
* r2 = address of abort
* r3 = cpsr of abort
*
* Returns:
* r0 = address of abort
* r1 != 0 if writing
* r3 = FSR
* r4 = corrupted
*/
.align 5
ENTRY(cpu_arm926_data_abort)
mrc p15, 0, r0, c6, c0, 0 @ get FAR
mrc p15, 0, r4, c5, c0, 0 @ get FSR
tst r1, #1<<24 @ Check for Jbit (NE -> found)
movne r1, #-1 @ Mark as writing
bne 2f
tst r3, #1<<5 @ Check for Thumb-bit (NE -> found)
ldrneh r1, [r2] @ Read aborted Thumb instruction
tstne r1, r1, lsr #12 @ C = bit 11
ldreq r1, [r2] @ Read aborted ARM instruction
tsteq r1, r1, lsr #21 @ C = bit 20
sbc r1, r1, r1 @ r1 = C - 1
2:
and r3, r4, #255
mov pc, lr
/* /*
* cpu_arm926_check_bugs() * cpu_arm926_check_bugs()
*/ */
...@@ -146,9 +109,7 @@ ENTRY(cpu_arm926_reset) ...@@ -146,9 +109,7 @@ ENTRY(cpu_arm926_reset)
*/ */
.align 5 .align 5
ENTRY(cpu_arm926_do_idle) ENTRY(cpu_arm926_do_idle)
#if defined(CONFIG_CPU_ARM926_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#endif
mov pc, lr mov pc, lr
/* ================================= CACHE ================================ */ /* ================================= CACHE ================================ */
...@@ -167,7 +128,7 @@ ENTRY(cpu_arm926_cache_clean_invalidate_all) ...@@ -167,7 +128,7 @@ ENTRY(cpu_arm926_cache_clean_invalidate_all)
mov r2, #1 mov r2, #1
cpu_arm926_cache_clean_invalidate_all_r2: cpu_arm926_cache_clean_invalidate_all_r2:
mov ip, #0 mov ip, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else #else
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
...@@ -203,7 +164,7 @@ ENTRY(cpu_arm926_cache_clean_invalidate_range) ...@@ -203,7 +164,7 @@ ENTRY(cpu_arm926_cache_clean_invalidate_range)
bgt cpu_arm926_cache_clean_invalidate_all_r2 bgt cpu_arm926_cache_clean_invalidate_all_r2
1: teq r2, #0 1: teq r2, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE add r0, r0, #DCACHELINESIZE
...@@ -226,32 +187,6 @@ ENTRY(cpu_arm926_cache_clean_invalidate_range) ...@@ -226,32 +187,6 @@ ENTRY(cpu_arm926_cache_clean_invalidate_range)
mov pc, lr mov pc, lr
/*
* cpu_arm926_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm926_flush_ram_page)
mov r1, #PAGESIZE
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */ /* ================================ D-CACHE =============================== */
/* /*
...@@ -267,7 +202,7 @@ ENTRY(cpu_arm926_flush_ram_page) ...@@ -267,7 +202,7 @@ ENTRY(cpu_arm926_flush_ram_page)
*/ */
.align 5 .align 5
ENTRY(cpu_arm926_dcache_invalidate_range) ENTRY(cpu_arm926_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1 tst r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1 tst r1, #DCACHELINESIZE - 1
...@@ -293,7 +228,7 @@ ENTRY(cpu_arm926_dcache_invalidate_range) ...@@ -293,7 +228,7 @@ ENTRY(cpu_arm926_dcache_invalidate_range)
*/ */
.align 5 .align 5
ENTRY(cpu_arm926_dcache_clean_range) ENTRY(cpu_arm926_dcache_clean_range)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1 bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0 sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE cmp r1, #MAX_AREA_SIZE
...@@ -326,7 +261,7 @@ ENTRY(cpu_arm926_dcache_clean_range) ...@@ -326,7 +261,7 @@ ENTRY(cpu_arm926_dcache_clean_range)
*/ */
.align 5 .align 5
ENTRY(cpu_arm926_dcache_clean_page) ENTRY(cpu_arm926_dcache_clean_page)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r1, #PAGESIZE mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE add r0, r0, #DCACHELINESIZE
...@@ -347,7 +282,7 @@ ENTRY(cpu_arm926_dcache_clean_page) ...@@ -347,7 +282,7 @@ ENTRY(cpu_arm926_dcache_clean_page)
*/ */
.align 5 .align 5
ENTRY(cpu_arm926_dcache_clean_entry) ENTRY(cpu_arm926_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif #endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB mcr p15, 0, r0, c7, c10, 4 @ drain WB
...@@ -399,7 +334,7 @@ ENTRY(cpu_arm926_icache_invalidate_page) ...@@ -399,7 +334,7 @@ ENTRY(cpu_arm926_icache_invalidate_page)
.align 5 .align 5
ENTRY(cpu_arm926_set_pgd) ENTRY(cpu_arm926_set_pgd)
mov ip, #0 mov ip, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */ /* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else #else
...@@ -424,13 +359,13 @@ ENTRY(cpu_arm926_set_pgd) ...@@ -424,13 +359,13 @@ ENTRY(cpu_arm926_set_pgd)
*/ */
.align 5 .align 5
ENTRY(cpu_arm926_set_pmd) ENTRY(cpu_arm926_set_pmd)
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit biceq r1, r1, #4 @ clear bufferable bit
#endif #endif
str r1, [r0] str r1, [r0]
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif #endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB mcr p15, 0, r0, c7, c10, 4 @ drain WB
...@@ -462,14 +397,14 @@ ENTRY(cpu_arm926_set_pte) ...@@ -462,14 +397,14 @@ ENTRY(cpu_arm926_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young? tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0 movne r2, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page? eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b tst r3, #0x0b
biceq r2, r2, #4 biceq r2, r2, #4
#endif #endif
str r2, [r0] @ hardware version str r2, [r0] @ hardware version
mov r0, r0 mov r0, r0
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif #endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB mcr p15, 0, r0, c7, c10, 4 @ drain WB
...@@ -480,20 +415,17 @@ cpu_manu_name: ...@@ -480,20 +415,17 @@ cpu_manu_name:
.asciz "ARM" .asciz "ARM"
ENTRY(cpu_arm926_name) ENTRY(cpu_arm926_name)
.ascii "ARM926EJ-S" .ascii "ARM926EJ-S"
#if defined(CONFIG_CPU_ARM926_CPU_IDLE) #ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM926_I_CACHE_ON)
.ascii "i" .ascii "i"
#endif #endif
#if defined(CONFIG_CPU_ARM926_D_CACHE_ON) #ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d" .ascii "d"
#if defined(CONFIG_CPU_ARM926_WRITETHROUGH) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)" .ascii "(wt)"
#else #else
.ascii "(wb)" .ascii "(wb)"
#endif #endif
#ifdef CONFIG_CPU_ARM926_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR" .ascii "RR"
#endif #endif
#endif #endif
...@@ -510,7 +442,7 @@ __arm926_setup: ...@@ -510,7 +442,7 @@ __arm926_setup:
mcr p15, 0, r4, c2, c0 @ load page table pointer mcr p15, 0, r4, c2, c0 @ load page table pointer
#if defined(CONFIG_CPU_ARM926_WRITETHROUGH) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ disable write-back on caches explicitly mov r0, #4 @ disable write-back on caches explicitly
mcr p15, 7, r0, c15, c0, 0 mcr p15, 7, r0, c15, c0, 0
#endif #endif
...@@ -532,13 +464,13 @@ __arm926_setup: ...@@ -532,13 +464,13 @@ __arm926_setup:
orr r0, r0, #0x0031 orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifdef CONFIG_CPU_ARM926_ROUND_ROBIN #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... .... orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif #endif
#ifdef CONFIG_CPU_ARM926_D_CACHE_ON #ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1.. orr r0, r0, #0x0004 @ .... .... .... .1..
#endif #endif
#ifdef CONFIG_CPU_ARM926_I_CACHE_ON #ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... .... orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif #endif
mov pc, lr mov pc, lr
...@@ -561,7 +493,6 @@ arm926_processor_functions: ...@@ -561,7 +493,6 @@ arm926_processor_functions:
/* cache */ /* cache */
.word cpu_arm926_cache_clean_invalidate_all .word cpu_arm926_cache_clean_invalidate_all
.word cpu_arm926_cache_clean_invalidate_range .word cpu_arm926_cache_clean_invalidate_range
.word cpu_arm926_flush_ram_page
/* dcache */ /* dcache */
.word cpu_arm926_dcache_invalidate_range .word cpu_arm926_dcache_invalidate_range
......
arch/arm/mm/proc-macros.S
View file @ 9f1a2068
...@@ -21,6 +21,11 @@ ...@@ -21,6 +21,11 @@
ldr \rd, [\rn, #VMA_VM_FLAGS] ldr \rd, [\rn, #VMA_VM_FLAGS]
.endm .endm
.macro tsk_mm, rd, rn
ldr \rd, [\rn, #TI_TASK]
ldr \rd, [\rd, #TSK_ACTIVE_MM]
.endm
/* /*
* act_mm - get current->active_mm * act_mm - get current->active_mm
*/ */
......
arch/arm/mm/proc-sa110.S
View file @ 9f1a2068
...@@ -262,26 +262,6 @@ ENTRY(cpu_sa1100_cache_clean_invalidate_range) ...@@ -262,26 +262,6 @@ ENTRY(cpu_sa1100_cache_clean_invalidate_range)
bhi cpu_sa1100_cache_clean_invalidate_all_r2 bhi cpu_sa1100_cache_clean_invalidate_all_r2
b 1b b 1b
/*
* cpu_sa110_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_sa110_flush_ram_page)
ENTRY(cpu_sa1100_flush_ram_page)
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */ /* ================================ D-CACHE =============================== */
/* /*
...@@ -550,7 +530,6 @@ ENTRY(sa110_processor_functions) ...@@ -550,7 +530,6 @@ ENTRY(sa110_processor_functions)
/* cache */ /* cache */
.word cpu_sa110_cache_clean_invalidate_all .word cpu_sa110_cache_clean_invalidate_all
.word cpu_sa110_cache_clean_invalidate_range .word cpu_sa110_cache_clean_invalidate_range
.word cpu_sa110_flush_ram_page
/* dcache */ /* dcache */
.word cpu_sa110_dcache_invalidate_range .word cpu_sa110_dcache_invalidate_range
...@@ -591,7 +570,6 @@ ENTRY(sa1100_processor_functions) ...@@ -591,7 +570,6 @@ ENTRY(sa1100_processor_functions)
/* cache */ /* cache */
.word cpu_sa1100_cache_clean_invalidate_all .word cpu_sa1100_cache_clean_invalidate_all
.word cpu_sa1100_cache_clean_invalidate_range .word cpu_sa1100_cache_clean_invalidate_range
.word cpu_sa1100_flush_ram_page
/* dcache */ /* dcache */
.word cpu_sa1100_dcache_invalidate_range .word cpu_sa1100_dcache_invalidate_range
......
arch/arm/mm/proc-syms.c
View file @ 9f1a2068
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#ifndef MULTI_CPU #ifndef MULTI_CPU
EXPORT_SYMBOL(cpu_cache_clean_invalidate_all); EXPORT_SYMBOL(cpu_cache_clean_invalidate_all);
EXPORT_SYMBOL(cpu_cache_clean_invalidate_range); EXPORT_SYMBOL(cpu_cache_clean_invalidate_range);
EXPORT_SYMBOL(cpu_flush_ram_page);
EXPORT_SYMBOL(cpu_dcache_clean_page); EXPORT_SYMBOL(cpu_dcache_clean_page);
EXPORT_SYMBOL(cpu_dcache_clean_entry); EXPORT_SYMBOL(cpu_dcache_clean_entry);
EXPORT_SYMBOL(cpu_dcache_clean_range); EXPORT_SYMBOL(cpu_dcache_clean_range);
......
include/asm-arm/cpu-multi32.h
View file @ 9f1a2068
...@@ -56,10 +56,6 @@ extern struct processor { ...@@ -56,10 +56,6 @@ extern struct processor {
* flush a specific page or pages * flush a specific page or pages
*/ */
void (*clean_invalidate_range)(unsigned long address, unsigned long end, int flags); void (*clean_invalidate_range)(unsigned long address, unsigned long end, int flags);
/*
* flush a page to RAM
*/
void (*_flush_ram_page)(void *virt_page);
} cache; } cache;
struct { /* D-cache */ struct { /* D-cache */
...@@ -121,7 +117,6 @@ extern const struct processor sa110_processor_functions; ...@@ -121,7 +117,6 @@ extern const struct processor sa110_processor_functions;
#define cpu_cache_clean_invalidate_all() processor.cache.clean_invalidate_all() #define cpu_cache_clean_invalidate_all() processor.cache.clean_invalidate_all()
#define cpu_cache_clean_invalidate_range(s,e,f) processor.cache.clean_invalidate_range(s,e,f) #define cpu_cache_clean_invalidate_range(s,e,f) processor.cache.clean_invalidate_range(s,e,f)
#define cpu_flush_ram_page(vp) processor.cache._flush_ram_page(vp)
#define cpu_dcache_clean_page(vp) processor.dcache.clean_page(vp) #define cpu_dcache_clean_page(vp) processor.dcache.clean_page(vp)
#define cpu_dcache_clean_entry(addr) processor.dcache.clean_entry(addr) #define cpu_dcache_clean_entry(addr) processor.dcache.clean_entry(addr)
......
include/asm-arm/cpu-single.h
View file @ 9f1a2068
...@@ -29,7 +29,6 @@ ...@@ -29,7 +29,6 @@
#define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle) #define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle)
#define cpu_cache_clean_invalidate_all __cpu_fn(CPU_NAME,_cache_clean_invalidate_all) #define cpu_cache_clean_invalidate_all __cpu_fn(CPU_NAME,_cache_clean_invalidate_all)
#define cpu_cache_clean_invalidate_range __cpu_fn(CPU_NAME,_cache_clean_invalidate_range) #define cpu_cache_clean_invalidate_range __cpu_fn(CPU_NAME,_cache_clean_invalidate_range)
#define cpu_flush_ram_page __cpu_fn(CPU_NAME,_flush_ram_page)
#define cpu_dcache_invalidate_range __cpu_fn(CPU_NAME,_dcache_invalidate_range) #define cpu_dcache_invalidate_range __cpu_fn(CPU_NAME,_dcache_invalidate_range)
#define cpu_dcache_clean_range __cpu_fn(CPU_NAME,_dcache_clean_range) #define cpu_dcache_clean_range __cpu_fn(CPU_NAME,_dcache_clean_range)
#define cpu_dcache_clean_page __cpu_fn(CPU_NAME,_dcache_clean_page) #define cpu_dcache_clean_page __cpu_fn(CPU_NAME,_dcache_clean_page)
...@@ -57,7 +56,6 @@ extern int cpu_do_idle(int mode); ...@@ -57,7 +56,6 @@ extern int cpu_do_idle(int mode);
extern void cpu_cache_clean_invalidate_all(void); extern void cpu_cache_clean_invalidate_all(void);
extern void cpu_cache_clean_invalidate_range(unsigned long address, unsigned long end, int flags); extern void cpu_cache_clean_invalidate_range(unsigned long address, unsigned long end, int flags);
extern void cpu_flush_ram_page(void *virt_page);
extern void cpu_dcache_invalidate_range(unsigned long start, unsigned long end); extern void cpu_dcache_invalidate_range(unsigned long start, unsigned long end);
extern void cpu_dcache_clean_range(unsigned long start, unsigned long end); extern void cpu_dcache_clean_range(unsigned long start, unsigned long end);
......
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